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IIR SIMD

Catalog Datasheet MFG & Type PDF Document Tags

implementing FIR and IIR digital filters

Abstract: FIR 3D AP-598 FIR and IIR Filtering using Streaming SIMD Extensions FIR and IIR Filtering using , IIR Filtering using Streaming SIMD Extensions Information in this document is provided in , Corporation 1998, 1999 02/04/99 AP-598 FIR and IIR Filtering using Streaming SIMD Extensions Table , . 6 02/04/99 iii AP-598 FIR and IIR Filtering using Streaming SIMD Extensions Revision , (Finite Impulse Response) and IIR (Infinite Impulse Response) filters. The Streaming SIMD Extensions
Intel
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implementing FIR and IIR digital filters FIR 3D FIR FILTER implementation in c language IIR FILTER implementation in c language iir filter applications IIR SIMD

IIR SIMD

Abstract: sharc iir filter SIMD FIR and SIMD IIR code that is attached. Complete source code for 64-bit-accurate FIR and IIR , /processors Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors Contributed by Brian M , the SHARC architecture performs long word (64-bit) accesses in SIMD mode. Lastly, it discusses the implementation of an extendedprecision FIR and IIR filter. Source files for the example filters are provided in , work in SIMD mode, how the VisualDSP+® tools work with 64-bit data, and how basic arithmetic
Analog Devices
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EE-270 EE-186 ADSP-21160 ADSP-21161 sharc iir filter 0xC0001 MRF transistor 0x123456789ABCDEF0 ADSP21160 ADSP-2116 ADSP2126 ADSP-2136

TSUM16

Abstract: S10-S12 Single Instruction, Multiple Data (SIMD) multiprocessing paradigm. SIMD support is mode selectable via , dual executions to memory. The ADSP-21160 in SIMD mode can take advantage of the instruction level , clocked ADSP-2106x DSP. 6,0'0RGHDQG,QVWUXFWLRQ6XSSRUW The ADSP-21160 provides SIMD support features , second set of compute units. Some of these additional SIMD support features include: Full second register file and alternate register set to support the second compute unit set, Useful SIMD extensions
Analog Devices
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TSUM16 S10-S12 dfkh interrupt in assembly for sharc ADSP-2106 908910206761537356617E-6 536743164E-7 737066277507114174E-12 160478446323816900E-9 250518708834705760E-7

hall effect 44e

Abstract: 44e hall effect . 2-120 iir , LIBRARY FOR ADSP-21XXX SIMD PROCESSORS DSP Run-Time Library Guide , Functions . 3-17 Implications of Using SIMD Mode , . 3-128 iir
Analog Devices
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hall effect 44e 44e hall effect DM 311 adsp20 Hall 44E block ifft

BIT 3713

Abstract: GP32 -4W Benchmarks Routines N-tap Block FIR N-tap Single Sample FIR N-tap Complex Block FIR N-tap LMS IIR 256 , 32-bit, saturating, 40-bit extended precision, fractional, SIMD l Wide range of addressing , SIMD arithmetic Code Density Instruction Level Parallelism Increase 2-byte IS, GP16 · 32
STMicroelectronics
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ST100 ST100-4W ST1000 BIT 3713 GP32 MOPS ST100-2W

Architecture of TMS320C64X

Abstract: SH76xx processor DSPs-typically used for FIR RISC/RISC chip filters, IIR filtering, convolution, VLIW vs , being made on the power front, with a few vendors targeting VLIW DSPs at the handset market. SIMD , SIMD for short. SIMD works extremely well in the sort of repetitive calculations used in multimedia signal processing. SIMD isn't an architecture but an architectural technique that can be used in VLIW , example, into two 16-bit or four 8-bit ones. Intel took a SIMD approach to add DSP capabilities to the
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Architecture of TMS320C64X SH76xx portable dvd player mp3 player one chip vs embedded powerpc 460 PXA255

ADSP-21489

Abstract: ADSP-21369 . 2-181 ifftN (SHARC SIMD Processors) . 2-185 iir , SIMD Mode . 2-24 Using Data in External Memory , . 2-65 cfft_mag (SHARC SIMD Processors) . 2-68 cfftN . 2-70 cfftN (SHARC SIMD Processors) . 2-74 cfftf (SHARC SIMD Processors) . 2-77 circindex
Analog Devices
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ADSP-21489 ADSP-21369 sharc ADSP-21xxx architecture ADSP-21489 user manual 21479 rfft

sharc 21xxx

Abstract: rfft . 2-174 ifftN (SHARC SIMD Processors) . 2-178 iir , Implications of Using SIMD Mode . 2-23 Documented Library Functions , . 2-61 cfft_mag (SHARC SIMD Processors) . 2-64 cfftN . 2-66 cfftN (SHARC SIMD Processors) . 2-70 cfftf (SHARC SIMD Processors) . 2-73 circindex
Analog Devices
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sharc 21xxx ADSP-21469 ADSP-21062 UTC 2241 CFFT128 adsp-210XX instruction set

sharc iir filter

Abstract: 7.1 theater system (finite impulse response), IIR (infinite impulse response), and FFT (fast fourier transform). The , next-generation audio systems as an example. ® Why Hardware Accelerators The FIR filters, IIR filters, and , filters, IIR filters, and FFTs. These operations form the basis of communication systems, medical , 450 MHz. By using SIMD (single-instruction multiple-data), the core can perform two MAC , processing power. The accelerators offload common signal processing operations-FIR filters, IIR filters
Analog Devices
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7.1 theater system sharc accelerator IIR pdf str 5643 5.1 home theatre circuit datasheet circuit for 7.1 home theatre system sharc iir filter IIR Accelerator ADSP-2146

intel 283

Abstract: IIR SIMD intel Workstation Applications of Streaming SIMD Extensions February 1999 W o r k s t a t i o n , .4 Streaming SIMD Extensions .5 SIMD Floating-Point Instructions .5 SIMD Performs Like Operations in Parallel , .6 SIMD Prefetch Instructions Hide Memory Latency
Intel
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intel 283 IIR SIMD intel Pentium III Developer

AD1896

Abstract: sharc accelerator IIR , multiple-data (SIMD) computational architecture On-chip memory-5 Mbits of on-chip RAM, 4 Mbits of on-chip , DPI PINS (14) FIR IIR 3/5 MLB DMA ARBITER LINK PORTS DPI ROUTING UNIT 4 , instruction set) execution support Single instruction multiple data (SIMD) architecture provides: Two , (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an , accelerator implements radix-2 complex/real input, complex output FFT with no core intervention IIR
Analog Devices
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ADSP-21462W ADSP21465W AD1896 CP-1201 ADSP-21465W ADSP-2146x SHARC Processor Hardware Reference ADSP-21462W/ADSP-21465W/ADSP-21467 48-BIT AD21462WBBZ3 324-B

IIR SIMD

Abstract: ADSP-21469 , multiple-data (SIMD) computational architecture On-chip memory-5 Mbits of on-chip RAM, 4 Mbits of on-chip , GPIO ASRC DPI PINS (14) FIR IIR 3/5 MLB DMA ARBITER LINK PORTS DPI ROUTING , (SIMD) architecture provides: Two computational processing elements Concurrent execution Code , units allows: Single cycle executions (with or without SIMD) of a multiply operation, an ALU operation , output FFT with no core intervention IIR accelerators perform dedicated IIR filtering with
Analog Devices
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t04 68 3 pin diode 0X0009 0x000B B-324-2 AD21465WBBZ3 AD21469WBBZ3 ADSP-21467KBZ-ENG ADSP-21469KBZ-ENG PR07809-0-1/09

GP32

Abstract: ST100 multimedia board ST Solutions for Embedded Applications ST100 DSP-MCU Cores High Performance DSP-MCU Core 32 bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW Supports arithmetic on 32 bit, saturating, 40 bit extended precision, fractional, SIMD 4 Gbytes unified data and program memory space , Block FIR N-tap Single Sample FIR N-tap Complex Block FIR N-tap LMS IIR 256-point Complex FFT
STMicroelectronics
Original
ST120 ST100 multimedia board memory bandwidth ST120-DSP 2000TM

ADSP-21469

Abstract: optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational , 225 MHz IOA(19) IOD(32) 7 16 DM DATA BUS 64 FFT/FIR/IIR accelerators PROCESSING ELEMENT , Single instruction multiple data (SIMD) architecture provides: Two computational processing elements , buses and computational units allows: Single cycle executions (with or without SIMD) of a mul tiply , implements radix-2 complex/real input, com plex output FFT with no core intervention FIR/IIR accelerators
Analog Devices
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MS-034-BAR-2 ADSP-21469KBZ-ENG2 PR07809-0-10/08

sharc accelerator IIR

Abstract: ADSP-21469 , multiple-data (SIMD) computational architecture On-chip memory-5 Mbits of on-chip RAM CORE PROCESSOR , ARBITER SPI PORT (2) TWO WIRE INTERFACE GPIO ASRC DPI PINS (14) FIR IIR LINK PORTS , instruction set) execution support Single instruction multiple data (SIMD) architecture provides: Two , (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an , accelerator implements radix-2 complex/real input, complex output FFT with no core intervention IIR
Analog Devices
Original
ADSP21469W ADSP-21469W ADSP-21469/ADSP-21469W PR07809-0-11/08

of architecture of ADSP21xxx SHARC processor

Abstract: adsp21xxx Arithmetic . 1-149 SIMD Support . 1-150 Using SIMD Mode with Multichannel Data . 1-151 Using SIMD Mode with Single-Channel Data . 1-152 Restrictions to Using SIMD , Constraints on Using SIMD C/C+ . 1-157 Impact of Anomaly #40 on SIMD . 1-158 Performance When Using SIMD C/C+ . 1-159 Examples Using SIMD C
Analog Devices
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of architecture of ADSP21xxx SHARC processor adsp21xxx syntax for writing the assembly codes in ADSP-210XX tools Architecture of adsp21xxx sharc processor TAG 8939 CI STR 3234

IIR SIMD

Abstract: pmx64 SIMD (single instruction multiple data) SHARC family of processors, featuring the Analog Devices Super Harvard architecture and an enhanced SIMD VISA (variable instruction size architecture) core , impulse response), IIR (infinite impulse response), and FFT (fast Fourier transform) algorithms without , each core memory access and DMA is random. There are also two channels of IIR filter running in the background on the dedicated IIR hardware accelerator unit. IDD-INPEAK VDD_INT supply current for peak
Analog Devices
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125OC pmx64 EE-348 ADSP-21467/9

76655

Abstract: IIR SIMD SHARC® family of processors. ADSP-21262 processors offer SIMD architecture and are equipped with , important feature of the ADSP-21262 processor is its SIMD architecture. The ADSP21262 has two parallel , float operand2[1024]; float result; { int j; Parallel Data Fetch and SIMD result = 0; ADSP , FIR/IIR filter loops, DCT, FFT, and other transforms. The above routines involve MAC operations on , approximately 1024 cycles to execute. The code can be structured further, allowing the compiler to use SIMD
Analog Devices
Original
EE-255 76655

sharc iir filter

Abstract: 4x4 multipliers single-instruction, multiple-data (SIMD) architecture. This approach significantly increases performance while , ) 90 us FIR Filter (per tap) 10 ns (1 cycle) IIR Filter (per biquad) 20 ns (2 cycles
Analog Devices
Original
4x4 multipliers how dsp is used in radar multiprocessing ADSP21100 fir filter design ADI 21100 ADSP-21100 ADSP2106 H3353-15-9/98

GHS linker file format

Abstract: BIT 3713 40- and 32-bit arithmetic SIMD (Packed Arithmetic 2 x 16-bit) Saturating (Clamping) and/or Rounding , addressing modes . SIMD arithmetic Ins t Pa ructi ral o leli n Le => Hig sm In vel cre hp erf , FIR 2N N-tap LMS 1.6N IIR 3 per Biquad 256 -point Complex FFT 3713 Block , Instruction Multiple Data (SIMD) arithmetic ST100 GP32 instruction set provides "customized primitives" for
STMicroelectronics
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GHS linker file format ST110 ST140 ST180 MCU2000 300MH
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