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IEEE-754

Catalog Datasheet MFG & Type PDF Document Tags

56800E

Abstract: ieee 754 User Manual ­ 56800E Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide , . 0.4 Freescale 56800E Family IEEE-754 Compliant Floating-Point Library User Guide 1 User , division the 56800E Family IEEE-754 Compliant Floating-Point Library 2 User Guide RCSL FP 1.0 - , use of the different floating-point features imposed by the IEEE-754 standard [1] is beyond the scope , : RCSL FP 1.0 - Rev. 0.4 Freescale 56800E Family IEEE-754 Compliant Floating-Point Library User
Freescale Semiconductor
Original
ieee 754

56800

Abstract: IEEE-754 User Manual ­ 56800 Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide , . 0.4 Freescale 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 1 User , division the 56800 Family IEEE-754 Compliant Floating-Point Library 2 User Guide RCSL FP 1.0 - Rev , use of the different floating-point features imposed by the IEEE-754 standard [1] is beyond the scope , : 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 3 User Guide ­ SA = 0 -
Freescale Semiconductor
Original
56800

IEEE754

Abstract: IEEE-754 IEEE754. 1.1 Target user The targe users are users who use Round to Nearest and request of completely agreement wiht IEEE754. 1.2 Phenomenon When a rounding mode of Round to Nearest is used, result of , number but underflow flag is set in IEEE754. This LSI does not set underflow flag in the above case , '3F00 0800) is executed. (1) IEEE754 Result : H'0080 0000 FPSCR : H'0004 300C (2) This LSI Result : H , ) IEEE754 Result : H'0010 0000 0000 0000 FPSCR : H'000C 300C (2) This LSI Result : H'0010 0000 0000 0000
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SH7750 SH7750S SH7750R SH7751 SH7751R H0080 H0004 Hitachi DSA00205 TN-SH7-448A/E

AP3E3000-2

Abstract: vhdl code 64 bit FPU GAISLER 4 GRFPU / GRFPU-FT 2 GRFPU - High-performance IEEE-754 Floating-point unit 2.1 , Standard for Binary Floating-Point Arithmetic (IEEE-754) and the SPARC V8 standard (IEEE-1754). Supported , details about GRFPU's implementation of the IEEE-754 standard including FP formats, operations, opcodes , , "GRFPU - High Performance IEEE-754 Floating-Point Unit" (available at www.gaisler.com). 2.2 , single or double precision format as defined in the IEEE754 standard with exception for denormalized
Aeroflex Gaisler
Original
AP3E3000-2 vhdl code 64 bit FPU leon3 4 bit binary multiplier Vhdl code leon3 processor vhdl SPARC 7 IEEE-STD-754

ieee754

Abstract: TRW LSI Products Notes IEEE-754 Format. Page J3 TMC3033-1 - Floating-Point ALU 32-Bit 10 8 0.21 0.2 , c C, V c C, A C, A C, V C, V C IEEE-754 Format. J3 TMC3200 TMC32Û1 TMC3202 TMC3210 , -Bit 32-Bit 10 8 16 20 0.16 0.16 0.3 0.3 IEEE-754 w/lnternal Accumulate. IEEE-754 w/Three Port I/O. 8M FLOP, M IL-STD -1750A. 2.5M FLÜP, IEEE-754 Format, J3 J17 J39 J57 hy.es i 2 G u
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C3202 TRW LSI Products ABMT TMC3032-1 32/34-B

k 2996

Abstract: vhdl code of floating point unit mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard , are available each clock cycle. Full IEEE-754 precision and accuracy are included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision real , analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the , flags settings. Result Composer - performs result rounding function, data alignment to IEEE-754
Digital Core Design
Original
k 2996 vhdl code of floating point unit example algorithm verilog ieee floating point verilog vhdl code for Clock divider for FPGA ieee floating point vhdl

RT3PE3000L-1

Abstract: ieee floating point multiplier vhdl 2009, Version 1.0.3 GAISLER 4 GRFPU / GRFPU-FT 2 GRFPU - High-performance IEEE-754 , defined in the IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754) and the SPARC V8 standard , "Functional description" gives details about GRFPU's implementation of the IEEE-754 standard including FP , details refer to the white paper, "GRFPU - High Performance IEEE-754 Floating-Point Unit" (available at , floating-point numbers in single or double precision format as defined in the IEEE754 standard with exception for
Aeroflex Gaisler
Original
RT3PE3000L-1 ieee floating point multiplier vhdl RTAX4000S vhdl code infinity microprocessor rtax4000

MUR1 crouzet 88826105

Abstract: PIC 32 bit -bit IEEE-754 standard FP format is used: r r r r r r Bit 31 = sign bit (0 = positive, 1 = , using IEEE-754-1985 format .text ; program memory .global _SPADD,_SPSUB,_addf,_subf ; entry labels , ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IEEE-754 32-bit SP Floating Point input argument 1 " " " " " " " 2 " " " " " output , IEEE-754-1985 format .text .global _SPDIV,_divf .align 32 arg1 arg2 ans exp1 exp2 sign , ; ; ; ; ; ; ; ; ; ; ; ; ; ; program memory ; entry labels ; Fetch Packet boundary IEEE-754 32-bit SP Floating Point input
Texas Instruments
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MUR1 crouzet 88826105 PIC 32 bit rts6201 FP 801 C6201 SPRA515 TMS320C62

ieee floating point multiplier vhdl

Abstract: ieee floating point multiplier verilog mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard , and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The , function, data alignment to IEEE-754 standard, and the final flags setting. PERFORMANCE The following
Digital Core Design
Original
FLEX10KE APEX20K APEX20KE APEX20KC ieee floating point multiplier verilog vhdl code for floating point multiplier verilog code for digital clock

ieee floating point vhdl

Abstract: floating point verilog DINT2FP Integer to Floating Point Pipelined Converter ver 2.32 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 , Embedded arithmetic coprocessor Data processing & control KEY FEATURES Full IEEE-754 , :0) en rst clk Arguments Checker - performs input data analyze against IEEE-754 number , performs result rounding function, and data alignment to IEEE-754 standard. PERFORMANCE PINS
Digital Core Design
Original
floating point verilog

vhdl code for floating point multiplier

Abstract: vhdl code complex multiplier mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard , and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included , KEY FEATURES Full IEEE-754 compliance Single precision real format support Simple , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , alignment to IEEE-754 standard, and the final flags setting. The following table gives a survey about the
Digital Core Design
Original
vhdl code complex multiplier vhdl complex multiplier verilog code for floating point unit digital clock vhdl code vhdl code for digital clock 78245

verilog code for floating point unit

Abstract: ieee floating point verilog Integer to Floating Point Pipelined Converter ver 2.31 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 , Data processing & control KEY FEATURES Full IEEE-754 compliance Double word integer , clk Arguments Checker - performs input data analyze against IEEE-754 number standard compliance , result rounding function, and data alignment to IEEE-754 standard. PERFORMANCE The following table
Digital Core Design
Original

vhdl code of floating point adder

Abstract: verilog code for floating point adder mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 , results are available each clock cycle. Full IEEE754 precision and accuracy were included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , IEEE-754 number standard compliance. The appropriate numbers and information about the input data , . Result Composer - performs result rounding function, data alignment to IEEE-754 standard, and the final
Digital Core Design
Original
vhdl code of floating point adder verilog code for floating point adder ieee 754 vhdl code of floating point adder vhdl code of pipelined adder vhdl code for floating point adder

vhdl code for Clock divider for FPGA

Abstract: verilog code divide mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard , are available each clock cycle. Full IEEE-754 precision and accuracy are included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate , , data alignment to IEEE-754 standard, and the final flags setting. PERFORMANCE The following table
Digital Core Design
Original
verilog code divide digital clock verilog code ARITHMETIC COPROCESSOR

verilog code for floating point unit

Abstract: ieee floating point verilog Floating Point To Integer Pipelined Converter ver 2.07 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 , IEEE-754 compliance Single precision real input numbers Double word output numbers(4 , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , to IEEE-754 standard, and the final flags setting. SYMBOL datai(31:0) datao(31:0) ofo ufo
Digital Core Design
Original

verilog code for floating point adder

Abstract: vhdl code for floating point adder algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard , are available each clock cycle. Full IEEE754 precision and accuracy were included. DELIVERABLES , processing & control KEY FEATURES Full IEEE-754 compliance Single precision real format , en rst clk Arguments Checker - performs input data analyze against IEEE-754 number standard , result rounding function, data alignment to IEEE-754 standard, and the final flags setting. The
Digital Core Design
Original
pipelined adder VHDL code for Real Time Clock 9071

example algorithm verilog

Abstract: vhdl code for digital clock Floating Point Pipelined Square Root Unit ver 2.07 OVERVIEW The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 , algorithms KEY FEATURES Full IEEE-754 compliance Single precision real format support , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , to IEEE-754 standard, and the final flags setting. PERFORMANCE datao(31:0) ofo ufo ifo en
Digital Core Design
Original

leon3 processor vhdl

Abstract: IEEE-1754 2008, Version 1.0.4 GAISLER 4 GRFPU Lite / GRFPU-FT Lite 2 GRFPU Lite - IEEE-754 , as defined in IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754) and SPARC V8 standard , precision format as defined in IEEE-754 standard. Copyright Aeroflex Gaisler AB December 2008 , floating-point unit detects all exceptions defined by the IEEE-754 standard. This includes detection of Invalid , rounding modes defined in the IEEE-754 standard are supported: round-to-nearest, round-to+inf
Aeroflex Gaisler
Original
RTAX2000S sparc v8 floatingpoint addition vhdl leon3 vhdl model VHDL code for floating point addition processor control unit vhdl code RTAX2000

vhdl code of floating point unit

Abstract: ieee floating point vhdl DFP2INT Floating Point To Integer Pipelined Converter ver 2.20 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 , support IP Core implementation support 3 months maintenance Full IEEE-754 compliance , ifo en rst clk Arguments Checker - performs input data analyze against IEEE-754 number , performs result rounding function, data alignment to IEEE-754 standard, and the final flags setting
Digital Core Design
Original

verilog code for floating point multiplication

Abstract: vhdl code for cordic cosine and sine input numbers format is according to IEEE-754 standard. DFPMU-DP supports double and single precision , No programming required IEEE-754 Double precision real format support ­ double type IEEE-754 , exponents and work registers. Align ­ performs the numbers analyze against IEEE-754 standard compliance , . IEEE-754 FP Instruction Addition Subtraction Multiplication Division Square Root Sine Cosine
Digital Core Design
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DP8051 verilog code for floating point multiplication vhdl code for cordic cosine and sine vhdl code for 8 bit floating point processor verilog code for cordic verilog code for single precision floating point multiplication verilog code for double precision floating point multiplication

Floating-Point Arithmetic

Abstract: 00FF -bit IEEE-754 standard FP format is used: r r r r r r Bit 31 = sign bit (0 = positive, 1 = , ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IEEE-754 32-bit SP Floating Point input argument 1 " " " " " " " 2 " " " " " output , ; ; ; ; ; ; ; ; ; ; ; ; ; ; program memory ; entry labels ; Fetch Packet boundary IEEE-754 32-bit SP Floating Point input , reserved. Syd Poland 03-23-98 (for TMS320C62xx DSPs) a4 -> a4 IEEE-754 short 32-bit SP Floating , ; program section ; entry labels ; start on fetch packet boundary ; ; ; ; ; ; ; ; input IEEE-754
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Floating-Point Arithmetic 00FF ADSP-2100

ARM11 instruction sets

Abstract: ARM Architecture Reference Manual User Manual ­ 56800 Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide , . 0.4 Freescale 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 1 User , division the 56800 Family IEEE-754 Compliant Floating-Point Library 2 User Guide RCSL FP 1.0 - Rev , use of the different floating-point features imposed by the IEEE-754 standard [1] is beyond the scope , : 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 3 User Guide ­ SA = 0 -
ARM
Original
VFP11 ARM11 instruction sets ARM Architecture Reference Manual ARM11 CP15 ARM11 Architecture Reference Manual 0274B

FLO32

Abstract: FLO24 GAISLER 4 GRFPU / GRFPU-FT 2 GRFPU - High-performance IEEE-754 Floating-point unit 2.1 , Standard for Binary Floating-Point Arithmetic (IEEE-754) and the SPARC V8 standard (IEEE-1754). Supported , details about GRFPU's implementation of the IEEE-754 standard including FP formats, operations, opcodes , , "GRFPU - High Performance IEEE-754 Floating-Point Unit" (available at www.gaisler.com). 2.2 , single or double precision format as defined in the IEEE754 standard with exception for denormalized
Microchip Technology
Original
AN575 FLO32 FLO24 FPA24 FPD32 FPM24 integer and floating point numbers PIC16/17 10F-1C

VFP10

Abstract: 0x40000005 specification, and the SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP (NS=1) mode , Exception (aexc) [Status Field, Readable and Writable] This field accumulates IEEE_754 floating-point , ) [Status Field, Readable and Writable] This field identifies IEEE_754 floating-point exceptions that were , without a trap, or when an FPop causes an IEEE_754_exception trap. Only one IEEE_754 exception is , fp_exception trap 1 5 IEEE_754_ exception IEEE 754 exceptions (nv, of, uf, dz, nx) 2 4
ARM
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VFP10 0x40000005 ARM10200 ARM10 ARM1020T VFP10TM

ARM11 processor

Abstract: ARM11 mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard , are available each clock cycle. Full IEEE-754 precision and accuracy are included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision real , analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the , flags settings. Result Composer - performs result rounding function, data alignment to IEEE-754
ARM
Original
ARM11 processor ARM11 "instruction set summary" ARMv5TE instruction set
Abstract: . 3-2 Compliance with IEEE-754 , IEEE754 for Inexact, Overflow, Invalid operation, and Divide-by-zero. The Underflow exception status bit , FCMP followed by an FMSTAT instruction. For more information See Compliance with IEEE-754 on page 3-4 -
OCR Scan
MB86936 E10-1 E10-2 E10-4 B86936
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