IDT88K8483 IDT7172604 VDDA25 88K8483 VDDC12 VDDH15 VDDH25 VDDL12 VDDL25 VDDT33 - Datasheet Archive

 

SPI-4 Exchange Document Issue 1.0 Description Features Functionality ­ Multiplexes logical ports (LPs) from SPI-4A and SPI-4B

 

IDT88K8483 IDT88K8483 SPI-4 Exchange Document Issue 1.0 Description Features Functionality ­ Multiplexes logical ports (LPs) from SPI-4A and SPI-4B to SPI4M ­ Optionally converts between interleaved packet transfers and whole packet transfers per logical port ­ Data redirection per LP between SPI-4A, SPI-4B and 10G FPGA ­ Per LP configurable memory allocation ­ Per LP memory expansion via QDR-II SRAM interface ­ 3 separate clock generators allowing fully flexible, fully integrated clock derivations and generation Standard Interfaces ­ Two OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range, 64 concurrently active LPs per interface ­ One OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range, 128 concurrently active LPs ­ SPI-4 FIFO status channel options: ­ LVDS full-rate, LVDS quarter-rate, LVTTL quarter-rate ­ SPI-4 compatible with Network Processor Streaming Interface (NPSI NPE-Framer mode of operation) ­ HSTL Interface with selectable operating mode 160 - 200 MHz DDR packet interface, 64 concurrently active LPs; or QDR-II memory interface: 160 - 200MHz HSTL ­ Serial or parallel microprocessor interface for control and monitoring ­ IEEE 1491.1 JTAG The IDT88K8483 IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4 Exchange devices build on IDT's proven SPI-4 implementation and packet fragment processor (PFP) design. The IDT88K8483 IDT88K8483 suits applications with slow backpressure response and other advanced networking applications when there is the need for duplicate ports to reroute data multiple times through the packet-exchange and temporary storage for complete in-flight packets. The data on each SPI-4 interface logical port (LP) are mapped to a logical identifier (LID). A data flow between logical port addresses on the various interfaces is accomplished using LID maps that can be dynamically reconfigured. The device enables the connection of two SPI-4 devices to a network processor having one or more SPI-4 interfaces. Up to 18Mbit of additional buffer memory can be provided using the QDRII interface. Alternatively, the HSTL I/O may be used to provide a generic packet interface to a FPGA. The device supports a maximum of 128 logical ports. Applications ­ ­ ­ ­ ­ ­ Ethernet transport SONET / SDH packet transport line cards Broadband aggregation Multi-service switches IP services equipment Security firewalls Block Diagram Auxiliary 10Gbps Interface Tributary SPI-4s QDR-II 10Gbps Memory int. SPI-4A 64 Logical Ports SPI-4B 64 Logical Ports 10Gbps FPGA Packet Int. Serial / 8bit MicroprocessorInterface Micro. Int. Packet Fragment Processor A-TM (PFP) Packet Fragment Processor A-MT (PFP) SPI-4M 128 Logical Ports Main SPI-4 Packet Fragment Processor B-TM (PFP) Packet Fragment Processor B-MT (PFP) JTAG Interface JTAG Int. Figure 1 IDT88K8483 IDT88K8483 Block Diagram IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 162 © 2006 Integrated Device Technology, Inc. October 20, 2006 DSC 6214/- IDT IDT88K8483 IDT88K8483 Table Of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SPI-4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Insert and Extract paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Packet Fragment Processor (PFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 QDR-II Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Embedded Processor Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Direct Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Indirect Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Electrical and Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 2 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. IDT88K8483 IDT88K8483 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PFP Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PFP Allocation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 QDR-II SRAM Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 QDR-II Allocation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SPI-4 Ingress Port Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SPI-4 Egress Calendar Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SPI-4 Tributary to SPI-4 Main Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SPI-4 main to SPI-4 Tributary Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PFP Loop Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path . . . . . . . 38 PFP Redirect Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IDT88K8483 IDT88K8483 SPI-4 Connections Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SPI-4 Ingress Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SPI-4 Ingress State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SPI-4 Egress State Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Egress word transition state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Status Channel State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PFP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PFP Ingress Flow Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PFP Flow Control Example For Over Booking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 54 IDT88K8483 IDT88K8483 and IDT7172604 IDT7172604 QDR-II SRAM connections . . . . . . . . . . . . . . . . . . . . . 55 Flow Control Mode 1 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 QDR-II FIFOs Allocation Example For Buffering Option . . . . . . . . . . . . . . . . . . . . . . . 57 QDR-II Flow Control Example For Buffering Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Flow Control Mode 2 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 IDT88K8483 IDT88K8483 and FPGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Generic Interface - Transfer Format for Normal Data . . . . . . . . . . . . . . . . . . . . . . . . . 59 Generic Interface - Transfer Format for Stratus Word. . . . . . . . . . . . . . . . . . . . . . . . . . 60 Microprocessor Interface - Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PMON Measure Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Internal PMON Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 External PMON Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Clock Generator Type M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Clock Generator Type T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Power-on-Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 JTAG Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 TRSTB Signal During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 IDT88K8483 IDT88K8483 Power Supply Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 IDT88K8483 IDT88K8483 VDDA25 VDDA25 Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 IDT88K8483 IDT88K8483 SPI4x_VREF Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Indirect Register Access Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Indirect access module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Auxiliary Interface - QDR-II / Generic - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . 154 Auxiliary Interface - QDR-II / Generic - Read Access . . . . . . . . . . . . . . . . . . . . . . . . 154 MCU Interface - Motorola Mode - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MCU Interface - Motorola Mode - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MCU Interface - Intel Mode - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 MCU Interface - Intel Mode - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 88K8483 88K8483 Top View Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Figure 54. JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 55. BR 672 FCBG Package Outline, RoHS compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. IDT88K8483 IDT88K8483 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 SPI-4 Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Generic Interface - Control Field Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Field Associated Non-Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Field Associated Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Non Field Associated Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Time Base Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 CLK_SEL signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DIV4 signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 JTAG Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Direct Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Indirect Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Direct Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Indirect Registers Map - Segment Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Indirect Registers Map - Module Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Indirect Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Global Software Reset Register (Register Offset=0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Microprocessor Mailbox Input FIFO Data Register (Register Offset=0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Microprocessor Mailbox Input FIFO Length Register (Register Offset=0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Microprocessor Mailbox Input FIFO Status Register (Register Offset=0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Microprocessor Mailbox Output FIFO Data Register (Register Offset=0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Microprocessor Mailbox Output FIFO Length Register (Register Offset=0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Microprocessor Mailbox Input FIFO Status Register (Register Offset=0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Embedded Processor State Register (Register Offset=0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Microprocessor Indirect Access Control Register (Register Offset=0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Microprocessor Indirect Access Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Microprocessor Indirect Access Data Register -1 (Register Offset=0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Microprocessor Indirect Access Data Register - 2 (Register Offset=0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Microprocessor Indirect Access Data Register - 3 (Register Offset=0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Microprocessor Indirect Access Data Register - 4 (Register Offset=0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Microprocessor Indirect Access Address Register - 1 (Register Offset=0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Microprocessor Indirect Access Address Register - 2 (Register Offset=0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Microprocessor Indirect Access Address Register - 3 (Register Offset=0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PFP T-M insert control register (Register Offset=0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PFP T-M insert data register(Register Offset=0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PFP T-M extract control register (Register Offset=0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PFP T-M extract data register (Register Offset=0x3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PFP M-T insert control register (Register Offset=0x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PFP M-T insert data register (Register Offset=0x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PFP M-T extract control register (Register Offset=0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 PFP M-T extract data register (Register Offset=0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Primary Interrupt Indication Register (Register Offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Primary Interrupt Enable Register (Register Offset=0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Secondary Module Indication Register (Register Offset=0x0A.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Secondary Module Enable Register (Register Offset=0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Secondary interrupt module B Indication register(Register Offset=0xC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Secondary Interrupt module B enable register (Register Offset=0xD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Interrupt secondary COMMON indication register (Register Offset=0xe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Interrupt Secondary COMMON Enable Register (register_offset=0xf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 MCLK Divider Sticky Register (Block Base=0x0a00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Clock Control Input Status Register (Block Base=0x0a00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . .104 5 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. SPI-4 Ingress LP to LID Mapping Table (Block Base=0x0000, Register Offset=0x00-0xff) . . . . . . . . . . . . . . . . . . .105 SPI-4 Ingress Calendar 0 Table (Block Base=0x0100, Register Offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . .105 Ingress Calendar 1 Table (Block Base=0x0200, Register Offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . . . . . . .105 SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SPI-4 Ingress Configuration Register (Block Base=0x0300, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . .106 SPI-4 Ingress Training Parameter Register (Block base=0x0300, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . .107 SPI-4 Ingress Calendar 0 Configuration Register (Block Base=0x0300, Register Offset=0x03) . . . . . . . . . . . . . . .107 SPI-4 Ingress Calendar 1 Configuration Register (Block base=0x0300, Register Offset=0x04) . . . . . . . . . . . . . . .108 SPI-4 Ingress Status Register (Block base=0x0300, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 SPI-4 Ingress Diagnostics Register (Block base=0x0300, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .109 SPI-4 Ingress Automatic Alignment Control Register (Block base=0x0300, Register Offset=0x07) . . . . . . . . . . . . .109 SPI-4 Ingress Calendar Switch Control Register (Block base=0x0300, Register Offset=0x08) . . . . . . . . . . . . . . . .109 Ingress Calendar Switch Register: Bit CAL_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Ingress calendar Switch Register: Bit I_DIP_CSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 SPI-4 Ingress Fill Level Register (Block base=0x0300, Register offset=0x0B-0x0C) . . . . . . . . . . . . . . . . . . . . . . . .110 SPI-4 Ingress Max Fill Level Register (Block Base=0x0300, Register Offset=0x0D-0x0E . . . . . . . . . . . . . . . . . . . .110 SPI-4 Ingress Watermark Register (Block Base=0x0300, Register Offset=0x0F-0x10) . . . . . . . . . . . . . . . . . . . . . .111 Ingress Training to out of sync threshold Registe(Block Base=0x0300,Register Offset=0x13) . . . . . . . . . . . . . . . .111 SPI-4 Egress LID To LP Mapping Table (Block Base=0x0400, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . .111 SPI-4 Egress Calendar 0 Table (Block Base=0x0500, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . . . . . . . . .111 SPI-4 Egress Calendar 1 Table (Block Base=0x0600, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . . . . . . . . .112 SPI-4 Egress Configuration Register (Block Base=0x0800, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . .113 SPI-4 Egress Training Parameter Register (Block Base=0x0800, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . .113 SPI-4 Egress Calendar 0 Configuration Register (Block Base=0x0800, Register Offset=0x03) . . . . . . . . . . . . . . . .114 SPI-4 Egress Calendar 1 Configuration Register (Block Base=0x0800, Register Offset=0x04) . . . . . . . . . . . . . . . .114 SPI-4 Egress Status Register (Block Base=0x0800, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 SPI-4 Egress Diagnostics Register (Block Base=0x0800, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .115 SPI-4 Egress Automatic Alignment Control Register (Block Base=0x0800, Register Offset=0x07) . . . . . . . . . . . . .115 SPI-4 Egress Calendar Switch Control Register (Block Base = 0x0800, Register Offset=0x08) . . . . . . . . . . . . . . .116 SPI-4 Egress Fill Level Register (Block Base=0x0800, Register Offset = 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . .116 SPI-4 Egress Max Fill Level Register (Block Base =0x0800, Register Offset = 0x0D and 0x0E) . . . . . . . . . . . . . .116 SPI-4 Histogram Measure Launch Register (Block Base=0x0900 Register Offset=0x00) . . . . . . . . . . . . . . . . . . . .117 SPI-4 Histogram Measure Status Register (Block Base=0x0900 Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . .117 SPI-4 Histogram Counter Register (Block Base=0x0900 Register Offset=0x02-0x0B) . . . . . . . . . . . . . . . . . . . . . .117 SPI-4 Bit Alignment Result Register (Block Base=0x0900 Register Offset=0x0C-0x1E) . . . . . . . . . . . . . . . . . . . . .118 SPI-4 Egress Data Lane Timing Control (Block Base=0x0900, Register Offset=0x2A) . . . . . . . . . . . . . . . . . . . . . .118 SPI-4 Egress Data Control Lane Timing Control (Block Base=0x0900, Register Offset=0x2B) . . . . . . . . . . . . . . . .118 SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C) . . . . . . . . . . . . . . . . . . . . . .119 SPI-4 Egress Status Timing Control (Block Base=0x0900, Register Offset=0x2D) . . . . . . . . . . . . . . . . . . . . . . . . .119 SPI-4 Egress Status Clock Timing Control (Block Base=0x0900, Register Offset=0x2E) . . . . . . . . . . . . . . . . . . . .120 PFP Buffer Segment Assign Table (Block Base=0x01000/0x1800, Register Offset=0x00-0x3F) . . . . . . . . . . . . . .120 PFP Packet Length Thresholds (Block Base=0x1100/0x1900, Register Offset=0x00-03F) . . . . . . . . . . . . . . . . . . .121 PFP Queue Diagnose Table (Block Base=0x1200/0x1A00, Register Offset=0x00-0x3F) . . . . . . . . . . . . . . . . . . . .121 PFP Packet Diagnose Table (Block Base=0x1300/0x1B00, Register Offset=0x00-03F) . . . . . . . . . . . . . . . . . . . . .121 PFP Egress Burst Size Table (Block Base=0x1400/0x1C00, Register Offset=0x00-0x3F) . . . . . . . . . . . . . . . . . . .122 PFP Egress Weight And Direction Register (Block Base=0x1500/0x1D00, Register Offset=0x00-03F) . . . . . . . . .122 PFP Egress Packet Mode Control Register (Block Base=0x1600/0x1E00, Register Offset=0x00-0x3F) . . . . . . . . .123 PFP Link Number Configuration Register (Block Base=0x1700/0x1F00, Register Offset=0x00) . . . . . . . . . . . . . . .123 PFP Buffer Management Configuration Register (Block Base=0x1700/0x1F00, Register Offset=0x01) . . . . . . . . .123 PFP Queue Weighting Enable Register (Block Base=0x1700/0x1F00, Register Offset=0x02) . . . . . . . . . . . . . . . .124 PFP Flow Control Register (Block Base=0x1700/0x1F00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . .125 PFP Test Register (Block Base=0x1700/0x1F00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 PFP Ingress Status Monitor Register - 1 (Block Base=0x1700/0x1F00, Register Offset=0x05) . . . . . . . . . . . . . . . .126 PFP Ingress Status Monitor Register - 2 (Block Base=0x1700/0x1F00, Register Offset=0x06) . . . . . . . . . . . . . . . .126 6 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 120. Table 121. Table 119. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. PFP Ingress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x07) . . . . . . . . . . . . . . . .126 PFP Ingress Status Monitor Register - 4 (Block Base=0x1700/0x1F00, Register Offset=0x08) . . . . . . . . . . . . . . . .126 PFP Egress Status Monitor Register - 1 (Block Base=0x1700/0x1F00, Register Offset=0x09) . . . . . . . . . . . . . . . .127 PFP Egress Status Monitor Register - 2 (Block Base=0x1700/0x1F00, Register Offset=0x0A) . . . . . . . . . . . . . . . .127 PFP Egress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x0B) . . . . . . . . . . . . . . . .127 PFP Egress Status Monitor Register - 4 (Block Base=0x1700/0x1F00, Register Offset=0x0C) . . . . . . . . . . . . . . . .127 PFP Internal Parity Error Indication Register (Block Base=0x1700/0x1F00, Register Offset=0x0D) . . . . . . . . . . . .127 PFP Maximum Packet Length Register (Block Base=0x1700/0x1F00, Register Offset=0x0E) . . . . . . . . . . . . . . . .128 Auxiliary Interface Enable Register (Block Base=0x0A00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .129 Auxiliary Interface Configuration Register (Block Base=0x0A00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . .129 Auxiliary Extension Buffer Configuration Register (Block Base=0x0A00, Register Offset=0x02) . . . . . . . . . . . . . . .129 Auxiliary Clock Monitor Status Register (Block Base=0x0A00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . .130 External Memory Test Control Register (Block Base=0x0A00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . .130 External Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 External Memory Test Results Register (Block Base=0x0A00, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . .131 Auxiliary Early Backpressure Threshold Register (Block Base=0x0A00, Register Offset=0x07) . . . . . . . . . . . . . . .131 Auxiliary Packet Mode Configuration Register (Block Base=0x0A00, Register Offset=0x08) . . . . . . . . . . . . . . . . .131 Auxiliary HSTL Receiver Test Control Register (Block Base=0x0A00, Register Offset=0x0E) . . . . . . . . . . . . . . . .131 Auxiliary Automatic Impedance Matching Control Register (Block Base=0x0A00, Register Offset=0x0F) . . . . . . . .132 Auxiliary Synchronization Status Register (Block Base=0x0A00, Register Offset=0x12) . . . . . . . . . . . . . . . . . . . . .132 Auxiliary Initialization Control Register (Block Base=0x0A00, Register Offset=0x013) . . . . . . . . . . . . . . . . . . . . . .133 Enable Control Register (Block Base=0x0B00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Feedback Configuration Register (Block Base=0x0B00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Bandwidth Control Register (Block Base=0x0B00, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Bandwidth level as per field BW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Packet Length Register (Block Base=0x0B00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Burst Size Register (Block Base=0x0B00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Random Control Register (Block Base=0x0B00, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 LID Register (Block Base=0x0B00, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Synchronization Register (Block Base=0x0B00, Register Offset=0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Bit Error Insertion Register (Block Base=0x0B00, Register Offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . .136 PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . .139 PMON Buffer T-M Overflow Indication Register (Block Base=0x0F00, Register Offset=0x02-0x03) . . . . . . . . . . . .140 PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05) . . . . . . . . . . . .141 PMON Buffer T-M Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x06-0x07) . . . . . . .141 PMON Buffer M-T Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x08-0x09) . . . . . . .141 PMON Buffer Overflow Source Register (Block Base=0x0F00, Register Offset=0x0A) . . . . . . . . . . . . . . . . . . . . . .142 PMON T-M Inactive Transfer LP Field Register (Block Base=0x0F00, Register Offset=0x0B) . . . . . . . . . . . . . . . .142 PMON M-T Inactive Transfer LP Field Register (Block Base=0x0F00, Register Offset=0x0C) . . . . . . . . . . . . . . . .142 PMON T-M Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0D) . . . . . . . . . . . . . . . . . .142 PMON T-M Illegal EOP Event Field Register (Block Base=0x0F00, Register Offset=0x0E) . . . . . . . . . . . . . . . . . .142 PMON M-T Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0F) . . . . . . . . . . . . . . . . . .143 PMON M-T Illegal EOP Event Field Register (Block Base=0x0F00, Register Offset=0x10) . . . . . . . . . . . . . . . . . .143 PMON T-M Packet Cut-Down LID Field Register (Block Base=0x0F00, Register Offset=0x11) . . . . . . . . . . . . . . .143 PMON M-T Packet Cut-Down LID Field Register (Block Base=0x0F00, Register Offset=0x12) . . . . . . . . . . . . . . .143 PMON Per LID Counter Table (Block Base=0x0C00, Register Offset=0x00-0x17F) . . . . . . . . . . . . . . . . . . . . . . . .144 PMON Per Module/Interface Counter Table (Block Base=0x0E00 Register Offset=0x00-0x10 . . . . . . . . . . . . . . . .144 PMON Timebase Control Register (Block Base=0x8B00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .145 Timebase source table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 PMON 1ms Timer Register (Block Base=0x8B00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 GPIO Direction Register (Block Base=0x8B00, Register Offset=0x10-0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 GPIO Level Register (Block Base=0x8B00, Register Offset=0x13-0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 GPIO Link Table (Block Base=0x8B00, Register Offset=0x16-0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 7 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Version Number Register (Block Base=0x8B00, Register Offset=0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Version Number Register (Block Base=0x8B00, Register Offset=0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 8 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Pin Assignment The following table shows the IDT88K8483 IDT88K8483 pins and their corresponding symbols. Function Pin ADR0 E1 ADR1 E2 ADR2 D2 ADR3 C4 ADR4 D3 ADR5 B4 BOND0 R6 BOND1 P6 CSB D5 DAT0 A5 DAT1 A4 DAT2 A3 DAT3 B3 DAT4 C3 DAT5 C2 DAT6 C1 DAT7 D1 DIV4 AB6 GPIO0 AE5 GPIO1 AD5 GPIO2 AC5 INTB D4 MPM E4 QDR_A0 L24 QDR_A1 M24 QDR_A10 R24 QDR_A11 R23 QDR_A12 R22 QDR_A13 T21 QDR_A14 R21 QDR_A15 P21 QDR_A16 N21 QDR_A17 M21 QDR_A2 N24 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 1 of 19) 9 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin QDR_A3 N23 QDR_A4 N22 QDR_A5 P22 QDR_A6 P23 QDR_A7 P24 QDR_A8 P25 QDR_A9 P26 QDR_CQ N26 QDR_CQB N25 QDR_D0 D25 QDR_D1 H22 QDR_D10 K23 QDR_D11 K24 QDR_D12 K25 QDR_D13 M22 QDR_D14 M23 QDR_D15 K26 QDR_D16 H26 QDR_D17 F26 QDR_D18 R25 QDR_D19 U26 QDR_D2 F23 QDR_D20 W26 QDR_D21 U25 QDR_D22 W25 QDR_D23 U24 QDR_D24 W24 QDR_D25 U23 QDR_D26 U22 QDR_D27 AC26 QDR_D28 AA26 QDR_D29 AC25 QDR_D3 H23 QDR_D30 Y25 QDR_D31 Y24 QDR_D32 AA23 QDR_D33 AA22 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 2 of 19) 10 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin QDR_D34 W23 QDR_D35 W22 QDR_D4 F24 QDR_D5 H24 QDR_D6 F25 QDR_D7 H25 QDR_D8 D26 QDR_D9 K22 QDR_IMP AD25 QDR_K L26 QDR_KB L25 QDR_Q0 C25 QDR_Q1 G22 QDR_Q10 J23 QDR_Q11 J24 QDR_Q12 J25 QDR_Q13 L22 QDR_Q14 L23 QDR_Q15 J26 QDR_Q16 G26 QDR_Q17 E26 QDR_Q18 R26 QDR_Q19 T26 QDR_Q2 F22 QDR_Q20 V26 QDR_Q21 T25 QDR_Q22 V25 QDR_Q23 T24 QDR_Q24 V24 QDR_Q25 T23 QDR_Q26 T22 QDR_Q27 AB26 QDR_Q28 Y26 QDR_Q29 AB25 QDR_Q3 G23 QDR_Q30 AA25 QDR_Q31 AA24 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 3 of 19) 11 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin QDR_Q32 Y23 QDR_Q33 Y22 QDR_Q34 V23 QDR_Q35 V22 QDR_Q4 E24 QDR_Q5 G24 QDR_Q6 E25 QDR_Q7 G25 QDR_Q8 C26 QDR_Q9 J22 QDR_RB K21 QDR_VREF AD26 QDR_WB L21 RDB C5 RESETB AF4 SPI4A_BIAS A24 SPI4A_CLK_SEL F21 SPI4A_ECTL_N D15 SPI4A_ECTL_P D14 SPI4A_ED[0]_N E15 SPI4A_ED[0]_P E14 SPI4A_ED[1]_N E17 SPI4A_ED[1]_P E16 SPI4A_ED[10]_N A19 SPI4A_ED[10_P A18 SPI4A_ED[11]_N E21 SPI4A_ED[11]_P E20 SPI4A_ED[12]_N D21 SPI4A_ED[12]_P D20 SPI4A_ED[13]_N D22 SPI4A_ED[13]_P E22 SPI4A_ED[14]_N C21 SPI4A_ED[14]_P C20 SPI4A_ED[15]_N B21 SPI4A_ED[15]_P B20 SPI4A_ED[2]_N D17 SPI4A_ED[2]_P D16 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 4 of 19) 12 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4A_ED[3]_N C17 SPI4A_ED[3]_P C16 SPI4A_ED[4]_N B17 SPI4A_ED[4]_P B16 SPI4A_ED[5]_N A17 SPI4A_ED[5]_P A16 SPI4A_ED[6]_N E19 SPI4A_ED[6]_P E18 SPI4A_ED[7]_N D19 SPI4A_ED[7]_P D18 SPI4A_ED[8]_N C19 SPI4A_ED[8]_P C18 SPI4A_ED[9]_N B19 SPI4A_ED[9]_P B18 SPI4A_EDCLK_N A21 SPI4A_EDCLK_P A20 SPI4A_ESCLK_N A7 SPI4A_ESCLK_P A6 SPI4A_ESCLK_T D6 SPI4A_ESTA[0]_N C7 SPI4A_ESTA[0]_P C6 SPI4A_ESTA[1]_N B7 SPI4A_ESTA[1]_P B6 SPI4A_ESTA_T0 E7 SPI4A_ESTA_T1 D7 SPI4A_ICTL_N E9 SPI4A_ICTL_P E8 SPI4A_ID[0]_N D9 SPI4A_ID[0]_P D8 SPI4A_ID[1]_N C9 SPI4A_ID[1]_P C8 SPI4A_ID[10]_N D13 SPI4A_ID[10]_P D12 SPI4A_ID[11]_N C13 SPI4A_ID[11]_P C12 SPI4A_ID[12]_N B13 SPI4A_ID[12]_P B12 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 5 of 19) 13 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4A_ID[13]_N A13 SPI4A_ID[13]_P A12 SPI4A_ID[14]_N C15 SPI4A_ID[14]_P C14 SPI4A_ID[15]_N B15 SPI4A_ID[15]_P B14 SPI4A_ID[2]_N B9 SPI4A_ID[2]_P B8 SPI4A_ID[3]_N A9 SPI4A_ID[3]_P A8 SPI4A_ID[4]_N E11 SPI4A_ID[4]_P E10 SPI4A_ID[5]_N D11 SPI4A_ID[5]_P D10 SPI4A_ID[6]_N C11 SPI4A_ID[6]_P C10 SPI4A_ID[7]_N B11 SPI4A_ID[7]_P B10 SPI4A_ID[8]_N A11 SPI4A_ID[8]_P A10 SPI4A_ID[9]_N E13 SPI4A_ID[9]_P E12 SPI4A_IDCLK_N A15 SPI4A_IDCLK_P A14 SPI4A_ISCLK_N A23 SPI4A_ISCLK_P A22 SPI4A_ISCLK_T C24 SPI4A_ISTA[0]_N C23 SPI4A_ISTA[0]_P C22 SPI4A_ISTA[1]_N B23 SPI4A_ISTA[1]_P B22 SPI4A_ISTA_T0 D23 SPI4A_ISTA_T1 D24 SPI4A_LVDSSTA G21 SPI4A_RCLK E23 SPI4A_VREF B24 SPI4B_BIAS AF24 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 6 of 19) 14 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4B_CLK_SEL AA21 SPI4B_ECTL_N AC15 SPI4B_ECTL_P AC14 SPI4B_ED[0]_N AB15 SPI4B_ED[0]_P AB14 SPI4B_ED[1]_N AB17 SPI4B_ED[1]_P AB16 SPI4B_ED[10]_N AF19 SPI4B_ED[10_P AF18 SPI4B_ED[11]_N AB21 SPI4B_ED[11]_P AB20 SPI4B_ED[12]_N AC21 SPI4B_ED[12]_P AC20 SPI4B_ED[13]_N AC22 SPI4B_ED[13]_P AB22 SPI4B_ED[14]_N AD21 SPI4B_ED[14]_P AD20 SPI4B_ED[15]_N AE21 SPI4B_ED[15]_P AE20 SPI4B_ED[2]_N AC17 SPI4B_ED[2]_P AC16 SPI4B_ED[3]_N AD17 SPI4B_ED[3]_P AD16 SPI4B_ED[4]_N AE17 SPI4B_ED[4]_P AE16 SPI4B_ED[5]_N AF17 SPI4B_ED[5]_P AF16 SPI4B_ED[6]_N AB19 SPI4B_ED[6]_P AB18 SPI4B_ED[7]_N AC19 SPI4B_ED[7]_P AC18 SPI4B_ED[8]_N AD19 SPI4B_ED[8]_P AD18 SPI4B_ED[9]_N AE19 SPI4B_ED[9]_P AE18 SPI4B_EDCLK_N AF21 SPI4B_EDCLK_P AF20 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 7 of 19) 15 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4B_ESCLK_N AF7 SPI4B_ESCLK_P AF6 SPI4B_ESCLK_T AC6 SPI4B_ESTA[0]_N AD7 SPI4B_ESTA[0]_P AD6 SPI4B_ESTA[1]_N AE7 SPI4B_ESTA[1]_P AE6 SPI4B_ESTA_T0 AB7 SPI4B_ESTA_T1 AC7 SPI4B_ICTL_N AB9 SPI4B_ICTL_P AB8 SPI4B_ID[0]_N AC9 SPI4B_ID[0]_P AC8 SPI4B_ID[1]_N AD9 SPI4B_ID[1]_P AD8 SPI4B_ID[10]_N AC13 SPI4B_ID[10]_P AC12 SPI4B_ID[11]_N AD13 SPI4B_ID[11]_P AD12 SPI4B_ID[12]_N AE13 SPI4B_ID[12]_P AE12 SPI4B_ID[13]_N AF13 SPI4B_ID[13]_P AF12 SPI4B_ID[14]_N AD15 SPI4B_ID[14]_P AD14 SPI4B_ID[15]_N AE15 SPI4B_ID[15]_P AE14 SPI4B_ID[2]_N AE9 SPI4B_ID[2]_P AE8 SPI4B_ID[3]_N AF9 SPI4B_ID[3]_P AF8 SPI4B_ID[4]_N AB11 SPI4B_ID[4]_P AB10 SPI4B_ID[5]_N AC11 SPI4B_ID[5]_P AC10 SPI4B_ID[6]_N AD11 SPI4B_ID[6]_P AD10 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 8 of 19) 16 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4B_ID[7]_N AE11 SPI4B_ID[7]_P AE10 SPI4B_ID[8]_N AF11 SPI4B_ID[8]_P AF10 SPI4B_ID[9]_N AB13 SPI4B_ID[9]_P AB12 SPI4B_IDCLK_N AF15 SPI4B_IDCLK_P AF14 SPI4B_ISCLK_N AF23 SPI4B_ISCLK_P AF22 SPI4B_ISCLK_T AD24 SPI4B_ISTA[0]_N AD23 SPI4B_ISTA[0]_P AD22 SPI4B_ISTA[1]_N AE23 SPI4B_ISTA[1]_P AE22 SPI4B_ISTA_T0 AC23 SPI4B_ISTA_T1 AC24 SPI4B_LVDSTA Y21 SPI4B_RCLK AB23 SPI4B_VREF AE24 SPI4M_BIAS AD1 SPI4M_CLK_SEL AE3 SPI4M_ECTL_N R4 SPI4M_ECTL_P P4 SPI4M_ED[0]_N R5 SPI4M_ED[0]_P P5 SPI4M_ED[1]_N U5 SPI4M_ED[1]_P T5 SPI4M_ED[10]_N W1 SPI4M_ED[10_P V1 SPI4M_ED[11]_N AA5 SPI4M_ED[11]_P Y5 SPI4M_ED[12]_N AA4 SPI4M_ED[12]_P Y4 SPI4M_ED[13]_N AB4 SPI4M_ED[13]_P AB5 SPI4M_ED[14]_N AA3 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 9 of 19) 17 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4M_ED[14]_P Y3 SPI4M_ED[15]_N AA2 SPI4M_ED[15]_P Y2 SPI4M_ED[2]_N U4 SPI4M_ED[2]_P T4 SPI4M_ED[3]_N U3 SPI4M_ED[3]_P T3 SPI4M_ED[4]_N U2 SPI4M_ED[4]_P T2 SPI4M_ED[5]_N U1 SPI4M_ED[5]_P T1 SPI4M_ED[6]_N W5 SPI4M_ED[6]_P V5 SPI4M_ED[7]_N W4 SPI4M_ED[7]_P V4 SPI4M_ED[8]_N W3 SPI4M_ED[8]_P V3 SPI4M_ED[9]_N W2 SPI4M_ED[9]_P V2 SPI4M_EDCLK_N AA1 SPI4M_EDCLK_P Y1 SPI4M_ESCLK_N G1 SPI4M_ESCLK_P F1 SPI4M_ESCLK_T F4 SPI4M_ESTA[0]_N G3 SPI4M_ESTA[0]_P F3 SPI4M_ESTA[1]_N G2 SPI4M_ESTA[1]_P F2 SPI4M_ESTA_T0 G5 SPI4M_ESTA_T1 G4 SPI4M_ICTL_N J5 SPI4M_ICTL_P H5 SPI4M_ID[0]_N J4 SPI4M_ID[0]_P H4 SPI4M_ID[1]_N J3 SPI4M_ID[1]_P H3 SPI4M_ID[10]_N N4 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 10 of 19) 18 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4M_ID[10]_P M4 SPI4M_ID[11]_N N3 SPI4M_ID[11]_P M3 SPI4M_ID[12]_N N2 SPI4M_ID[12]_P M2 SPI4M_ID[13]_N N1 SPI4M_ID[13]_P M1 SPI4M_ID[14]_N R3 SPI4M_ID[14]_P P3 SPI4M_ID[15]_N R2 SPI4M_ID[15]_P P2 SPI4M_ID[2]_N J2 SPI4M_ID[2]_P H2 SPI4M_ID[3]_N J1 SPI4M_ID[3]_P H1 SPI4M_ID[4]_N L5 SPI4M_ID[4]_P K5 SPI4M_ID[5]_N L4 SPI4M_ID[5]_P K4 SPI4M_ID[6]_N L3 SPI4M_ID[6]_P K3 SPI4M_ID[7]_N L2 SPI4M_ID[7]_P K2 SPI4M_ID[8]_N L1 SPI4M_ID[8]_P K1 SPI4M_ID[9]_N N5 SPI4M_ID[9]_P M5 SPI4M_IDCLK_N R1 SPI4M_IDCLK_P P1 SPI4M_ISCLK_N AC1 SPI4M_ISCLK_P AB1 SPI4M_ISCLK_T AD3 SPI4M_ISTA[0]_N AC3 SPI4M_ISTA[0]_P AB3 SPI4M_ISTA[1]_N AC2 SPI4M_ISTA[1]_P AB2 SPI4M_ISTA_T0 AC4 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 11 of 19) 19 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin SPI4M_ISTA_T1 AD4 SPI4M_LVDSTA AF5 SPI4M_RCLK AF3 SPI4M_VREF AD2 SPIEN E3 TCK M6 TDI W21 TDO N6 TESTSE J21 TIMEBASE AE4 TMS H21 TRSTB V21 WRB B5 VDDA25 VDDA25 AA17 VDDA25 VDDA25 AA10 VDDA25 VDDA25 F17 VDDA25 VDDA25 F10 VDDA25 VDDA25 G17 VDDA25 VDDA25 G10 VDDA25 VDDA25 L8 VDDA25 VDDA25 L7 VDDA25 VDDA25 U8 VDDA25 VDDA25 U7 VDDA25 VDDA25 Y17 VDDA25 VDDA25 Y10 VDDC12 VDDC12 H17 VDDC12 VDDC12 H16 VDDC12 VDDC12 H15 VDDC12 VDDC12 H14 VDDC12 VDDC12 H13 VDDC12 VDDC12 H12 VDDC12 VDDC12 H11 VDDC12 VDDC12 H10 VDDC12 VDDC12 H9 VDDC12 VDDC12 H19 VDDC12 VDDC12 H18 VDDC12 VDDC12 J17 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 12 of 19) 20 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VDDC12 VDDC12 J16 VDDC12 VDDC12 J15 VDDC12 VDDC12 J14 VDDC12 VDDC12 J13 VDDC12 VDDC12 J12 VDDC12 VDDC12 J11 VDDC12 VDDC12 J10 VDDC12 VDDC12 J9 VDDC12 VDDC12 J19 VDDC12 VDDC12 J18 VDDC12 VDDC12 K10 VDDC12 VDDC12 K9 VDDC12 VDDC12 K19 VDDC12 VDDC12 K18 VDDC12 VDDC12 L10 VDDC12 VDDC12 L9 VDDC12 VDDC12 L19 VDDC12 VDDC12 L18 VDDC12 VDDC12 M10 VDDC12 VDDC12 M9 VDDC12 VDDC12 M19 VDDC12 VDDC12 M18 VDDC12 VDDC12 N10 VDDC12 VDDC12 N9 VDDC12 VDDC12 N19 VDDC12 VDDC12 N18 VDDC12 VDDC12 P10 VDDC12 VDDC12 P9 VDDC12 VDDC12 P19 VDDC12 VDDC12 P18 VDDC12 VDDC12 R10 VDDC12 VDDC12 R9 VDDC12 VDDC12 R19 VDDC12 VDDC12 R18 VDDC12 VDDC12 T10 VDDC12 VDDC12 T9 VDDC12 VDDC12 T19 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 13 of 19) 21 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VDDC12 VDDC12 T18 VDDC12 VDDC12 U10 VDDC12 VDDC12 U9 VDDC12 VDDC12 U19 VDDC12 VDDC12 U18 VDDC12 VDDC12 V17 VDDC12 VDDC12 V16 VDDC12 VDDC12 V15 VDDC12 VDDC12 V14 VDDC12 VDDC12 V13 VDDC12 VDDC12 V12 VDDC12 VDDC12 V11 VDDC12 VDDC12 V10 VDDC12 VDDC12 V9 VDDC12 VDDC12 V19 VDDC12 VDDC12 V18 VDDC12 VDDC12 W17 VDDC12 VDDC12 W16 VDDC12 VDDC12 W15 VDDC12 VDDC12 W14 VDDC12 VDDC12 W13 VDDC12 VDDC12 W12 VDDC12 VDDC12 W11 VDDC12 VDDC12 W10 VDDC12 VDDC12 W9 VDDC12 VDDC12 W19 VDDC12 VDDC12 W18 VDDH15 VDDH15 M26 VDDH15 VDDH15 AE26 VDDH15 VDDH15 B26 VDDH15 VDDH15 M20 VDDH15 VDDH15 N20 VDDH15 VDDH15 V20 VDDH15 VDDH15 W20 VDDH15 VDDH15 Y20 VDDH25 VDDH25 G19 VDDH25 VDDH25 Y19 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 14 of 19) 22 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VDDL12 VDDL12 AA13 VDDL12 VDDL12 AA12 VDDL12 VDDL12 F13 VDDL12 VDDL12 F12 VDDL12 VDDL12 G13 VDDL12 VDDL12 G12 VDDL12 VDDL12 M8 VDDL12 VDDL12 M7 VDDL12 VDDL12 N8 VDDL12 VDDL12 N7 VDDL12 VDDL12 Y13 VDDL12 VDDL12 Y12 VDDL25 VDDL25 AA14 VDDL25 VDDL25 AA9 VDDL25 VDDL25 AA8 VDDL25 VDDL25 AA18 VDDL25 VDDL25 F14 VDDL25 VDDL25 F9 VDDL25 VDDL25 F8 VDDL25 VDDL25 F18 VDDL25 VDDL25 G14 VDDL25 VDDL25 G9 VDDL25 VDDL25 G8 VDDL25 VDDL25 G18 VDDL25 VDDL25 H8 VDDL25 VDDL25 H7 VDDL25 VDDL25 P8 VDDL25 VDDL25 P7 VDDL25 VDDL25 V8 VDDL25 VDDL25 V7 VDDL25 VDDL25 W8 VDDL25 VDDL25 W7 VDDL25 VDDL25 Y14 VDDL25 VDDL25 Y9 VDDL25 VDDL25 Y8 VDDL25 VDDL25 Y18 VDDT33 VDDT33 A25 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 15 of 19) 23 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VDDT33 VDDT33 A2 VDDT33 VDDT33 AF25 VDDT33 VDDT33 AF2 VSS AA7 VSS AA6 VSS AB24 VSS AE25 VSS AE2 VSS B25 VSS B2 VSS E6 VSS E5 VSS F7 VSS F6 VSS F5 VSS G7 VSS G6 VSS H6 VSS J6 VSS K17 VSS K16 VSS K15 VSS K14 VSS K13 VSS K12 VSS K11 VSS K6 VSS L17 VSS L16 VSS L15 VSS L14 VSS L13 VSS L12 VSS L11 VSS L6 VSS M17 VSS M16 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 16 of 19) 24 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VSS M14 VSS M11 VSS N17 VSS N16 VSS N12 VSS N11 VSS P17 VSS P16 VSS P11 VSS R17 VSS R16 VSS R13 VSS R11 VSS T17 VSS T16 VSS T15 VSS T14 VSS T13 VSS T12 VSS T11 VSS T6 VSS U17 VSS U16 VSS U15 VSS U14 VSS U13 VSS U12 VSS U11 VSS U6 VSS V6 VSS W6 VSS Y7 VSS Y6 VSS M25 VSS AA16 VSS AA11 VSS F16 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 17 of 19) 25 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VSS F11 VSS G16 VSS G11 VSS K8 VSS K7 VSS T8 VSS T7 VSS Y16 VSS Y11 VSS K20 VSS L20 VSS P20 VSS AA20 VSS AA19 VSS F20 VSS F19 VSS AA15 VSS F15 VSS G15 VSS J8 VSS J7 VSS R8 VSS R7 VSS Y15 VSS AE1 VSS B1 VSS U21 VSS M13 VSS M12 VSS R12 VSS P12 VSS P14 VSS P15 VSS N13 VSS N15 VSS M15 VSS R14 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 18 of 19) 26 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Function Pin VSS R15 VSS N14 VSS P13 VTT075 VTT075 G20 VTT075 VTT075 H20 VTT075 VTT075 J20 VTT075 VTT075 R20 VTT075 VTT075 T20 VTT075 VTT075 U20 NP1 A1 NP1 A26 NP1 AF1 NP1 AF26 Table 1 IDT88K8483 IDT88K8483 Pinout (Part 19 of 19) 27 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Pin Description Table The following table lists the functions of the pins provided on the IDT88K8483 IDT88K8483. Some of the functions listed are multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Analog signals ending with "P" are defined as being positive. Analog signals ending with "N" are defined as being negative. Digital signals ending with "B" are defined as being active, or asserted, when at a logic zero (low) level. All other digital signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Symbol1 I/O Type2 Function SPI-4 Interface Comments Link PHY SPI4A_ED[15:0]_P SPI4B_ED[15:0]_P SPI4M_ED[15:0]_P SPI4A_ED[15:0]_N SPI4B_ED[15:0]_N SPI4M_ED[15:0]_N O LVDS Egress Data Bus. This data bus is used to carry egress payload data and in-band control words. TDAT[15:0] RDAT[15:0] SPI4A_EDCLK_P SPI4B_EDCLK_P SPI4M_EDCLK_P SPI4A_EDCLK_N SPI4B_EDCLK_N SPI4M_EDCLK_N O LVDS Egress Data Clock. This clock is associated with the egress data bus (ED) and the control signal (ECTL). TDCLK RDCLK SPI4A_ECTL_P SPI4B_ECTL_P SPI4M_ECTL_P SPI4A_ECTL_N SPI4B_ECTL_N SPI4M_ECTL_N O LVDS Egress Control. This signal is high when a control word is present on the egress data bus (ED) and it is low otherwise. TCTL RCTL SPI4A_ESTA[1:0]_P SPI4B_ESTA[1:0]_P SPI4M_ESTA[1:0]_P SPI4A_ESTA[1:0]_N SPI4B_ESTA[1:0]_N SPI4M_ESTA[1:0]_N I LVDS Egress FIFO Status LVDS. These signals are used to carry egress round-robin FIFO status information, along with associated error detection and framing. TSTAT[1:0] RSTAT[1:0] SPI4A_ESCLK_P SPI4B_ESCLK_P SPI4M_ESCLK_P SPI4A_ESCLK_N SPI4B_ESCLK_N SPI4M_ESCLK_N I LVDS Egress Status Clock LVDS. This clock is associated with the egress FIFO status signals (ESTA). TSCLK RSCLK SPI4A_ESTA_T[1:0] SPI4B_ESTA_T[1:0] SPI4M_ESTA_T[1:0] I LVTTL Pull-up Egress FIFO Status LVTTL. These signals are used to carry egress round-robin FIFO status information, along with associated error detection and framing. TSTAT[1:0] RSTAT[1:0] SPI4A_ESCLK_T SPI4B_ESCLK_T SPI4M_ESCLK_T I LVTTL Pull-up Schmitt Trigger Egress Status Clock LVTTL. This clock is associated with the egress FIFO status signals (ESTA_T). TSCLK RSCLK Table 2 Pin Description (Part 1 of 5) 28 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Symbol1 I/O Type2 SPI4A_ID[15:0]_P SPI4B_ID[15:0]_P SPI4M_ID[15:0]_P SPI4A_ID[15:0]_N SPI4B_ID[15:0]_N SPI4M_ID[15:0]_N I LVDS Ingress Data Bus. This data bus is used to carry ingress payload data and in-band control words. RDAT[15:0] TDAT[15:0] SPI4A_IDCLK_P SPI4B_IDCLK_P SPI4M_IDCLK_P SPI4A_IDCLK_N SPI4B_IDCLK_N SPI4M_IDCLK_N I LVDS Ingress Data Clock. This clock is associated with the ingress data bus (ID) and the control signal (ICTL). RDCLK TDCLK SPI4A_ICTL_P SPI4B_ICTL_P SPI4M_ICTL_P SPI4A_ICTL_N SPI4B_ICTL_N SPI4M_ICTL_N I LVDS Ingress Control. This signal is high when a control word is present on the ingress data bus (ID) and it is low otherwise. RCTL TCTL SPI4A_ISTA[1:0]_P SPI4B_ISTA[1:0]_P SPI4M_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4B_ISTA[1:0]_N SPI4M_ISTA[1:0]_N O LVDS Ingress FIFO Status LVDS. These signals are used to carry ingress round-robin FIFO status information, along with associated error detection and framing. RSTAT[1:0] TSTAT[1:0] SPI4A_ISCLK_P SPI4B_ISCLK_P SPI4M_ISCLK_P SPI4A_ISCLK_N SPI4B_ISCLK_N SPI4M_ISCLK_N O LVDS Ingress Status Clock LVDS. This clock is associated with the ingress FIFO status signals (ISTA). RSCLK TSCLK SPI4A_ISTA_T[1:0] SPI4B_ISTA_T[1:0] SPI4M_ISTA_T[1:0] O LVTTL Pull-up Ingress FIFO Status LVTTL. These signals are used to carry ingress round-robin FIFO status information, along with associated error detection and framing. RSTAT[1:0] TSTAT[1:0] SPI4A_ISCLK_T SPI4B_ISCLK_T SPI4M_ISCLK_T O LVTTL Pull-up Schmitt Trigger Ingress Status Clock LVTTL. This clock is associated with the ingress FIFO status signals (ISTA_T). RSCLK TSCLK SPI4A_BIAS SPI4B_BIAS SPI4M_BIAS Analog BIAS. This signal must be connected via an external pull-down 1% 3K resistor to VSS. SPI4A_VREF SPI4B_VREF SPI4M_VREF Analog REF. These signals are reference for LVDS. These signals should be connected to VDDL12 VDDL12. CMOS Pull-down Status Channel Control. This signal controls the status signal I/O type. A hardware reset or software reset must be perform after changing the level of this signal. 1 - LVDS status. 0 - LVTTL status. SPI4A_LVDSSTA SPI4B_LVDSSTA SPI4M_LVDSSTA I Function Comments QDR-II Interface / Generic Interface (Auxiliary Interface) QDR_A[17:0] O HSTL QDR_A[17:0] is QDR-II Address Bus. This bus is used to transfer the address to the QDR-II / FPGA devices. It is driven out on the rising edge of K and K clocks during write or read operation. Table 2 Pin Description (Part 2 of 5) 29 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Symbol1 I/O Type2 QDR_D[35:0]/ G_ECTL[3:0], G_EDAT[31:0] O HSTL QDR_D[35:0] is QDR-II Output Data Bus. This bus is used to transfer the data to the QDR-II / FPGA devices. It is driven out on the rising edge of K and K clocks during write operation. G_ECTL[3:0] is Generic Interface Egress Control Bus. G_EDAT[31:0] is Generic Interface Egress Data Bus. QDR_Q[35:0]/ G_ICTL[3:0], G_IDAT[31:0] I HSTL QDR_Q[35:0] is QDR-II Input Data Bus. This bus is used to transfer data from the QDR-II / FPGA devices. It is sampled on the rising edge of K and K clocks during read operation. G_ICTL[3:0] is Generic Interface Ingress Control Bus. G_IDAT[31:0] is Generic Interface Ingress Data Bus. QDR_RB O HSTL QDR_RB is QDR-II Read Control. This active low signal is driven out on the rising edge of K clock. When it active, a read operation is initiated. When it deasserted, the read port is deselected. QDR_WB O HSTL QDR_WB is QDR-II Write Control. This active low signal is driven out on the rising edge of K clock. When it asserted, a write operation is initiated. When it deasserted, the write port is deselected. QDR_K / G_ECLKP O HSTL QDR_K is QDR-II Positive Output Clock. The rising edge of QDR_K is used to capture input data to the device and to drive out data from the device. G_ECLKP is Generic Interface Positive Egress Clock. QDR_KB / G_ECLKN O HSTL QDR_KB is QDR-II Negative Output Clock. The rising edge of QDR_KB is used to capture input data to the device and to drive out data from the device. G_ECLKN is negative Generic Interface Egress Clock. QDR_CQ / G_ICLKP I HSTL QDR_CQ is QDR-II Synchronous Positive Input Clock. The rising edge of QDR_CQ is tightly matched to the data inputs and can be used as a data valid indication. G_ICLKP is Generic Interface Positive Ingress Clock. QDR_CQB / G_ICLKN I HSTL QDR_CQB is QDR-II Synchronous Negative Input Clock. The rising edge of QDR_CQB is tightly matched to the data inputs and can be used as a data valid indication. G_ICLKN is Generic Interface Negative Ingress Clock. QDR_VREF / G_VREF I Analog Reference QDR_VREF is 0.75 Reference Voltage Input. This static input is used to set reference level for HSTL inputs and outputs as well as AC measurement points. This pin should be connected to VDDH15/2 VDDH15/2. G_VREF is 0.75 Reference Voltage Input. This pin should be connected to VDDH15/2 VDDH15/2. QDR_IMP / G_IMP I Reference QDR_IMP is Reference Input. This signal must be connected via an external pull-down 100 OHM resistor to VSS. G_IMP is Reference Input. This signal must be connected via an external pull-down 100 OHM resistor to VSS. I CMOS ADR[5:0] is Microprocessor Address Bus. This bus is used to transfer the address from the micro-controller. I/O CMOS DAT[7:0] is Microprocessor Data Bus. This bus is used to transfer the data between the device and the microprocessor. SDO (DAT[0]) is Serial Peripheral Interface (SPI) data. Function Comments Microprocessor Interface ADR[5:0] DAT[7:0] / SDO Table 2 Pin Description (Part 3 of 5) 30 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Symbol1 I/O Type2 WRB/SDI I CMOS Pull-up Schmitt Trigger WRB is Microprocessor Write Control. Active low. SDI is Serial Peripheral Interface (SPI) Chip Select. Active low. RDB / SCLK I CMOS Pull-up Schmitt Trigger RDB is Microprocessor Read Control. Active low. SCLK is Serial Peripheral Interface (SPI) Clock. CSB I CMOS Pull-up Schmitt Trigger CSB is Microprocessor Chip Select. Active low. INTB O CMOS Open Drain SPIEN I CMOS Pull-up SPIEN is Serial Peripheral Interface (SPI) mode enable. Active high. MPM I CMOS Pull-up MPM is Microprocessor mode Control. This signal controls the microcontroller mode. 1 - Intel Mode. 0 - Motorola Mode. TRSTB I CMOS Pull-up JTAG Reset. This active low signal asynchronously resets the boundary scan logic and the JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. TCK I CMOS Pull-up Schmitt Trigger JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. TMS I CMOS Pull-up JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. TDO O CMOS tri-state JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. TDI I CMOS Pull-up JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. RESETB I CMOS Pull-down Hardware Reset. Active low. TESTSE I CMOS Pull-down Test Scan Enable. Active high. Input used for IDT factory test. This signal should be pulled down for normal operation. TIMEBASE I/O CMOS Pull-up Time Base. A positive edge on this signal updates the PMON counters. Subsequent edges within approximately 4ms are be ignored. GPIO[2:0] I/O CMOS Pull-up General Purpose I/O. These pins can be configured as general purpose I/O pins. SPI4A_RCLK SPI4B_RCLK SPI4M_RCLK I CMOS Pull-up Schmitt Trigger DIV4 I CMOS Pull-up Function Comments INTB is Microprocessor Interrupt. Active low. JTAG Interface Miscellaneous Interface Clock Interface Interface A/B/M Reference Clock. Pre-scalar Select. Configuration pin. Table 2 Pin Description (Part 4 of 5) 31 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Symbol1 I/O I SPI4A_CLK_SEL SPI4B_CLK_SEL SPI4M_CLK_SEL Type2 CMOS Pull-up Function Comments Clock Select. Configuration pin. Power Supply and Ground VDDC12 VDDC12 PWR 1.2V Core Digital Power Supply. 76 pins total VDDL12 VDDL12 PWR 1.2V Digital Power Supply for LVDS. 12 pins total VDDH15 VDDH15 PWR 1.5V Digital Power Supply for HSTL. 8 pins total VDDL25 VDDL25 PWR 2.5V Digital Power Supply for LVDS. 24 pins total VDDH25 VDDH25 PWR 2.5V Digital Power Supply foe HSTL. 2 pins total VDDT33 VDDT33 PWR 3.3V Digital Power Supply for LVTTL. 4 pins total VDDA25 VDDA25 PWR 2.5V Analog Power Supply. 12 pins total VTT075 VTT075 I/O These pins are used for termination. 6 pins total Digital and Analog Ground. 111 pins total These pins must be connected to ground 2 VSS BOND[1:0] PWR IO Table 2 Pin Description (Part 5 of 5) 1. In table 2 Pin Description the external pins with multiple functions have both symbols in the Symbol column (column 1). In table1 IDT 88K8483 88K8483 Pinout the external pins with multiple functions have only the first symbol in the Function column (column 1). 2. All LVDS pins have 100 internal termination resistor. 32 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Functional Description The IDT88K8483 IDT88K8483 device is a three port SPI exchange device intended for use in Ethernet transport, SONET/SDH line cards, security firewalls, and multi-service switches. The SPI-4 interface is defined by the Optical Internetworking Forum. The device can be used to provide rate adaptation, switching, aggregation and fragment to packet conversion between network processor units, multi-gigabit MACs, framers and switch fabric interface devices. A set of HSTL pins may be configured as a packet bus to an FPGA or as a QDR-II memory bus. The FPGA interface can be used to reduce the unnecessary overhead generated in the FPGA by a SPI-4 standard interface. QDR-II memory can be added as an expansion of internal memory provided in the device. DATA PATH In normal operation, there are two paths through the IDT88K8483 IDT88K8483 device: the SPI-4A or SPI-4B ingress to SPI-4M egress path, and the SPI-4 M ingress to SPI-4A and SPI-4B egress path. SPI-4 burst sizes are separately configurable for each physical port. Data enter in bursts on a SPI-4 ingress interface and are sent to the SPI-4 ingress port buffers. The bursts are mapped to a SPI-4 address and stored in the buffer segment pool by the packet fragment processor (PFP). The PFP forward the data to the SPI-4 Egress Port Buffer. The content of the Egress Port buffer is transferred to the SPI-4 egress interface and transmitted out in burst. In addition to the data path described above, there are additional datapaths among the SPI-4 ports, FPGA interface, and microprocessor. Each SPI-4 interface has the ability to perform a per-LP loopback. In addition, the SPI-4A and SPI-4B interfaces can transfer packet bursts on a per-LP basis. All the SPI-4 interfaces can transfer packet bursts to the FPGA interface on a per-LP basis. Each SPI-4 ingress LP (logical port) can be mapped through LID (Logical Identifier) to each one of the SPI-4 egress LPs SPI-4 Ingress Interface SPI-4 Ingress Port Buffer Buffer Segment Pool (PFP) SPI-4 Egress Port Buffer SPI-4 Egress Interface IDT88K8483 IDT88K8483 Figure 2 General Data Path Data Structure PFP Structure There are 4 PFPs (Packet Fragment Processor) in the device - one per each port and direction. For example, for SPI-4A ingress to SPI-4M egress there is one PFP. Each PFP has 508 segments, and each segment has 256 bytes as shown in Figure 3 PFP Structure Example p.34. The user can program the LID allocation in the PFP to allocate the 508 segments to the LIDs that will be active. For example, the user can have 64 LIDs, and allocate 7 segments (1,792) bytes to each LID as shown in Figure 4 PFP Allocation Example p.34. 33 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 PFP (508 segments, 127K bytes) Segment 507 . . . Segment 1 Segment 0 256bytes Figure 3 PFP Structure Example PFP (508 segments, 127K bytes) LID 63 . . . LID 1 LID 0 7 segments (1,792 bytes) Figure 4 PFP Allocation Example QDR-II External Memory Structure The device can be connected to 18M bits QDR-II (2M usable data bytes) SRAM which can store up to 8K segments of 256 bytes as shown in Figure 5 QDR-II SRAM Structure Example p.34. The user can program the LID allocation in the QDR-II. For example, the user can have 64 LIDs, and allocate 128 segments (32Kbytes) to each LID as shown in Figure 6 QDR-II Allocation Example p.34. QDR-II (8K segments, 2M bytes, 16M bits) Segment 8K-1 . . . Segment 1 Segment 0 256bytes Figure 5 QDR-II SRAM Structure Example QDR-II (8K segments, 2M bytes, 16M bits) LID 63 . . . LID 1 LID 0 128 segments / 32K bytes Figure 6 QDR-II Allocation Example 34 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 SPI-4 Ingress Port Buffer Structure Each SPI-4 physical port in the ingress direction has 32 port buffers of 128 bytes as shown in Figure 7 SPI-4 Ingress Port Buffer Structure p.35. The buffers can be concatenated so that data flows from one FIFO into the next. SPI-4 Ingress Port Buffer (32 x 128 byte FIFOs, 4K bytes, 16K segments) Buffer 31 Buffer 30 . . . Buffer 1 Buffer 0 128 bytes Figure 7 SPI-4 Ingress Port Buffer Structure Flow Control SPI-4 Ingress Flow Control There are 3 main parameters for configuring the SPI-4 ingress flow control: - Maximum number of segments per LID is configured in M field in the PFP Buffer Segment Assign Table (p. 120) - Starving Free segments per LID is configured in THR_STARV field in the PFP Buffer Segment Assign Table (p. 120) - Hungry Free segments per LID is configured in THR_HUNG field in the PFP Buffer Segment Assign Table (p. 120) SPI-4 ingress flow control is described in greater detail in PFP Flow Control (p. 53) SPI-4 Egress Flow Control There are three LID status modes in the SPI-4 egress interface: starving, hungry and satisfied. In normal operation the SPI-4 egress interface is receiving starving status from the adjacent device through the status bus, so the LID status is starving, and the LID data is scheduled out in round robin. When the SPI-4 egress interface starts receiving hungry status from the adjacent device, the LID status is changed to hungry, and the LID data is scheduled out in round robin. When the SPI-4 egress interface starts receiving satisfied status from the adjacent device, the LID status is changed to satisfied, and the LID data is not scheduled out. Each SPI-4 interface has four SPI-4 calendars: two for ingress and two for egress. Only one calendar in each direction is active in a specific time. There are 64 LIDs per PFP, and each calendar has maximum of 256 entries. Each calendar entry can be assign to a specific LID as shown in Figure 8 SPI-4 Egress Calendar Example p.36. According to the calendar order, the LIDs with starving status are scheduled in a round robin fashion with high priority, and the LIDs with hungry status are scheduled in a round robin fashion with low priority. All the LIDs with the starving status are scheduled first. The LIDs with the hungry status are scheduled only when there are no LIDs with starving status. The LID status mode in the SPI-4 egress interface (status or credit mode) is configured by CREDIT_EN field in the PFP Flow Control Register (p. 125). If status mode is used (CREDIT_EN=0), then data is sent out until the LID status is changed (starving / hungry / satisfied). If credit mode is used (CREDIT_EN=1), then when the credit is one, the device sends out one data burst, clears to zero the credit, and then waits for another credit from the SPI-4 interface status bus before issuing another LID burst. In credit mode, when the SPI-4 egress interface receives starving status or hungry status from the adjacent device through the status bus, it sets the LID credit to one. When the SPI-4 egress interface receives satisfied status from the adjacent device, it clears the LID credit to zero. 35 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Calendar (256 entries) Entry 255 LID 4 (Hungry) . . . Entry 3 LID 6 (Starving) Entry 2 LID 5 (Hungry) Entry 1 LID 1 (Starving) Entry 0 LID 0 (Starving) Figure 8 SPI-4 Egress Calendar Example Data Path Detailed Description There are several data paths in the device as shown in the figures below. There are four PFPs in the device: PFP module A Tributary to Main (PFP-A-MT), PFP module A Main to Tributary (PFP-A-MT), PFP module B Tributary to Main (PFP-B-MT) and PFP module B Main to Tributary PFP-B-MT. SPI-4 tributary to SPI-4 main data path conveys data from SPI-4 tributary ingress to SPI-4 main egress as shown in Figure 9 SPI-4 Tributary to SPI-4 Main Data Path p.36. SPI-4 Egress Microprocessor SPI-4A Interface Packet Fragment Processor A-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress Microprocessor SPI-4B Interface SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress Microprocessor Packet Fragment Processor A-MT (PFP) SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress Microprocessor Auxiliary SPI-4 Egress Interface Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-TM (PFP) Packet Fragment Processor B-MT (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers Internal Traffic Detector SPI-4M Interface Main SPI-4s SPI-4 Egress SPI-4 Egress Port Buffers Internal Traffic Generator SPI-4 Egress SPI-4 Ingress Port Buffers Figure 9 SPI-4 Tributary to SPI-4 Main Data Path SPI-4 main to SPI-4 tributary data path conveys data from SPI-4 main ingress to SPI-4 tributary egress as shown in Figure 10 SPI-4 main to SPI-4 Tributary Data Path p.37. 36 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 SPI-4 Egress Microprocessor SPI-4A Interface Packet Fragment Processor A-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress Microprocessor SPI-4B Interface SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress Microprocessor Packet Fragment Processor A-MT (PFP) SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress Microprocessor Auxiliary SPI-4 Egress Interface Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-TM (PFP) Packet Fragment Processor B-MT (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers Internal Traffic Detector SPI-4M Interface Main SPI-4s SPI-4 Egress SPI-4 Egress Port Buffers Internal Traffic Generator SPI-4 Egress SPI-4 Ingress Port Buffers Figure 10 SPI-4 main to SPI-4 Tributary Data Path PFP loop data path is sending data from PFP-A back to PFP-A or sending data from PFP-B back to PFP-B as shown in Figure 11 PFP Loop Data Path p.37. SPI-4 Egress Microprocessor SPI-4A Interface Packet Fragment Processor A-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress Microprocessor SPI-4B Interface SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress Microprocessor Packet Fragment Processor A-MT (PFP) SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress Microprocessor Auxiliary SPI-4 Egress Interface Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-TM (PFP) Packet Fragment Processor B-MT (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers Internal Traffic Detector SPI-4M Interface Main SPI-4s SPI-4 Egress SPI-4 Egress Port Buffers Internal Traffic Generator SPI-4 Egress SPI-4 Ingress Port Buffers Figure 11 PFP Loop Data Path Figure 12 Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path p.38 describes the following data paths: - Microprocessor data path is sending data from/to microprocessor interface to/from PFP-A. - Auxiliary data path is sending data from/to Auxiliary interface to/from PFP-B. - Internal traffic generator / detector data path is sending data from Internal Traffic Generator to PFP-B and from PFP-B to Internal Traffic Detector. The Internal Traffic Generator and the Internal Traffic Detector both use a Pseudo Random Bit Sequence (PRBS) pattern. 37 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 SPI-4 Egress Microprocessor SPI-4A Interface Packet Fragment Processor A-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffer SPI-4 Egress Microprocessor SPI-4B Interface SPI-4 Egress SPI-4 Ingress Port Buffer SPI-4 Egress SPI-4 Egress Port Buffer SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress Microprocessor Packet Fragment Processor A-MT (PFP) SPI-4 Egress SPI-4 Egress Port Buffer Tributary SPI-4s SPI-4 Egress Microprocessor Auxiliary SPI-4 Egress Interface Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers Internal Traffic Detector Packet Fragment Processor B-MT (PFP) SPI-4M Interface Main SPI-4s SPI-4 Egress SPI-4 Egress Port Buffers Internal Traffic Generator SPI-4 Egress SPI-4 Ingress Port Buffers Figure 12 Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path PFP redirect data path conveys data from PFP-A to PFP-B or from PFP-B to PFP-A as shown in Figure 13 PFP Redirect Data Path p.38. SPI-4 Egress Microprocessor SPI-4A Interface Packet Fragment Processor A-TM (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress Microprocessor SPI-4B Interface SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers SPI-4 Egress Microprocessor Packet Fragment Processor A-MT (PFP) SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress Microprocessor Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-TM (PFP) Auxiliary SPI-4 Egress Interface Packet Fragment Processor B-MT (PFP) SPI-4 Egress SPI-4 Ingress Port Buffers Internal Traffic Detector SPI-4M Interface Main SPI-4s SPI-4 Egress SPI-4 Egress Port Buffers Internal Traffic Generator SPI-4 Egress SPI-4 Ingress Port Buffers Figure 13 PFP Redirect Data Path 38 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 External Interfaces The external interfaces provided on the IDT88K8483 IDT88K8483 device are three SPI-4 interfaces, SPI-4A, SPI-4B and SPI-4M, an interface to either a FPGA or a QDR-II bus, a pin-selectable serial or parallel microprocessor interface, a JTAG interface, and five general purpose input or output (GPIO) pins. The following information contains a set of the highlights of the features supported from the relevant standards, and a description of additional features implemented to enhance the usability of these interfaces for the system architect. SPI-4A AND SPI-4B Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02 OIF-SPI-4-02.1) for full details. ­ Two instantiations of the SPI-4 interface ­ Clock rate is 77.76 - 450 MHz DDR ­ Link and PHY interfaces are supported ­ Logical port address range of 0 ­ 255 with support for between 1 and 64 simultaneously active logical ports ­ MAXBURST parameters configurable from 16 to 256 bytes in 16 byte multiples ­ 256-entry FIFO status calendar ­ Quarter-clock-rate LVTTL, or full-rate LVDS FIFO status signals are selectable per SPI-4 port SPI-4M Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02 OIF-SPI-4-02.1) for full details. ­ One instantiation of the SPI-4 Main interface ­ Clock rate is 87 - 450 MHz DDR ­ Link and PHY interfaces are supported ­ Logical port address range of 0 ­ 255 with support for between 1 and 128 simultaneously active logical ports ­ MAXBURST parameters configurable from 16 to 256 bytes in 16 byte multiples ­ 256-entry FIFO status calendar ­ Quarter-clock-rate LVTTL, or full-rate LVDS FIFO status signals are selectable per SPI-4 port FPGA INTERFACE The FPGA interface is shared with the QDR-II interface. Selecting the FPGA interface enables the following features: ­ Clock rate is 160 - 200 MHz DDR source-synchronous ­ Logical port address range of 0 ­ 63 with support for 64 simultaneously active logical ports ­ DDR HSTL logic levels QDR-II INTERFACE The QDR-II interface is shared with the FPGA interface. Selecting the QDR-II interface enables the following features: ­ Clock rate is 160 - 200 MHz QDR-II ­ Up to 18 Mbit of QDR-II memory is supported ­ QDR-II HSTL logic levels MICROPROCESSOR INTERFACE Parallel microprocessor interface: ­ Eight bit data bus ­ Six bit address bus ­ Pin-selectable Intel or Motorola control signals ­ Direct accessed space used for quick interrupt processing ­ Expanded indirect access space used for provisioning ­ Read operations to a reserved address or reserved bit fields return 0 ­ Write operations to reserved addresses or bit fields are ignored 39 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Serial microprocessor interface: ­ Compliance to Motorola Serial Peripheral Interface (SPI) specification ­ Byte access ­ Direct accessed space used for quick interrupt processing ­ Expanded indirect access space used for provisioning ­ Read operations to a reserved address or reserved bit fields return 0 ­ Write operations to reserved addresses or bit fields are ignored JTAG ­ Complies with the IEEE 1149.1 standard. GPIO ­ Three GPIO signals are provided. Each signal may be independently defined as an input or an output pin. ­ The GPIO interface allows flexible use of the GPIO pins. The following can be defined per GPIO pin: Direction: input or output Level: value to write if programmed to be an output, or value that is being read if programmed to be an input 40 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 SPI-4 Interface Overview SPI-4.2 as originally defined is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device (network processor), for aggregate bandwidths of OC-192 OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications. The SPI-4.2 protocol transfers data in variable length bursts. Associated with each burst is information such as logical port number (for a multi-port device such as a 10 x 1 GbE MAC), SOP, EOP. This information is collected by the SPI-4 interface and passed to the PFPs. The Optical Internetworking Forum (OIF) controls the SPI-4.2 Implementation Agreement document (available at http://www.oiforum.com). The SPI-4 interface power down mode has to be disabled before configuring the interface. The SPI-4 interface also has to be configured before the interface is enabled. The SPI-4 interface LVDS outputs (except for the clock) can be powered down by setting to 1 the SPI4_PDN field in the SPI-4 Interface Enable Register (p. 106). The interface is enabled by setting to 1 the SPI4_EN field in the SPI-4 Interface Enable Register (p. 106). The SPI-4 interface consists of separate ingress and egress interfaces as described in Figure 14 IDT88K8483 IDT88K8483 SPI-4 Connections Example p.42. The ingress and egress ports are unidirectional and independent of each other. Each port has 16 data signals, a clock, and a control signal, all of which use LVDS (differential) signaling, and are sampled on both edges of the clock. There are also ingress status port and egress status port. Each status port has 2 fifo status signals and a clock. The status port signal can be configured to LVDS (differential) or LVTTL by the status channel control pin LVDSSTA (SPI4A_LVDSSTA, SPI4B_LVDSSTA, SPI4AM_LVDSSTA). The ingress port supports dynamic alignment, and the egress port supports programmable skew. The IDT88K8483 IDT88K8483 has three SPI-4 interfaces: one main SPI-4 interface (M) and two tributary SPI-4 interface (A and B). Each tributary SPI4 interface supports up to 64 logical ports. The main SPI4 interface supports up to 128 logical ports. The logical port in-band address are from 0 to 255. The clock source for the SPI-4 ingress port is the SPI-4 interface input clock IDCLK (SPI4A_IDCLK_P, SPI4A_IDCLK_N, SPI4B_IDCLK_P, SPI4B_IDCLK_N, SPI4M_IDCLK_P and SPI4M_IDCLK_N). The source clock for the SPI-4 egress port is the internal SPI-4 clock generator. 41 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 SPI4A_ED[15:0]_P SPI4A_ED[15:0]_N SPI4A_ID[15:0]_P SPI4A_ID[15:0]_N SPI4A_IDCLK_P SPI4A_IDCLK_N SPI4A_ICTL_P SPI4A_ICTL_N SPI4A_EDCLK_P SPI4A_EDCLK_N SPI4A_ECTL_P SPI4A_ECTL_N SPI4A_ESTA[1:0]_P SPI4A_ESTA[1:0]_N SPI4A_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4A_ISCLK_P SPI4A_ISCLK_N SPI4A_ESCLK_P SPI4A_ESCLK_N SPI4A_ID[15:0]_P SPI4A_ID[15:0]_N SPI4A_ED[15:0]_P SPI4A_ED[15:0]_N SPI4A_EDCLK_P SPI4A_EDCLK_N SPI4A_ECTL_P SPI4A_ECTL_N SPI4A_ESTA[1:0]_P SPI4A_ESTA[1:0]_N SPI4A_IDCLK_P SPI4A_IDCLK_N SPI4A_ICTL_P SPI4A_ICTL_N SPI4A_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4A_ISCLK_P SPI4A_ISCLK_N SPI4A_ESCLK_P SPI4A_ESCLK_N VDDL25 VDDL25 SPI4A_LVDSSTA VDDL12 VDDL12 SPI4A_VREF SPI4A_BIAS IDT88K8483 IDT88K8483 3K 1% Network Processor Figure 14 IDT88K8483 IDT88K8483 SPI-4 Connections Example SPI-4 Ingress Data Channel The SPI-4 ingress data channel is independent from the status channel. The data channel supports bit alignment and de-skew, error event detection and transfer termination. The status channel generates status frame, and controls the output skew per lane. 42 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Locker Bit alignment Deskew Rx machine PFP Skew control status generation status Figure 15 SPI-4 Ingress Block Diagram Bit alignment The bit alignment block is responsible for data and clock alignment. The bit alignment allows the clock to be used for correct data sampling and eliminate bit errors by providing adequate set-up and hold time margins. The alignment selection is programed by AUTO_ALIGN field in the SPI-4 Ingress Automatic Alignment Control Register (p. 109). The device is responsible for an edge transition histogram for each lane (lane is defined as a deferential pair of data, control or status signals). The data is sampled by 10-phased-shifted clock during each clock cycle. Each 2 consecutive sampled values are XORed and accumulated during a fixed observation window to generate transition edge histogram. The measurement histogram is triggered by writing to the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117). The measurement process is indicated by the BUSY field in the SPI-4 Histogram Measure Status Register (p. 117). The BUSY field is set to 1 when a measurement is launched. The BUSY field is auto cleared to 0 when the measure is finished. The received bit stream is selected from the 10 samples. The tap selection is made automatically and is available in the TAP_SEL field in the SPI-4 Bit Alignment Result Register (p. 118). The bit alignment sequence automatically carried out in the device as follows: - Write lane number in the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117). - Poll the BUSY field in the SPI-4 Histogram Measure Status Register (p. 117). If BUSY is 0, then read the C[n] field in the SPI-4 Histogram Counter Register (p. 117) which indicates the counter value. The counter value is used to select the tap. - Write the selected Tap value to TAP field in the SPI-4 Bit Alignment Result Register (p. 118). De-skew The De-skew block is responsible for alignment between the data signals. The De-skew block can de-skew +/-1bit. For diagnose purpose, an out of range offset between lines is provided. If the skew is more than 2 bits, then the I_DSK_OOR field in the SPI-4 Ingress Status Register (p. 108) is set. The I_DSK_OOR field is cleared when the offset is in range. Receive State Machine The ingress data channel has 2 states, IN_SYNCH and OUT_OF_SYNCH. The machine transitions from OUT_OF_SYNCH to IN_SYNCH if a number of consecutive error-free DIP-4 are detected. The number is configured by using the SPI-4 Ingress Configuration Register (p. 106). The machine stays in OUT_OF_SYNCH state if the interface is not enabled. The status of the synchronization is indicated by I_SYNCV field in the SPI-4 Ingress Status Register (p. 108). Any transition on I_SYNCV will be captured by the PMON Event Interrupt Indication Register (p. 136). An interrupt is generated if interrupt options is enabled. The data channel synchronization status is fed to status channel generation logic for handshaking. 43 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 B A OUT_OF_SYNCH IN_SYNCH A= A number of consecutive DIP-4 error or reset or interface disabled or a number of consecutive training pattern received B= A number of consecutive DIP-4 error free Figure 16 SPI-4 Ingress State Machine The bus word may be payload data word, payload control word, idle control word or training word. It is classified by the CTL input signal and the content of the control field. The DIP fields of the control word previous and subsequent payload data or training data are subjected to DIP checking. DIP checking is performed both in IN_SYNCH and OUT_OF_SYNCH state. In IN_SYNCH state, each DIP error generates a DIP-4 error event. This event is captured and forward to PMON. The logical port information is carried in the payload control word. The following data words are associated with this logical port. The LP to LID mapping is defined by the SPI-4 Ingress LP to LID Mapping Table (p. 105). Transfers for inactive LPs are flushed, and an ingress inactive logical port event generates. The event and the associated logical port are forwarded to PMON. For each active logical port, data word, SOP, EOP, abort tag and length are put into associated ingress port buffer. For statistics purpose, the number of transfers and bytes are forwarded to PMON. Multiple logical ports can not be mapped to the same LID. The logical port can not remapped in the IN_SYNCH state. Errors handling scheme: When a DIP4 error is received in the in IN_SYNCH state, a DIP4 error event is generated and an error tag is added to the packets being received. When a reserved control word is received, a bus error event is generated and the control word is ignored. When consecutive payload control words are received, a bus error event is generated and every control word is ignored except the last received. When payload is received following an idle control word, a bus error event is generated. When a transfer belonging to an inactive LP is received, an inactive transfer event is generated and the transfer is dropped. When an unaligned transfer is received, a bus error event is generated. SPI-4 Ingress Associated Status Channel Status Generation The device supports both LVTTL and LVDS status channel mode. The status mode (LVDS/LVTTL) is configured by LVDSSTA (SPI4A_LVDSSTA, SPI4B_LVDSSTA and SPI4M_LVDSSTA) pin. The level of the LVDSSTA pin is reflected by LVDS_STA field in the SPI-4 Ingress Status Register (p. 108). When the device is in LVTTL status mode, and if ingress data channel is out of sync, it sends all `11'. When the device is in LVDS status mode, and if ingress data channel is out of sync, it sends training pattern. When the device is in sync, it sends calendar frame or period training. They are switched at the frame boundary. The device supports one or two sets of calendars. If I_CSW_EN field in the SPI4 Ingress Calendar Switch Control Register (p. 109) is set to 1, then two sets of calendars are used. In this mode, a calendar selection word must be received immediately after the framing word for correct operation. If CAL_SEL field in the SPI4 Ingress Calendar Switch Control Register (p. 109) is cleared to 0, then the device selects calendar 0 and the selection word is fixed to 01b. If CAL_SEL field in the SPI4 Ingress Calendar Switch Control Register (p. 109) is set to 1, then the device selects calendar 1, and the calendar selection word is fixed to 10b. 44 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 If the I_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after the last `11' framing pattern. If I_CSW_EN is set to 1, and I_DIP_CSW is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indications after last `11' framing pattern. If I_CSW_EN is set to 1, and I_DIP_CSW is set to 0, then the DIP-2 is computed over all preceding status indications after last `11' framing pattern and excluding the calendar selection word. The starving, hungry or satisfied indication for each status word for each logical port is based on the status from the PFP and the SPI-4 ingress port buffer fill level. See SPI-4 Ingress WATERMARK Register (p. 111). The calendar length is configured by the I_CAL_LEN field in the SPI-4 Ingress Calendar 0 Configuration Register. (p. 107) while calendar length=I_CAL_LEN+1. In LVTTL mode, the I_CAL_LEN field can be programmed to any value. In LVDS mode, the I_CAL_LEN field must be programmed to 4n-1 (n is an integer). Output Skew The LVDS output lane skew is adjustable in order to provide greater flexibility for board layout. The clock outputs can be skewed over a range of 0 to 0.9 clock cycles with a resolution of 0.1 clock cycle. The data outputs can be skewed over a range of 0 to 0.3 clock cycle with a resolution of 0.1 clock cycle. The skews are controlled by the output delay registers. Diagnostics Features - Ingress data channel clock detect. The ingress data clock IDCLK (SPI4A_IDCLK_P, SPI4A_IDCLK_N, SPI4B_IDCLK_P, SPI4B_IDCLK_N, SPI4M_IDCLK_P, and SPI4M_IDCLK_N) is monitored. If there is no transition on IDCLK in a 2048 MCLK hopping window, then the DCLK_AV field in the SPI-4 Ingress Status Register (p. 108) is cleared to 0. The DCLK_AV flag transition from 1 to 0 generates an event towards the PMON, and the PMON captures this event. - Ingress port buffer unavailable. If there is more data but no port buffer available, then the device discards the data, generates a SPI_4 port buffer unavailable event, and forwards the event to PMON. - DIP-2 error insertion. A number of consecutive (less then 16) DIP-2 errors can be generated. The number of errors is configured by the DIP_E_NUM field in the SPI-4 Ingress Diagnostics Register (p. 109). When the I_ERR_INS field in the SPI-4 Ingress Diagnostics Register (p. 109) is set to 1, it triggers error insertion using the I_DIP_NUM field value. The I_ERR_INS field is self cleared when the correct number of errors is generated. The I_DIP_NUM field value is not changed by device. - Force continuous training. The status channel generates continuous training pattern in LVDS protocol if I_FORCE_TRAIN field in the SPI-4 Ingress Diagnostics Register (p. 109) is set to 1. The status channel generates a continuous `11' pattern in LVTTL protocol if I_FORCE_TRAIN field is set to 1. - Ingress port buffer fill level. The ingress port buffer fill level is indicated in the FILL_CURR field in the SPI-4 Ingress Fill Level Register (p. 110). The maximum port buffer fill level is configured by using the FILL_MAX field in the SPI-4 Ingress Training to out of sync threshold Register (p. 111). SPI4 egress Data Channel The SPI4 egress interface has data channel and status channel. The data channel carries transfers, and the status channel carries status. The output skew is per lane controllable. The status channel does bit alignment and de-skew in LVDS mode. The device receives status frame for controlling the data path flow. In packet mode, the TX machine must transmit a complete packet before it starts a transfer for another logical port. 45 of 162 October 20, 2006 IDT IDT88K8483 IDT88K8483 Skew control Locker TX machine data PFP Bit aligne De-skew Status termination status Figure 17 SPI-4 Egress State Block Diagram Tx Machine Control words are inserted only between the transfers. Once a transfer has begun, the data words are sent uninterrupted until a whole transfer is complete. The interval between the end of a given transfer and the next payload control word consists of zero or more idle control words and training patterns. Successive SOP must occur not less than 8 cycles apart. Figure 18 Egress word transition state machine p.46 shows the word transition on the interface. The adjacent device that generates the transfer have to meet the requirements as described in Figure 18 Egress word transition state machine p.46. Figure 18 Egress word transition state machine The SPI-4 interface loads data and overhead from the egress port buffer and generates transfer. The cycle to cycle behavior is described in Figure 18 Egress word transition state machine p.46. The number of idle control words between transfers is less than or equal to 4 if there is data for transmit. The LID to logical port mapping is configured by SPI-4 Ingress Training to out of sync threshold Register (p. 111). Multiple LID can not be mapped to the same logical port. LID can not be remapped in the IN_SYNCH status. Packet mode and cut through mode selection is defined in PFP. The main SPI-4 transmit data fr