IDT8737-11 IDT873711 - Datasheet Archive

 

LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LOW SKEW,

 

IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LOW SKEW, ÷1/÷2 ÷ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER IDT8737-11 IDT8737-11 FEATURES: DESCRIPTION: · Two divide-by-1 and two divide-by-2 differential 3.3V LVPECL outputs · Selectable differential CLK, xCLK, or LVPECL clock inputs · CLK, xCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, and HCSL · PCLK, xPCLK supports the following input types: LVPECL, CML, and SSTL · Maximum output frequency: 650MHz · Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on xCLK input · Output skew: 60ps (max.) · Part-to-part skew: as low as 200ps · Bank skew: - Bank A, as low as 20ps - Bank B, as low as 35ps · Propagation delay: 1.7ns (max.) · 3.3V operating supply · Available in TSSOP package The IDT8737-11 IDT8737-11 is a low skew, high performance differential-to-3.3V LVPECL fanout buffer-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT873711 IDT873711 ideal for clock distribution applications that demand well-defined performance and repeatability. FUNCTIONAL BLOCK DIAGRAM QA0 xQA0 D CLK_EN QA1 Q xCLK xQA1 LE CLK 0 ÷1 1 ÷2 PCLK xPCLK QB0 xQB0 CLK_SEL QB1 xQB1 MR The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AUGUST 2004 1 c 2004 Integrated Device Technology, Inc. DSC 6168/5 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VDD 1 20 CLK_EN 2 19 CLK_SEL 3 18 VDD CLK 4 17 5 16 xQA1 PCLK 6 15 QB0 xPCLK 7 14 8 13 VDD MR 9 12 QB1 VDD 10 11 ­0.5 to VDD+0.5 V 92.6 °C/W Storage Temperature ­65 to +150 °C xQB0 NC Output Voltage Package Thermal Impedance (0 lfpm) NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. QA1 xCLK V TSTG xQA0 V ­0.5 to VDD+0.5 JA QA0 4.6 Input Voltage VO VEE Power Supply Voltage VI xQB1 CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Parameter CIN RPULLUP RPULLDOWN Description Typ. Max. Unit Input Capacitance - 4 pF Input Pullup Resistor 51 - K Input Pulldown Resistor 51 - K TSSOP TOP VIEW PIN DESCRIPTION(1) Symbol Number VEE 1 Power Type CLK_EN 2 Input Description Negative Supply Pin Pullup Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS interface levels. CLK_SEL 3 Input Pulldown Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects CLK / xCLK inputs. LVTTL / LVCMOS interface levels. CLK 4 Input Pulldown xCLK 5 Input Pullup PCLK 6 Input Pulldown Pullup xPCLK 7 Input NC 8 Non-Inverting Differential Clock Input Inverting Differential Clock Input Non-Inverting Differential LVPECL Clock Input Unused Inverting Differential LVPECL Clock Input No Connection MR 9 Input VDD 10, 13, 18 Power Pulldown Positive Supply Pins Master Reset. Resets the output divider. LVTTL / LVCMOS interface levels. xQB1, QB1 11, 12 Output Differential Output Pair. LVTTL / LVCMOS interface levels. xQB0, QB0 14, 15 Output Differential Output Pair. LVTTL / LVCMOS interface levels. xQA1, QA1 16, 17 Output Differential Output Pair. LVTTL / LVCMOS interface levels. xQA0, QA0 19, 20 Output Differential Output Pair. LVTTL / LVCMOS interface levels. NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values. 2 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CONTROL INPUT FUNCTION TABLE(1,2) Inputs Outputs MR CLK_EN CLK_SEL Selected Source QA0, QA1 xQA0, xQA1 QB0, QB1 xQB0, xQB1 1 X X X LOW HIGH LOW HIGH 0 0 0 CLK, xCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 0 1 PCLK, xPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 1 0 CLK, xCLK Enabled Enabled Enabled Enabled 0 1 1 PCLK, xPCLK Enabled Enabled Enabled Enabled NOTES: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below. 2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table. Enabled Disabled xCLK, xPCLK CLK, PCLK CLK_EN xQA0, xQA1, xQB0, xQB1 QA0, QA1, QB0, QB1 CLK_EN Timing Diagram CLOCK INPUT FUNCTION TABLE(1) Inputs Outputs CLK or PCLK xCLK or xPCLK QAx xQAx QBx xQBx Input to Output Mode Polarity 0 1 L H L H Differential to Differential Non-Inverting 1 0 H L Differential to Differential Non-Inverting H L 0 (2) Biased L H L H Single-Ended to Differential Non-Inverting 1 Biased(2) H L H L Single-Ended to Differential Non-Inverting (2) Biased 1 L H L H Single-Ended to Differential Inverting Biased(2) 0 H L H L Single-Ended to Differential Inverting NOTES: 1. H = HIGH L = LOW 2. See Single-Ended Signal diagram under Application Information at the end of this datasheet. 3 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS - COMMERCIAL Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Positive Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current - - 50 mA DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH CLK_EN, CLK_SEL, MR 2 VDD + 0.3 V VIL CLK_EN, CLK_SEL, MR -0.3 0.8 V IIH Input Current HIGH CLK_EN 5 A IIL Input Current LOW CLK_EN VIN = 0V, VDD = 3.465V -150 CLK_SEL, MR VIN = 0V, VDD = 3.465V -5 CLK_SEL, MR VIN = VDD = 3.465V VIN = VDD = 3.465V 150 A DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL - COMMERCIAL Symbol VPP VCMR IIH Parameter Test Conditions Common Mode Input Voltage Min. Typ. V VDD - 0.85 V A Input Current LOW xCLK VIN = VDD = 3.465V 5 CLK IIL Input Current HIGH Unit 0.3 VEE + 0.5 (1,2) Max. 0.15 Peak-to-Peak Input Voltage VIN = VDD = 3.465V 150 xCLK VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V A -150 CLK -5 NOTES: 1. For single-ended applications, the max. input voltage for CLK / xCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH. DC ELECTRICAL CHARACTERISTICS, LVPECL- COMMERCIAL Symbol IIH Parameter Min. Typ. Max. Unit A VPP VIN = VDD = 3.465V 5 VIN = VDD = 3.465V 150 PCLK VIN = 0V, VDD = 3.465V -150 xPCLK Input Current LOW PCLK xPCLK IIL Input Current HIGH Test Conditions VIN = 0V, VDD = 3.465V -5 Peak-to-Peak Input Voltage 0.3 (1,2) A 1 V VCMR Common Mode Input Voltage VEE + 1.5 VDD V VOH Output Voltage HIGH(3) VDD - 1.4 VDD - 1 V VOL Output Voltage LOW(3) VDD - 2 VDD - 1.7 V 0.65 0.9 V VSWING Peak-to-Peak Output Voltage Swing NOTES: 1. For single-ended applications, the max. input voltage for PCLK / xPCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH. 3. Outputs terminated with 50 to VDD - 0.2V. 4 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS - COMMERCIAL All parameters measured at 500MHz unless noted otherwise; Cycle-to-cycle jitter = jitter on output; the part does not add jitter Symbol FMAX tPD Parameter Test Conditions Min. Typ. f 650MHz 1 Propagation Delay(1) CLK, xCLK 1 1.6 PCLK, xPCLK tSK(O) Output Skew tSK(B) Bank Skew(4) tSK(PP) Part-to-Part Skew(3,4) ns 60 ps 20 Bank A Bank B ps 35 200 tR Output Rise Time 20 - 80% @ 50MHz tF Output Fall Time 20 - 80% @ 50MHz 300 Output Duty Cycle ps 700 300 odc MHz 1.7 (2,4) Unit 650 Output Frequency Max. ps 700 48 ps 52 50 % NOTES: 1. Measured from the differential input crossingpoint to the differential output crossingpoint. 2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. This parameter is defined in accordance with JEDEC Standard 65. POWER SUPPLY CHARACTERISTICS - INDUSTRIAL Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Positive Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current - - 55 mA DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH CLK_EN, CLK_SEL, MR 2 VDD + 0.3 V VIL CLK_EN, CLK_SEL, MR -0.3 0.8 V IIH Input Current HIGH 5 A IIL Input Current LOW CLK_EN CLK_SEL, MR VIN = VDD = 3.465V VIN = VDD = 3.465V 150 CLK_EN VIN = 0V, VDD = 3.465V CLK_SEL, MR VIN = 0V, VDD = 3.465V A -150 -5 DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL - INDUSTRIAL Symbol VPP VCMR Parameter Test Conditions Min. Typ. V IIL Input Current HIGH Input Current LOW VDD - 0.85 V xCLK VIN = VDD = 3.465V 5 A CLK IIH Common Mode Input Voltage Unit 1.3 VEE + 0.5 (1,2) Max. 0.15 Peak-to-Peak Input Voltage VIN = VDD = 3.465V 150 xCLK VIN = 0V, VDD = 3.465V -150 CLK VIN = 0V, VDD = 3.465V -5 NOTES: 1. For single-ended applications, the max. input voltage for CLK / xCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH. 5 A IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS, LVPECL- INDUSTRIAL Symbol IIH Parameter Test Conditions Typ. Max. Unit A VPP VIN = VDD = 3.465V 5 VIN = VDD = 3.465V 150 PCLK VIN = 0V, VDD = 3.465V -150 xPCLK Input Current LOW PCLK xPCLK IIL Input Current HIGH Min. VIN = 0V, VDD = 3.465V -5 Peak-to-Peak Input Voltage A 0.3 (1,2) 1 V VCMR Common Mode Input Voltage VEE + 1.5 VDD V VOH Output Voltage HIGH(3) VDD - 1.4 VDD - 1 V VOL Output Voltage LOW(3) VDD - 2 VDD - 1.7 V 0.6 0.9 V Max. Unit VSWING Peak-to-Peak Output Voltage Swing NOTES: 1. For single-ended applications, the max. input voltage for PCLK / xPCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH. 3. Outputs terminated with 50 to VDD - 0.2V. AC ELECTRICAL CHARACTERISTICS - INDUSTRIAL All parameters measured at 500MHz unless noted otherwise; cycle-to-cycle jitter = jitter on output; the part does not add jitter Symbol FMAX tPD Parameter Test Conditions Min. 650 MHz f 650MHz 1 1.8 ns 1 1.7 Output Frequency Propagation Delay(1) CLK, xCLK PCLK, xPCLK tSK(O) Typ. Output Skew(2,4) (4) tSK(B) Bank Skew tSK(PP) 75 30 Part-to-Part Skew(3,4) Bank A Bank B ps ps 45 300 ps tR Output Rise Time 20 - 80% @ 50MHz 300 700 ps tF Output Fall Time 20 - 80% @ 50MHz 300 700 ps 53 % odc Output Duty Cycle 47 50 NOTES: 1. Measured from the differential input crossingpoint to the differential output crossingpoint. 2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. This parameter is defined in accordance with JEDEC Standard 65. 6 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PARAMETER MEASUREMENT INFORMATION VDD Scope Z = 50 Qx LVPECL 50 VDD = 2V Z = 50 xQx 50 VEE = -1.3V ± 0.135V Output Load Test Circuit VDD xCLK, xPCLK Cross Points VPP CLK, PCLK VEE Differential Input Level xQx Qx xQy Qy tSK(0) Output Skew 7 VCMR IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PARAMETER MEASUREMENT INFORMATION - CONTINUED xQx Part 1 Qx xQy Part 2 Qy tSK(PP) Part-to-Part Skew 80% 80% VSWING Clock Inputs and Outputs 20% 20% tF tR Input and Output Rise and Fall Time xCLK, xPLK CLK, PCLK xQA0, xQA1, xQB0, xQB1 QA0, QA1, QB0, QB1 tPD Propagation Delay xQA0, xQA1, xQB0, xQB1 QA0, QA1, QB0, QB1 Pulse Width tPERIOD tW odc = tPERIOD odc and tPERIOD 8 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF VDD/2 is generated by the bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/ R1 = 0.609. VDD R1 1K CLK_IN + VREF C1 0.1uF - R2 1K Single-Ended Signal Driving Differential Input TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50 5 2 FOUT Zo 5 2 Zo FIN Zo = 50 Zo = 50 FOUT 50 FIN 50 Zo = 50 VDD - 2V RTT 1 RTT = 3 2 Zo Zo 3 2 Zo (VOH + VOL / VDD - 2) - 2 LVPECL Output Termination, layout A LVPECL Output Termination, layout B 9 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the IDT8737-11 IDT8737-11. Equations and example calculations are also provided. POWER DISSIPATION: The total power dissipation for the IDT8737-11 IDT8737-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating power dissipated in the load. Power (core)MAX = VDD_MAX * ICC_MAX = 3.465 * 55mA = 190.57mW Power (outputs)MAX = 30.2mW/Loaded Output Pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 120.8mW = 311.37mW JUNCTION TEMPERATURE: Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum recommended junction temperature for this device is 125°C. The equation for is as follows: tJ = JA * Pd_total + TA tJ = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (JA) must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 77.6°C/W per the following Thermal Resistance table. Therefore, tJ for an ambient temperature of 85°C with all its outputs switching is: 85°C + 0.311W * 77.6°C/W = 109.16°C. This is well below the limit of 125°C. This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (singlelayer or multi-layer). THERMAL RESISTANCE JA for 20-pin TSSOP, forced convection JA by Velocity (Linear Feet per mInute) 0 10 200 400 Unit 92.6 Multi-Layer PCB, JEDEC Standard Test boards 77.6 70.9 °C/W IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CALCULATIONS AND EQUATIONS VDD Q1 VOUT RL 50 VDD - 2V LVPECL Output Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations, which assume a 50 load and a termination voltage of VDD ­ 2V. For Logic HIGH: VOUT = VOH_MAX = VDD_MAX ­ 1V. (VDD_MAX ­ VOH_MAX) = 1V For Logic LOW: VOUT = VOL_MAX = VDD_MAX ­ 1.7V. (VDD_MAX ­ VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives HIGH. Pd_L is power dissipation when the output drives LOW. Pd_H = {[ VOH_MAX ­ (VDD_MAX ­ 2V)] / RL} * (VDD_MAX ­ VOH_MAX) = {[ 2V ­ (VDD_MAX ­ VOH_MAX)] / RL} * (VDD_MAX ­ VOH_MAX) = [( 2V ­ 1V) / 50] * 1V = 20mW. Pd_L = {[ VOL_MAX ­ (VDD_MAX ­ 2V)] / RL} * (VDD_MAX ­ VOL_MAX) = {[ 2V ­ (VDD_MAX ­ VOL_MAX)] / RL} * (VDD_MAX ­ VOL_MAX) = [( 2V ­ 1.7V) / 50] * 1.7V = 10.2mW. Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 11 IDT8737-11 IDT8737-11 LOW SKEW, ÷1/÷2 DIFFERENTIAL-TO-3.3V LVPECL ÷ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process Blank I PG PGG Thin Shrink Small Outline Package TSSOP - Green 8737-11 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Low Skew, ÷1/ ÷2 Differential-to-3.3V LVPECL Fanout Buffer for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 12 for Tech Support: clockhelp@idt.com