PM4388 IDT82V2108 AN-354 PM6388 T1/J1-020H T1/J1-02CH T1/J1-044H XCK/24 - Datasheet Archive

 

PM4388 to the IDT82V2108 Application Note AN-354 INTRODUCTION The IDT82V2108, T1/E1/J1 Octal Framer, has the same PQFP pin

 

Converting Designs Using the PM4388 PM4388 to the IDT82V2108 IDT82V2108 Application Note AN-354 AN-354 INTRODUCTION The IDT82V2108 IDT82V2108, T1/E1/J1 Octal Framer, has the same PQFP pin assignment as PMC-Sierra's PM4388 PM4388. Functionally, it is an integrated super-set of the two PMC-Sierra's chips (PM4388 PM4388 & PM6388 PM6388) and offering the same basic functions. As a result, it may be possible to replace the PM4388 PM4388 with minimal changes to the hardware and software. This paper describes the considerations of converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108. It consists of 2 parts: PART I: CONVERTING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108; PART II: MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS. The IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 2002 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice February 24, 2003 Ver 1.0 Table of Contents PART I: CONVERTING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 . 3 1 2 3 4 5 6 7 8 TRANSMIT TIMING OPTIONS . 4 RECEIVE CAS/RBS BUFFER . 7 RECEIVE SYSTEM INTERFACE . 8 3.1 In Receive Clock Slave Mode - Case 1 . 9 3.2 In Receive Clock Slave Mode - Case 2 . 10 3.3 In Receive Clock Slave Mode - Case 3 . 11 3.4 In Receive Clock Slave Mode - Case 4 . 12 3.5 In Receive Clock Slave Mode - Case 5 . 13 3.6 In Receive Clock Slave Mode - Case 6 . 14 3.7 In Receive Clock Slave Mode - Case 7 . 15 3.8 In Receive Clock Slave Mode - Case 8 . 16 3.9 Receive Channel Offset And Bit Offset . 17 3.10 High Impedance Of The Receive System Interface . 17 TRANSMIT SYSTEM INTERFACE . 18 4.1 EMODE[1:0] (b7~6, 005H) In The PM4388 PM4388 . 19 4.2 ECLKFALL (b1, 004H) In The PM4388 PM4388 . 19 4.3 Transmit Channel Offset And Transmit Bit Offset . 20 4.4 Transmit Multiplexed Mode And Transmit Double Clock Mode . 20 HDLC CONTROLLER . 21 RECEIVE PER-CHANNEL CONTROL . 21 PRGD . 22 FRAME GENERATOR . 22 PART II: MICROPROCESSOR INTER-FACE TIMING CHARACTERISTICS . 23 APPENDICES . 24 Table of Contents 2 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 PART I: CONVERTING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 When the TEMODE (b0, 400H) in the IDT82V2108 IDT82V2108 is set to 1 (default), the whole chip is in T1/J1 mode. In this mode, the IDT82V2108 IDT82V2108 can be configured to perform the equivalent functions as that of the PM4388 PM4388. Because the PM4388 PM4388 supports T1 only, the J1 related bits in the IDT82V2108 IDT82V2108 should be set as the follows to disable the J1 format: (1). The JYEL bit (b3, T1/J1-020H T1/J1-020H) should be set to 0. (default) (2). The J1_YEL bit (b5, T1/J1-02CH T1/J1-02CH) should be set to 0. (default) (3). The J1_CRC bit (b6, T1/J1-044H T1/J1-044H) should be set to 0. (default) (4). The J1_YEL bit (b5, T1/J1_044H) should be set to 0. (default) Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 3 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 1 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 TRANSMIT TIMING OPTIONS shows the diagram of the Transmit Timing Options block in the PM4388 PM4388. Figure - 2 shows the diagram of Transmit Timing Options block in the IDT82V2108 IDT82V2108. The Transmit Timing Options block selects an input reference clock for the Transmit Jitter Attenuator DPLL and determines which clock signal is to be used as the Line Transmit Clock. The design of this function block in the IDT82V2108 IDT82V2108 differs from that of the PM4388 PM4388. Figure - 1 CECLK2M 0 CECLK 1 0 FIFOBYP 1 EMODE[1] 0 1 2.048 MHz Clock Gapper TJAT FIFO Input TLCLK[x] Output OCLKSEL CTCLK 1 01 RLCLK[x] 00 TJAT PLL PLLREF[1:0] 10 Smooth 1.544 MHz 0 0 1 SMCLKO "Jitter Free 1.544MHz 11 0 XCLK (37.056MHz) 1 CTCLKSEL /8 /3 12.352MHz for FRMR 0 /2 1 HSBPSEL High speed clock for ELST, SIGX, TPSC & RPSC Figure 1. PM4388 PM4388 Transmit Timing Options Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 4 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 TSCCKA TSCCKB LRCK TSCCKA TSCCKB LTCKn XCK/24 XCK/24 TSCCKA/8 LRCK input reference clock Transmit DPLL Clock output smoothed clock XCK/24 XCK/24 TSCCKA/8 Transmit Jitter Attenuator selected by the LTCK_SEL[2:0] (b2~0, T1/J1-007H T1/J1-007H) selected by the TJATREF_SEL[2:0] (b5~3, T1/J1-007H T1/J1-007H) FIFO data to be transmitted LTDn Figure 2. IDT82V2108 IDT82V2108 Transmit Timing Options The signal names in Figure - 1 are different from those in Figure 2, but the functions are the same. Table 1 shows their relationship. Table 2: PM4388 PM4388 Transmit Timing Options Registers Address: 007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H Table 1: Signal Name Relationship Between PM4388 PM4388 & IDT82V2108 IDT82V2108 PM4388 PM4388 CECLK CTCLK LTCLK[x] RLCLK[x] XCLK Bit TSCCKB TSCCKA LTCKn LRCKn XCK The different design in the IDT82V2108 IDT82V2108 and the PM4388 PM4388 results in the different functions of the corresponding registers. Table 2 is the Transmit Timing Options registers in the PM4388 PM4388, and Table 3 is the Transmit Timing Option registers in the IDT82V2108 IDT82V2108 T1 mode. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 Type Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IDT82V2108 IDT82V2108 R/W Unused Unused R/W R/W R/W R/W R/W HSBPSEL X X OCLKSEL PLLREF1 PLLREF0 CTCLKSEL SMCLKO 5 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 In the PM4388 PM4388, the HSBPSEL is used to select the high-speed clock used in the ELST, SIGX, RPSC and TPSC to be 18.528MHz or 12.352MHz. In the IDT82V2108 IDT82V2108, high frequency is not used and 12.352MHz clock is enough to handle the associated functions. The PLLREF[1:0] in the PM4388 PM4388 are used to select an input reference clock for the Transmit Jitter Attenuator Digital Phase Lock Loop (DPLL). The same function is performed by the TJATREF_SEL[2:0] in the IDT82V2108 IDT82V2108. Table 4 shows the different configurations between the PM4388 PM4388 and the IDT82V2108 IDT82V2108 for the same selection of DPLL input reference clock. The OCLKSEL, CTCLKSEL and SMCLKO in the PM4388 PM4388 are used to select one of clock signals as the Line Transmit Clock (LTCLK[x]). The same function is performed by the LTCK_SEL[2:0] in the IDT82V2108 IDT82V2108. Table 5 shows the different configurations in the PM4388 PM4388 and the IDT82V2108 IDT82V2108 for the same selection of Line Transmit Clock. (PM4388 PM4388: TLCLK[x] - IDT82V2108 IDT82V2108: LTCKn). Table 3: IDT82V2108 IDT82V2108 T1 Mode Transmit Timing Options Registers Address: 007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H Bit Type Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R/W R/W R/W R/W R/W R/W Reserved Reserved TJATREF_SEL2 TJATREF_SEL1 TJATREF_SEL0 LTCK_SEL2 LTCK_SEL1 LTCK_SEL0 Table 4: Comparison of TJAT Input Reference Clock Selection Between the PM4388 PM4388 and the IDT82V2108 IDT82V2108 TJAT Reference Source PM4388 PM4388 - PLLREF[1:0] IDT82V2108 IDT82V2108 - TJATREF_SEL[2:0] CTCLK/8 (IDT-TSCCKA/8) CECLK (IDT-TSCCKB) RLCLK (IDT-LRCK) CTCLK (IDT-TSCCKA) XCLK/24 XCLK/24 (IDT-XCK/24 IDT-XCK/24) CECLK (IDT-TSCCKB) 0 0, 0 1 10 11 0 0, 0 1 000 001 010 011 100 Any others Table 5: Comparison of Transmit Clock Selection Between the PM4388 PM4388 and the IDT82V2108 IDT82V2108 Transmit Clock Reference Source PM4388 PM4388 - CTCLK, SMCLKO, OCLKSEL, FIFOBYP, ECLKSLV IDT82V2108 IDT82V2108 - LTCK_SEL[2:0] CTCLK/8 (IDT-TSCCKA/8) CECLK (IDT-TSCCKB) RLCLK (IDT-LRCK) CTCLK (IDT-TSCCKA) XCLK/24 XCLK/24 (IDT-XCK/24 IDT-XCK/24) TJAT_SM_CLK * CTCLK = 0, SMCLKO = 1, OCLKSEL = 0, FIFOBYP = 0 ECLKSLV = 1, FIFOBYP = 1 OCLKSEL = 1, FIFOBYP = 0 CTCLKSEL = 1, SMCLKO = 1, OCLKSEL = 0, FIFOBYP = 0 SMCLKO = 0, OCLKSEL = 0, FIFOBYP = 0 000 001 010 011 100 Any others Note: * TJAT_SM_CLK is a smoothed clock output from TJAT DPLL Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 6 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 2 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 RECEIVE CAS/RBS BUFFER corresponding indirect register (from 01H to 18H) can be read first. If the value of these four bits are different from the previous extracted A, B, C, D code, the content of Bit 3 ~ 0 is the updated A, B, C, D code. If the content of the four bits is the same as the previous extracted A, B, C, D code, then the Bit 3 ~ 0 of the corresponding indirect register (from 21H to 38H) should be read to get the updated A, B, C, D code. The relationship of the channel, the COSS[n] bit and the extracted signaling data indirect register are shown in Table 7. Figure - 3 shows an example of the processing procedure of the IDT82V2108 IDT82V2108. (Here take CH9 as an example.) In both the PM4388 PM4388 and the IDT82V2108 IDT82V2108, the updated signaling data in the corresponding indirect register (from 21H to 3FH) is not available for one full SF/ESF frame right after the COSS[n] indication is available. In the PM4388 PM4388, if the signaling data is needed in the same SF/ESF frame that the COSS[n] indication is available, the corresponding indirect register (from 10H to 1FH) can be read to get the updated A, B, C, D code. The relationship between the channel, the COSS[n] bit and the extracted signaling data indirect register are shown in Table 6. In the IDT82V2108 IDT82V2108, if the signaling data is needed in the same SF/ ESF frame that the COSS[n] indication is available, the Bit 3 ~ 0 of the Table 6: Relationship Between CH, COSS And Extracted Signaling Data Indirect Register In PM4388 PM4388 CH COSS[n] Indirect Register Address Bit Mask CH COSS[n] Indirect Register Address Bit Mask 1 2 . . . 15 16 COSS[1] COSS[2] . . . COSS[15] COSS[16] 10H 11H . . . 1EH 1FH F0H F0H . . . F0H F0H 17 18 . 23 24 COSS[17] COSS[18] . COSS[23] COSS[24] 10H 11H . 16H 17H 0FH 0FH . 0FH 0FH Reserved Start (COSS[9]=1) Table 7: Relationship Between CH, COSS And Extracted Signaling Data Indirect Register In IDT82V2108 IDT82V2108 CH COSS[n] 1 2 . . . 23 24 COSS[1] COSS[2] . . . COSS[23] COSS[24] Read RCRB register 09H to TEMPT * Indirect Register Address 01H 02H . . . 17H 18H 21H 22H . . . 37H 38H TEMPT=SIGX9 *? Y Read RCRB register 29H to SIGX9 N SIGX9=TEMPT End process Note: * TEMPT is an temporary variable register. * SIGX9 is the register to save the received signaling data for CH9. Figure 3. Example of Processing Procedure of IDT82V2108 IDT82V2108 Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 7 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 3 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 RECEIVE SYSTEM INTERFACE shows the corresponding pins that have different names but the same functions. The pin assignments and functions of the Receive System Interface in the IDT82V2108 IDT82V2108 is the same as that of the PM4388 PM4388. Table 8 Table 8: Pin Matching Between the PM4388 PM4388 & IDT82V2108 IDT82V2108 PM4388 PM4388 Pin IDT82V2108 IDT82V2108 Pin Function ID[x] ICLK[x]/ISIG[x] IFP[x] CICLK CIFP RSDn/MRSD[1:2] RSCKn/RSSIGn/MRSSIG[1:2] RSFSn/MRSFS[1:2] RSCCK/MRSCCK RSCFS/MRSCFS Output received data stream Output clock/extracted signaling bits Indicating framing pulses Common clock provided from the system side Common framing pulse provided from the system side The Receive System Interface of the IDT82V2108 IDT82V2108 supports both the Non-multiplexed bus (1.544Mb/s or 2.048Mb/s) and Multiplexed bus (8.192Mb/s). The PM4388 PM4388 only supports Non-multiplexed bus. To perform the same function as the PM4388 PM4388, the RSCCK8M bit (b3, T1/J1001H T1/J1001H) in the IDT82V2108 IDT82V2108 should be set to 0 (default) to disable the Multiplexed bus. The Receive System Interface of the IDT82V2108 IDT82V2108 in the Receive Clock Slave Mode supports double clock mode (the bit rate of the backplane is double of the 2.048Mb/s or 8.192Mb/s). The PM4388 PM4388 does not support the double clock mode. To perform the same function as the PM4388 PM4388, the CMS bit (b4, T1/J1-078H T1/J1-078H) in the IDT82V2108 IDT82V2108 should be set to 0 (default) to disable the double clock mode. In the Receive System Interface, the default timing between the framing pulses and the data is different between the PM4388 PM4388 and the IDT82V2108 IDT82V2108. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 8 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 0 (the ID[x], ISIG[x], IFP[x] are updated on the falling edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 4. 3.1 IN RECEIVE CLOCK SLAVE MODE - CASE 1 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 0 (the bit rate of data on the back-plane is 1.544Mb/s); - CIFPFALL (b1, 003H) = 0 (the common ingress frame pulse is sampled on the rising edge of CICLK); CIFP CICLK IFP[x] ID[x] 1 2 3 4 5 6 7 8 F 1 2 3 CH24 4 5 6 7 8 1 2 CH1 3 4 5 CH2 Figure 4. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 1 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 5. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 0; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 0; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 0. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 F 1 2 CH24 3 4 5 6 7 CH1 8 1 2 3 4 5 CH2 Figure 5. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 1 To achieve the same default functional timing as the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Time Slot Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011000" - BOFF_EN (b3, T1/J1-078H T1/J1-078H) = 0. Generally, the IDT82V2108 IDT82V2108 does not support the Channel Offset and Bit Offset for the 1.544Mb/s data rate, the above setting is just provided for the equivalent functional timing as that of the PM4388 PM4388. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 9 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 1 (the ID[x], ISIG[x], IFP[x] are updated on the rising edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 6. 3.2 IN RECEIVE CLOCK SLAVE MODE - CASE 2 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 0 (the bit rate of data on the back-plane is 1.544Mb/s); - CIFPFALL (b1, 003H) = 0 (the common ingress frame pulse is sampled on the rising edge of CICLK); CIFP CICLK IFP[x] 1 ID[x] 2 3 4 5 6 7 8 F 1 2 3 CH24 4 5 6 7 8 1 2 CH1 3 4 5 CH2 Figure 6. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 2 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 7. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 0; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 0; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 1. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 F 1 2 CH24 3 4 5 6 7 8 CH1 1 2 3 4 5 CH2 Figure 7. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 2 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011000" - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = "0". Generally, the IDT82V2108 IDT82V2108 does not support the Channel Offset and Bit Offset for the 1.544Mb/s data rate, the above setting is just provided for the equivalent functional timing as that of the PM4388 PM4388. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 10 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = "0" (the ID[x], ISIG[x], IFP[x] are updated on the falling edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 8. 3.3 IN RECEIVE CLOCK SLAVE MODE - CASE 3 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = "0" (the bit rate of data on the back-plane is 1.544Mb/s); - CIFPFALL (b1, 003H) = "1" (the common ingress frame pulse is sampled on the falling edge of CICLK); CIFP CICLK IFP[x] ID[x] 1 2 3 4 5 6 7 8 F 1 2 3 CH24 4 5 6 7 8 1 2 CH1 3 4 5 CH2 Figure 8. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 3 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 9. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 0; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 1; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 0. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 CH1 CH24 8 1 2 3 4 5 CH2 Figure 9. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 3 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011000"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 0. Generally, the IDT82V2108 IDT82V2108 does not support the Channel Offset and Bit Offset for the 1.544Mb/s data rate, the above setting is just provided for the equivalent functional timing as that of the PM4388 PM4388. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 11 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 1 (the ID[x], ISIG[x], IFP[x] are updated on the rising edge of CICLK). The default functional timing diagram of the Receive System Interface in PM4388 PM4388 is shown in Figure - 10. 3.4 IN RECEIVE CLOCK SLAVE MODE - CASE 4 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 0 (the bit rate of data on the back-plane is 1.544Mb/s); - CIFPFALL (b1, 003H) = 1 (the common ingress frame pulse is sampled on the falling edge of CICLK); CIFP CICLK IFP[x] ID[x] 1 2 3 4 5 6 7 8 F 1 2 3 CH24 4 5 6 7 8 1 2 3 4 5 CH2 CH1 Figure 10. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 4 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 11. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 0; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 1; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 1. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 F 1 2 CH24 3 4 5 6 7 CH1 8 1 2 3 4 5 CH2 Figure 11. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 4 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011000"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 0. Generally, the IDT82V2108 IDT82V2108 does not support the Channel Offset and Bit Offset for the 1.544Mb/s data rate, the above setting is just provided for the equivalent functional timing as that of the PM4388 PM4388. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 12 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 0 (the ID[x], ISIG[x], IFP[x] are updated on the falling edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 12. 3.5 IN RECEIVE CLOCK SLAVE MODE - CASE 5 When the PM4388 PM4388 is set as the follows: - CICLK2M bit (b4, 001H) = 1 (the bit rate of data on the back-plane is 2.048Mb/s); - CIFPFALL (b1, 003H) = 0 (the common ingress frame pulse is sampled on the rising edge of CICLK); CIFP CICLK IFP[x] ID[x] 1 2 3 4 5 6 7 8 P X X CH24 X X X X F 1 2 3 4 5 6 CH2 DUMMY Figure 12. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 5 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 13. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 1; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 0; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 0. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 P X X CH24 X X X X F DUMMY 1 2 3 4 5 6 CH1 Figure 13. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 5 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0000000"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 1; - BOFF_[2:0] (b2~0, T1/J1-078H T1/J1-078H) = "000". Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 13 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 1 (the ID[x], ISIG[x], IFP[x] are updated on the rising edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 14. 3.6 IN RECEIVE CLOCK SLAVE MODE - CASE 6 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 1 (the bit rate of data on the back-plane is 2.048Mb/s); - CIFPFALL (b1, 003H) = 0 (the common ingress frame pulse is sampled on the rising edge of CICLK); CIFP CICLK IFP[x] 1 ID[x] 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 DUMMY CH24 4 5 6 CH2 Figure 14. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 6 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 15. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 1; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 0; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 1. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 P X X CH24 X X X X F 1 DUMMY 2 3 4 5 6 CH1 Figure 15. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 6 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011111"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 0. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 14 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 0 (the ID[x], ISIG[x], IFP[x] are updated on the falling edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 16. 3.7 IN RECEIVE CLOCK SLAVE MODE - CASE 7 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 1 (the bit rate of data on the back-plane is 2.048Mb/s); - CIFPFALL (b1, 003H) = 1 (the common ingress frame pulse is sampled on the falling edge of CICLK); CIFP CICLK IFP[x] ID[x] 1 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 5 6 CH2 DUMMY CH24 4 Figure 16. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 7 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 17. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 1; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 1; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 0. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 P X X CH24 X X X X F DUMMY 1 2 3 4 5 6 CH1 Figure 17. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 7 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0011111"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 0. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 15 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 - CICLKRISE (b0, 003H) = 1 (the ID[x], ISIG[x], IFP[x] are updated on the rising edge of CICLK). The default functional timing diagram of the Receive System Interface in the PM4388 PM4388 is shown in Figure - 18. 3.8 IN RECEIVE CLOCK SLAVE MODE - CASE 8 When the PM4388 PM4388 is set as the follows: - CICLK2M (b4, 001H) = 1 (the bit rate of data on the back-plane is 2.048Mb/s); - CIFPFALL (b1, 003H) = 1 (the common ingress frame pulse is sampled on the falling edge of CICLK); CIFP CICLK IFP[x] 1 ID[x] 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 DUMMY CH24 4 5 6 CH2 Figure 18. PM4388 PM4388 Receive Clock Slave Mode - Functional Timing 8 The default functional timing diagram of the Receive System Interface in the IDT82V2108 IDT82V2108 is shown in Figure - 19. For the same setting in the IDT82V2108 IDT82V2108 as the follows: - RSCCK2M (b4, T1/J1-001H T1/J1-001H) = 1; - RSCFSFALL (b1, T1/J1-003H T1/J1-003H) = 1; - RSCCKRISE (b0, T1/J1-003H T1/J1-003H) = 1. RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 6 7 8 P X X CH24 X X X X F DUMMY 1 2 3 4 5 6 CH1 Figure 19. IDT82V2108 IDT82V2108 T1 Receive Clock Slave Mode - Functional Timing 8 To achieve the same default functional timing as that of the PM4388 PM4388, the IDT82V2108 IDT82V2108 should be set by both the Channel Offset and Bit Offset as the follows: - TSOFF [6:0] (b6~0, T1/J1-077H T1/J1-077H) = "0000000"; - BOFF_EN(b3, T1/J1-078H T1/J1-078H) = 1; - BOFF_[2:0] (b2~0, T1/J1-078H T1/J1-078H) = "000". Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 16 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 3.10 HIGH IMPEDANCE OF THE RECEIVE SYSTEM INTERFACE The TRI[1:0] (b5~4, T1/J1-003H T1/J1-003H) in the IDT82V2108 IDT82V2108 can be used to set the RSDn and RSSIGn into high impedance state. The PM4388 PM4388 does not have these bits. To substitute the PM4388 PM4388, the TRI[1:0] should be set to "01" for normal operation 3.9 RECEIVE CHANNEL OFFSET AND BIT OFFSET The PM4388 PM4388 does not support the Channel Offset and Bit Offset. But the IDT82V2108 IDT82V2108 T1 mode supports the Channel offset and Bit Offset when the data rate in the system side is 2.048 Mb/s. The registers for configuring the Channel Offset and Bit Offset in the IDT82V2108 IDT82V2108 are T1/ J1-077H J1-077H and T1/J1-078H T1/J1-078H. To provide the equivalent functions as the PM4388 PM4388, these registers should be in their default states. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 17 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 4 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 TRANSMIT SYSTEM INTERFACE The functional timing of the Transmit System Interface in the IDT82V2108 IDT82V2108 is the same as that of the PM4388 PM4388. But the IDT82V2108 IDT82V2108 provides more options. To achieve the same functions as that of the PM4388 PM4388, the following bits should be configured properly. The pin assignment and functions of the Transmit System Interface in the IDT82V2108 IDT82V2108 is equivalent to that of the PM4388 PM4388. Table 9 shows the corresponding pins that have different names but the same functions. Table 9: Comparison of Transmit System Interface Between the PM4388 PM4388 and the IDT82V2108 IDT82V2108 PM4388 PM4388 Pin IDT82V2108 IDT82V2108 Pin Function ED[x] ESIG[x]/ECLK[x]/EFP[x] CEFP[x] CECLK CTCLK TSDn/MTSD[1:2] TSSIGn/TSFSn/MTSSIG[1:2] TSCFSn/MTSCFS[1:2] TSCCKB/MTSCCKB TSCCKA Input transmitted data stream Input external signaling bit streams / Output framing indication pulse * Input common framing pulses in Transmit Clock Slave mode Common clock provided from the system side Input a reference clock Note: * The IDT82V2108 IDT82V2108 does not support the Transmit Clock Master NxDS0 mode, and the corresponding gapped clock ECLK[x] is eliminated from this multi-function pin. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 18 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 4.2 ECLKFALL (B1, 004H) IN THE PM4388 PM4388 In Transmit Clock Master mode in the PM4388 PM4388, the data on ED[x] is sampled by the ECLK[x]. The active edge of ECLK[x] is selected by the ECLKFALL (b1, 004H) bit. In Transmit Clock Master mode in the IDT82V2108 IDT82V2108, the data on the TSDn is sampled by the line transmit clock LTCKn. The active edge of the LTCKn is selected by the TSDFALL (b1, T1/J1-004H T1/J1-004H) in the IDT82V2108 IDT82V2108. 4.1 EMODE[1:0] (B7~6, 005H) IN THE PM4388 PM4388 When the EMODE [1:0] (b7~6, 005H) = "00", the PM4388 PM4388 is configured in Transmit Clock Master NxDS0 Mode. Because the IDT82V2108 IDT82V2108 does not support the Transmit Clock Master NxDS0 mode, the EMODE[1:0] (b7~6, T1/J1-005H T1/J1-005H) in the IDT82V2108 IDT82V2108 can not be set to "00". Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 19 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 4.4 TRANSMIT MULTIPLEXED MODE AND TRANSMIT DOUBLE CLOCK MODE The PM4388 PM4388 does not support the Transmit Multiplexed mode or the Transmit Double Clock mode. But the IDT82V2108 IDT82V2108 supports the Transmit Multiplexed mode and the Transmit Double Clock mode. The corresponding bits are the CMS (b5, T1/J1-015H T1/J1-015H), the MTBS (b6, T1/J1015H T1/J1015H) and the RATE[1:0] (b3~2, T1/J1-005 T1/J1-005). To substitute the PM4388 PM4388, these bit should be set properly. 4.3 TRANSMIT CHANNEL OFFSET AND TRANSMIT BIT OFFSET The PM4388 PM4388 does not support the Transmit Channel Offset or Transmit Bit Offset. But the IDT82V2108 IDT82V2108 supports both the Transmit Channel Offset and the Transmit Bit Offset. The corresponding registers are T1/J1-014H T1/J1-014H and T1/J1-015H T1/J1-015H. These registers should be set in default value to substitute the PM4388 PM4388. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 20 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 5 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 HDLC CONTROLLER 6 In ESF mode, the PM4388 PM4388 provides one HDLC Controller for each framer, whereas the IDT82V2108 IDT82V2108 provides two HDLC Controllers for each framer. The #1 HDLC Controller in the IDT82V2108 IDT82V2108 performs the same function as that of the PM4388 PM4388, which is fixed to link to the Data Link in the DL of F bit. The #2 HDLC Controller in the IDT82V2108 IDT82V2108 can be configured by 070H and 071H registers to link to any bits in any channel in the selected Odd/Even frames. To substitute the PM4388 PM4388, the T1/J1-00D T1/J1-00D H register in the IDT82V2108 IDT82V2108 should be set as the follows to select the #1 HDLC Controller: - RHDLCSEL[1:0] = "00"; - THDLCSEL[1:0] = "00". Consequently, the #2 HDLC interrupt indication bits RHDLC#2 and THDLC#2 (b7, b3, T1/J1-009H T1/J1-009H) can be neglected when replacing the PM4388 PM4388 with the IDT82V2108 IDT82V2108. Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 RECEIVE PER-CHANNEL CONTROL The FIX bit and the POL bit in the SIGX Per-DS0 Configuration Data (b2~1, SIGX Indirect Register 40-57 H) in the PM4388 PM4388 are used to select how to manipulate the signaling bits on the ID[x] pin. These two bits are relocated to T1/J1 RPLC Per-Channel Configuration Registers (b1~0, RPLC Indirect Register 01H-18H 01H-18H) in the IDT82V21088 IDT82V21088. The functions and names of these two bits in the IDT82V2108 IDT82V2108 are the same as those in the PM4388 PM4388. 21 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 7 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 PRGD 8 In the PM4388 PM4388, eight PRGD circuits are integrated in the chip, and each framer has one PRGD circuit respectively. But in the IDT82V2108 IDT82V2108, there is only one PRGD circuit shared by all eight framers. So, in the T1/ J1 Pattern Generator/Detector Positioning /Control Register (T1/J100FH T1/J100FH), three bits (PRGDSEL[2:0]) are added in the IDT82V2108 IDT82V2108 to select which one of the eight framers will be linked to the PRGD. Consequently, there is only one set of PRGD registers in the IDT82V2108 IDT82V2108 (T1/ J1 - 060H ~ 06FH) instead of eight sets of PRDG registers in the PM4388 PM4388. (060H ~ 06FH for PRGD1, 0E0H ~ 0EFH for PRGD2, 160H ~ 16FH for PRGD3, 1E0H ~ 1EFH for PRGD4, 260H ~ 26FH for PRGD5, 2E0H ~ 2EFH for PRGD6, 360H ~ 36FH for PRGD7 and 3E0 H ~ 3EF H for PRGD 8). Part I: Converting the PM4388 PM4388 to the IDT82V2108 IDT82V2108 FRAME GENERATOR The FRESH bit (b7, T1/J1-040H T1/J1-040H) in the IDT82V2108 IDT82V2108 is used to optimize the FIFO in the Frame Generator circuit. There is no such a bit in the PM4388 PM4388. It is recommended to set this bit to 1 to initialize the FIFO and then set it to 0 for normal operation. 22 *Notice: The information in this document is subject to change without notice February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 PART II: MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS the comparison of Read Access Timing between the IDT82V2108 IDT82V2108 and the PM4388 PM4388, and Table 11 is the comparison of Write Access Timing between the IDT82V2108 IDT82V2108 and the PM4388 PM4388. There are some minor discrepancies of the control interface timing characteristics between the IDT82V2108 IDT82V2108 and the PM4388 PM4388. Table 10 is Table 10: Comparison of Read Access Timing Between the PM4388 PM4388 and IDT82V2108 IDT82V2108 Symbol Min. Parameter Max PM4388 PM4388 IDT82V2108 IDT82V2108 PM4388 PM4388 IDT82V2108 IDT82V2108 Units tSAR Address to Valid Read Set-up Time 10 0 ns tHAR Address to Valid Read Hold Time 5 0 ns tSALR Address to Latch Set-up Time 10 5 ns tHALR Address to Latch Hold Time 10 5 ns tVL Valid Latch Pulse Width 20 10 ns tSLR Latch to Read Set-up Time 0 0 ns tHLR Latch to Read Hold 5 0 ns tPRD Valid Read to Valid Data Propagation Delay 80 160 ns tZRD Valid Read Negated to Output Tri-state 20 20 ns tZINTH Valid Read Negated to INT High 50 185 ns tW2R Valid interval from last write to next read 150 ns tVRD Valid Read Width 150 ns Table 11: Comparison of Write Access Timing Between the PM4388 PM4388 and IDT82V2108 IDT82V2108 Symbol Min. Parameter Max PM4388 PM4388 IDT82V2108 IDT82V2108 PM4388 PM4388 IDT82V2108 IDT82V2108 Units tSAW Address to Valid Write Set-up Time 10 5 ns tSDW Data to Valid Write Set-up Time 10 0 ns tSALW Address to Latch Set-up Time 10 5 ns tHALW Address to Latch Hold Time 10 5 ns tVL Valid Latch Pulse Width 20 5 ns tSLW Latch to Write Set-up Time 0 tHLW Latch to Write Hold 5 5 ns tHDW Data to Valid Write Hold Time 5 5 ns 5 ns tHAW Address to Valid Write Hold Time 5 tVWR Valid Write Pulse Width 40 tW2W ns Write to Write Interval ns 100 Part II: Microprocessor Inter-face Timing Characteristics 23 *Notice: The information in this document is subject to change without notice ns February 24, 2003 IDT82V2108 IDT82V2108 CONVERTING DESIGNS USING THE PM4388 PM4388 TO THE IDT82V2108 IDT82V2108 APPENDICES The pins and blocks of the IDT82V2108 IDT82V2108 and the PM4388 PM4388 have different names but the same functions. The following two tables are the comparison. Table 13: Block Name Comparison PM4388 PM4388 Table 12: Pin Name Comparison PM4388 PM4388 IDT82V2108 IDT82V2108 RLD RLCLK ID ISIG IFP ICLK CIFP CICLK MID MISIG MIFP MCIFP LRD LRCK RSD RSSIG RSFS RSCK RSCFS RSCCK MRSD MRSSIG MRSFS MRSCFS MCICLK TLD TLCLK ED ESIG EFP CEFP CECLK MED MESIG MCEFP MCECLK CTCLK XCLK Appendices Explanation Line Receive Data Line Receive Clock Receive side System Data Receive side System Signaling Receive side System Frame Pulse Receive side System Clock Receive side System Common Frame Pulse Receive side System Common Clock Multiplexed Receive side System Data Multiplexed Receive side System Signaling Multiplexed Receive side System Frame Pulse Multiplexed Receive side System Common Frame Pulse MRSCCK Multiplexed Receive side System Common Clock LTD Line Transmit Data LTCK Line Transmit Clock TSD Transmit side System Data TSSIG Transmit side System Signaling TSFS Transmit side System Frame Pulse TSCFS Transmit side System Common Frame Pulse TSCCKB Transmit side System Common Clock B MTSD Multiplexed Transmit side System Data MTSSIG Multiplexed Transmit side System Signaling MTSCFS Multiplexed Transmit side System Common Frame Pulse MTSCCKB Multiplexed Transmit side System Common Clock B TSCCKA Transmit side System Common Clock A XCK Crystal Clock IDT82V2108 IDT82V2108 FRMR RDLC RBOC ALMI ELST SIGX RPSC IIF XBAS TDPR XBOC XIBC TPSC EIF FRMP RHDLC RBOM ALMD ELSB RCRB RPLC RESI FRMG THDLC TBOM IBCG TPLC TRSI 24 *Notice: The information in this document is subject to change without notice Explanation Frame Processor HDLC Receiver Bit-Oriented Message Receiver Alarm Detector Elastic Store Buffer Receive CAS/RBS Buffer Receive Payload Control Receive System Interface Frame Generator HDLC Transmitter Bit-Oriented Message Transmitter Inband Loopback Code Generator Transmit Payload Control Transmit System Interface February 24, 2003