IDT77155 GR-253-CORE DSC-3497/1 PX-128 IIDT77155 128-PIN A0/119 A1/120 A2/121

INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS ADVANCED INFORMATION IDT77155 Integrated Device Technology, Inc. KEY FEATURES

PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS ADVANCED INFORMATION IDT77155 IDT77155 Integrated Device Technology, Inc. KEY FEATURES · One chip ATM User Network Interface for 155.52 Mbps/ 51.84Mbps operating speed. · Full implementation of the SONET/SDH criteria according to Bellcore GR-253-CORE GR-253-CORE and ITU-T G.709, G.783. · Full implementation of the ATM physical layer according to CCITT I.432 and ATM Forum User Network Interface Specification. · Full-duplex 155.52 Mbps STS-3c/STM-1 or 51.84 Mbps STS-1 data with built-in clock/data recovery and clock synthesis. · Supports 4-cell PHY FIFO buffers for both transmit and receive directions with parity. · Provides GFC bits insertion and extraction. · UTOPIA Level 1 and Level 2 Interface. · Supports up to 4 PHYs for Multi-PHY connections with 2bit address and 8-bit data using UTOPIA 2 protocol. · Provides an 8-bit microprocessor bus interface for configuration, control and monitoring. · Low power CMOS · 128 pin PQFP Package (14 mm x 20 mm). DESCRIPTION The IDT77155 IDT77155 is a member of IDT's SWITCHStARTM family of products for Asynchronous Transfer Mode (ATM) networks. The IDT77155 IDT77155 is a integrated circuit that provides the SONET/SDH processing and ATM mapping functions of a 155 Mbps/51 Mbps ATM User Network Interface. Provides full compliance with SONET/SDH requirements and ATM Forum ATP2 TBYP RATE1 RATE0 TCLK TFPO XOFF TGFC TCP SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM TRCLKTRCLK+ Parallel to Serial TXCTXC+ Encoder redocnE Transmit SONET Framer Transmit UTOPIA Cell FIFO timsnarT MTA lleC OFIF TXD+ TXDRXDORXD- Decoder Receive UTOPIA Cell FIFO Receive SONET Framer RXD+ Serial to Parallel RXDO+ RRCLK.ceR klC TFCLK TWRENB TXPRTY TDAT[7:0] TSOC TCA TxADDR[1:0] MPHYEN RxADDR[1:0] TSEN RFCLK RRDENB RXPRTY RDAT[7:0] RSOC RCA Clk Gen. Clk Rec. RRCLK+ Micoprocessor Interface ALOS- RBYP LFO LF LF+ APT1 RCLK RALM RFP INT RST RD WR CS ALE A[7:0] D[7:0] RCP RGFC ALOS+ 3497 drw 01 NICStAR and SWITCHStAR are trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 8.03 SEPTEMBER 1996 DSC-3497/1 DSC-3497/1 1 IDT77155 IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE ADVANCED INFORMATION Commercial Temperature Range User Network Interface specifications. The IDT77155 IDT77155 provides both Transmission Convergence (TC) and Physical Media Dependent (PMD) sublayer functions of a 155.52 Mbps/51.84 Mbps ATM PHY suitable for ATM networks. The SONET/SDH interface provides the SONET/SDH overheads demultiplex and multiplex processing functions. The UTOPIA interface provides standardized control and communications to other components, such as Segmentation and Reassembly (SAR) controllers and ATM switches. The IDT77155 IDT77155 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of CMOS. IDT77155 IDT77155 TOP VIEW PX-128 PX-128 Vcc GND GND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND VCLK RATE[0] RATE[1] TSOC TXPRTY TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TCA TWRENB TFCLK RSOC RXPRTY Vcc GND RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] Vcc GND RDAT[1] RDAT[0] RCA RRDENB RFCLK TSEN GND 3497 drw 02 GND ATP1 RBYP LF+ LFLFO RXADDR[1] RXADDR[0] TXADDR[1] TXADDR[0] MPHYEN XOFF TCP TGFC TFPO TCLK Vcc GND RCLK RFP RGFC RCP Vcc GND RALM GND GND TBYP ATP2 AVcc AGND AVcc AGND AVcc TRCLKTRCLK+ AGND TXVcc TXC+ TXCTXD+ TXDTXGND Vcc GND Vcc GND RXDO+ RXDOAVcc RXDRXD+ ALOSALOS+ AGND AVcc AGND AVcc RRCLKRRCLK+ AGND AVcc AGND GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND ALE A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] Vcc GND D[3] D[2] D[1] D[0] PACKAGE PINOUT 8.03 2 IIDT77155 IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE ADVANCED INFORMATION Commercial Temperature Range PACKAGE DIMENSIONS 128 Draft Angle = 11°13° 1 A2 A1 e 0.20 Rad Typ. 128-Pin PQFP E1 9'-5" 8'-7" E 0.20 Rad Typ. 4° ± 4° A 2'-0" L D1 5'-10" b 3445 drw 03 D 6'-8" DIMENSIONS 128-PIN 128-PIN PQFP DImension Tolerance Letter (mm) A Max. +.10 A1 A2 +.17 D +.25 +.10 D1 E +.25 E1 +.10 L +15 e Basic b .05 Dimension (mm) 3.30 0.35 2.70 17.20 14.00 23.20 20.00 0.75 0.50 0.22 8.03 3 IDT77155 IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE ADVANCED INFORMATION Commercial Temperature Range PIN DESCRIPTIONS Symbol Name I/O Description A0-A7 Address I Address bus to select specific registers in the register set. The address pin A7 has an integral pull-down resistor. Pin #: A0/119 A0/119, A1/120 A1/120, A2/121 A2/121, A3/122 A3/122, A4/123 A4/123, A5/124 A5/124, A6/125 A6/125, A7/126 A7/126 AGND Analog Ground G These pins should be physically isolated from the other ground pins. Pin #: 5, 7, 11, 29, 31, 35, 37 Address Latch Enable I Latches the address bus when low, and is transparent when high. It allows interfacing to a multiplexed address/data bus. ALE has an integral pull-up resistor. Pin #: 127 ALOS+ ALOS- Analog Loss of Signal I Differential inputs indicate a loss of receive signal power. When ALOS+/- is asserted, data on the RXD+/- inputs is squelched and the receive data/clock recovery PLL switches to the reference clock. ALOS+/- has an effect only when RBYP is disabled. These inputs must be dc-coupled. Pin #: ALOS+ 28, ALOS- 27 ATP1 Test pin I Test pin for the transmit clock synthesis logic. When asserted, the TNB output of the clock synthesis block is reflected on the LFO pin. ATP1 has an integral pull-down resistor. Pin #: 40 ATP2 Test pin I Test pin for the receive clock/data recovery logic. When asserted, the CNB output of the clock recovery block is reflected on the LF-pin. ATP2 has an integral pull-down resistor. Pin #: 3 AVcc Analog Power P These power pins should be physically isolated from the other power pins and connected to a well coupled 5v dc source. Pin #: 4, 6, 8, 24, 30, 32, 36 CS Chip Select I Active low chip select to access registers. Pin #: 100 D1-D7 Data I/O Bidirectional data bus for register access during register reads and writes. Pin #: D0/109 D0/109, D1/110 D1/110, D2/111 D2/111, D3/112 D3/112, D4/115 D4/115, D5/116 D5/116, D6/117 D6/117, D7/118 D7/118 GND Ground G Core, Ring and Thermal Grounds. Pin #: 1, 19, 21, 38, 39, 56, 62, 64, 65, 72, 80, 102, 103, 106, 113, 128 INT Interrupt O Open drain interrupt signal which goes low when an interrupt source is active and unmasked open from within the chip. This signal is cleared by appropriate reads to the interrupt registers. INT is an open-drain output. Pin #: 108 LF+ LF- Loop Filter O Special pin to output CAP voltage of the receive data/clock recovery logic when ATP2 is enabled. Reference clock signal of the receive data/clock recovery logic. Pin #: LF+/42, LF-/43 LF-/43 LFO Special O Special pin to output CAP voltage of the transmit clock synthesis logic when ATP1 is enabled. Pin #: 44 MPHYEN Mult-phy Enable I When asserted, the multiphy enable signal converts the UTOPIA interface to be fully compliant with the UTOPIA level-2 specification. In this mode, the TXADDR[1:0] and RXADDR[1:0] bits determine the address of the device to be addressed. The default operation of the chip is in single-phy UTOPIA level-1 mode. MPHYEN pin has an integral pulldown resistor. Pin #: 49 RALM Receive Alarm O Output is asserted if line alarm indication signal (LAIS), path alarm indication signal (PAIS), loss of signal (LOS), loss of frame (LOF), or loss of cell delineation (LOC) is detected in the receive logic. RALM is updated on the rising edge of RCLK. Pin #: 63 RATE0 RATE1 Line Rate I RATE inputs select the frame format and line rates for both the transmit and receive functions RATE(1:0) 11 155.52 Mb/s, STS-3c / STM-1 10 51.84 Mb/s, STS-1 0X Reserved ALE The RATE inputs have integral pull-up resistors, so the default is STS-3c Pin #: RATE0/98 RATE0/98, RATE1/97 RATE1/97 8.03 4 IIDT77155 IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE ADVANCED INFORMATION Commercial Temperature Range PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O Description RBYP Receive Bypass I Active high RBYP input disables clock recovery. If enabled, the receive different serial data RXD+/- is sampled on the rising edged of the receive differential reference clock RRCLK+/-. If RBYP is disabled, the receive clocks are recovered from RXD+/- bit stream. RBYP has an integral pull down resistor. Pin #: 41 RCA/ TXEMPTY Receive Cell Available O This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy protocol. Pin #: 69 RCLK Receive Clock O Provides a timing reference, and is a divide-by-8 version of tri-covered clock when RBYP is disabled or RRCLK+/- when RBYP is enabled. Pin #: 57 RCP Receive Cell O Receive GFC pulse indicates the start of the four generic flow control bits (GFC) in the RGFC Pulse output. RCP is coincident with the most significant GFC bits. RCP is updated on the rising edge of RCLK. Pin #: 60 RD Read I Active low read signal to read contents of addressed register. The data bus is driven by the contents of the addresses register when the read signal is asserted along with the chip select (CS) signal. Pin #: 105 RDAT0RDAT7 Receive Data O The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the level-2 protocol. Pin #: RDAT0/70 RDAT0/70, RDAT1/71 RDAT1/71, RDAT2/74 RDAT2/74, RDAT3/75 RDAT3/75, RDAT4/76 RDAT4/76, RDAT5/77 RDAT5/77, RDAT6/78 RDAT6/78, RDAT7/79 RDAT7/79 RFCLK Receive FIFO Clock I The receive ATM clock from the ATM layer