IDT74LVCH162721A 20-BIT LVCH162721A MIL-STD-883 DSC-4940/2 - Datasheet Archive

 

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH

 

IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the LVCH162721A LVCH162721A are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The LVCH162721A LVCH162721A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The LVCH162721A LVCH162721A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. · Typical tSK(o) (Output Skew) < 250ps · ESD > 2000V per MIL-STD-883 MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · CMOS power levels (0.4µ W typ. static) µ · All inputs, outputs, and I/O are 5V tolerant · Supports hot insertion · Available in TSSOP and TVSOP packages DRIVE FEATURES: · Balanced Output Drivers: ±12mA · Low switching noise APPLICATIONS: · 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM OE 1 56 CLK CLKEN 29 CE C1 55 D1 2 Q1 1D To 19 Other Channels The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4940/2 DSC-4940/2 IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol 1 56 Q1 2 55 Q2 3 54 GND 4 53 Q3 5 52 D3 Q4 6 51 D4 VCC 7 50 VCC Q5 8 49 D5 Q6 9 48 D6 Q7 10 47 D7 GND 11 46 GND Q8 12 45 D8 Q9 13 44 D9 Q10 14 43 D10 Q11 15 42 D11 Q12 16 41 D12 Q13 17 40 D13 GND 18 39 GND Q14 19 38 Q15 20 Q16 21 VCC 22 35 VCC Q17 23 34 D17 Q18 24 33 D18 GND 25 32 GND Q19 26 31 27 30 D20 28 29 CLKEN DC Output Current ­50 to +50 mA Continuous Clamp Current, VI < 0 or VO < 0 ­50 mA Continuous Current through each VCC or GND ±100 mA D19 Q20 °C ICC ISS GND V ­65 to +150 IIK IOK D2 ­0.5 to +6.5 Storage Temperature IOUT D1 Terminal Voltage with Respect to GND TSTG CLK Max VTERM OE Description NC Unit NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. CIN Input Capacitance VIN = 0V 4.5 6 Unit pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description OE 3­State Output Enable Input (Active LOW) Dx Data Inputs(1) D14 Qx 3-State Outputs 37 D15 CLK Clock Input 36 D16 CLKEN NC Clock Enable Input (Active LOW) No Internal Connection NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH FLIP-FLOP)(1) Inputs Outputs OE CLK Dx Qx L H X X Q(2) L L H H L L L L L L L or H X Q(2) H TSSOP/ TVSOP TOP VIEW CLKEN X X X Z NOTES: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High-Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2 IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = ­40°C to +85°C VIL Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 - - V 2 - - VCC = 2.3V to 2.7V - - 0.7 VCC = 2.7V to 3.6V VIH Min. VCC = 2.7V to 3.6V Symbol - - 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V - - ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V - - ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO 5.5V - - ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = ­18mA - ­0.7 ­1.2 V VH ICCL ICCH ICCZ ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC - - 100 - - 10 mV µA 3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND - - - - 10 500 µA Min. Typ.(2) Max. Unit ­ 75 - - µA VI = 0.8V 75 - - VI = 1.7V - - - VI = 0.7V - - - VI = 0 to 3.6V - - ±500 IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current Test Conditions VCC = 3V VI = 2V IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 µA µA IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC ­ 0.2 - V IOH = ­ 4mA 1.9 - VCC = 2.3V to 3.6V IOH = ­ 0.1mA VCC = 2.3V IOH = ­ 6mA 2.2 - IOH = ­ 8mA 2 - IOH = ­ 6mA 2.4 - IOH = ­ 12mA 2 - VCC = 2.3V to 3.6V IOL = 0.1mA - 0.2 VCC = 2.3V IOL = 4mA - 0.4 IOL = 6mA - 0.55 IOL = 4mA - 0.4 IOL = 8mA - 0.6 IOL = 6mA - 0.55 IOL = 12mA Output LOW Voltage - IOH = ­ 4mA VCC = 3V VOL 1.7 VCC = 2.7V - 0.8 VCC = 2.7V VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = ­ 40°C to + 85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Test Conditions Typical CL = 0pF, f = 10Mhz Unit Power Dissipation Capacitance Outputs disabled pF SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH tPHL Min. Max. Unit 6.6 2 5.8 ns 1.5 7.6 1.5 6.6 ns 1.5 5.9 1.5 5.6 ns CLK to Qx Output Enable Time Max. 2 Propagation Delay tPZH VCC = 3.3V ± 0.3V Min. tPZL OE to Qx tPHZ Output Disable Time tPLZ OE to Qx tSU Set-up Time, data before CLK 3.6 - 3.1 - ns tSU Set-up Time, CLKEN before CLK 3.1 - 2.7 - ns tH Hold Time, data after CLK 0 - 0 - ns tH Hold Time, CLKEN after CLK 0 - 0 - ns tW Pulse Duration, CLK HIGH or LOW 3.3 - 3.3 - ns Output Skew(2) - - - 500 ps tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = ­ 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V tPLH VLOAD 6 6 2 x Vcc 2.7 2.7 Vcc tPHL OUTPUT V VIH tPHL tPLH Unit V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF LVC Link Propagation Delay Pulse (1, 2) Generator VIN tPZL GND VOUT OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH D.U.T. 500 RT VIH VT 0V CONTROL INPUT Open 500 DISABLE ENABLE VLOAD VCC VIH VT 0V OPPOSITE PHASE INPUT TRANSITION CL tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC Link LVC Link Test Circuit for All Outputs Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. DATA INPUT SWITCH POSITION tSU Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open OUTPUT 1 tPLH1 tSK (x) tSK (x) tPLH2 tSU tH LOW-HIGH-LOW PULSE VOH VT VOL LVC Link VT tW HIGH-LOW-HIGH PULSE VOH VT VOL OUTPUT 2 tREM Set-up, Hold, and Release Times VIH VT 0V tPHL1 tH TIMING INPUT Test INPUT VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V VT LVC Link Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 LVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVCH162721A IDT74LVCH162721A 3.3V CMOS 20-BIT 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT LVC X XX Bus-Hold Temp. Range XX Family XXX XX Device Type Package PA PF Thin Shrink Small Outline Package Thin Very Small Outline Package 721A 20-Bit Flip-Flop with 3-State Outputs 162 H Bus-hold 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Double-Density with Resistors, ±12mA ­40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: logichelp@idt.com (408) 654-6459