IDT74FST6800 10-BIT FST6800 MIL-STD-883 P24-1 SO24-2 SO24-8 A1-10 B1-10 - Datasheet Archive

 

PRELIMINARY 10-BIT BUS SWITCH WITH PRECHARGE Integrated Device Technology, Inc. The FST6800 belong to IDT's family of Bus

 

IDT74FST6800 IDT74FST6800 PRELIMINARY 10-BIT 10-BIT BUS SWITCH WITH PRECHARGE Integrated Device Technology, Inc. The FST6800 FST6800 belong to IDT's family of Bus switches. Bus switch devices perform the function of connecting or isolating two ports without providing any inherent current sink or source capability. Thus they generate little or no noise of their own while providing a low resistance path for an external driver. These devices connect input and output ports through an nchannel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts and the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET, the FET is turned off. The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. The FST6800 FST6800 provides a 10-Bit TTL-compatible interface. The pin serves as the enable pin. When is high, A and B ports are isolated and B outputs are precharged to the BIASV voltage, through the equivalent of a 10K resistor. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION FEATURES: · · · · Bus switches provide zero delay paths Low switch on-resistance: 5 TTL-compatible input and output levels ESD > 2000V per MIL-STD-883 MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · Available in QSOP, SOIC and PDIP DESCRIPTION: ON ON BIASV ON VCC 2 23 B1 A2 3 22 B2 A3 4 21 B3 A4 B1 24 A1 A1 1 5 20 B4 19 B5 18 B6 P24-1 P24-1 SO24-2 SO24-2 SO24-8 SO24-8 7 A7 8 17 B7 A8 9 16 B8 A9 10 15 B9 A10 11 14 B10 GND B10 6 A6 A10 A5 12 13 BIASV ON DIP/SOIC/QSOP TOP VIEW 3261 drw 01 3261 drw 02 PIN DESCRIPTION Pin Names A1-10 A1-10, B1-10 B1-10 ON BIASV I/O I/O Description Buses A, B I Bus Switch Enable (Active LOW) I Bias Voltage 3261 tbl 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES ©1995 Integrated Device Technology, Inc. AUGUST 1995 10.7 DSC-4667/- DSC-4667/- 1 IDT74FST6800 IDT74FST6800 10-BIT 10-BIT BUS SWITCH WITH PRECHARGED OUTPUTS COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) FUNCTION TABLE 0 to +70 °C TBIAS Temperature Under Bias ­55 to +125 °C TSTG Storage Temperature ­55 to +125 °C PT Power Dissipation 0.5 W IOUT DC Output Current ­60 to +120 mA ON Commercial Unit ­0.5 to +7.0 V TA Rating Terminal Voltage with Respect to GND Operating Temperature L B1-B10 B1-B10 A1-A10 A1-A10 Description Connect H BIASV Precharge 3261 tbl 03 3261 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Input, I/O and VCC terminals. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Conditions Typ. Max. Unit VIN = 0V 4 pF Capacitance COUT Output VOUT = 0V 5 pF Capacitance 3261 tbl 04 NOTE: 1. Capacitance is characterized but not tested. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = ­40°C to +85°C, VCC = 5.0V ±10%; BIASV = 0 to VCC Parameter Input HIGH Voltage Test Conditions(1) Guaranteed Logic HIGH for Control Inputs Min. 2.0 Typ.(2) - Max. - Unit V VIL Input LOW Voltage Guaranteed Logic LOW for Control Inputs - - 0.8 V II H Input HIGH Current - - ±1 µA II L Input LOW Voltage IO Precharge Output Current VCC = Min., BIASV = 2.4V, VO = 0V I OZH High Impedance Output Current VCC = Max. I OZL (3-State Output pins) I OS Short Circuit Current VIK Clamp Diode Voltage Symbol VIH VCC = Max. VI = VCC I CC Switch On Quiescent Power Supply Current - ±1 - - mA VO = VCC - - ±1 µA VO = GND - - ±1 - 300 - mA - ­0.7 ­1.2 V VCC = Min., VIN = 0.0V ION = 64mA - - 6 VCC = Min., VIN = 2.4V ION = 15mA RON Resistance(4) - 0.25 - - 12 VCC = Max., VI = GND or V CC - 0.1 10 VI = GND VCC = Max., VO = GND(3) VCC = Min., IIN = ­18 mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Measured by voltage drop between ports at indicated current through the switch. 10.7 µA 3261 tbl 05 2 IDT74FST6800 IDT74FST6800 10-BIT 10-BIT BUS SWITCH WITH PRECHARGED OUTPUTS COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) ICCD Total Power Supply Current (6) IC Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open Enable Pin Toggling 50% Duty Cycle VCC = Max. Outputs Open Enable Pin Toggling (10 Switches Toggling) fi = 10MHz 50% Duty Cycle Min. - Typ.(2) 0.5 Max. 1.5 Unit mA VIN = VCC VIN = GND - 30 40 µA/ MHz/ Switch VIN = VCC VIN = GND - 3.0 4.0 mA VIN = 3.4 VIN = GND - 3.3 4.8 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fiN) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency N = Number of SwitchesToggling at fi All currents are in milliamps and all frequencies are in megahertz. 3261 tbl 06 SWITCHING CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = ­40°C to +85°C, VCC = 5.0V ±10% Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Description Data Propagation Delay Ai, Bi to Bi, Ai (3,4) Switch Turn on Delay to Ai, Bi Switch Turn off Delay to Ai, Bi (3) Condition(1) CL = 50pF RL = 500 Min.(2) - Com'l. Typ. - Max. 0.25 Unit ns ON 1.5 - 6.5 ns ON 1.5 - 5.5 ns 3261 tbl 07 NOTES: 1. See test circuit and waveforms. 2. Minimum limits guaranteed but not tested. 3. This parameter is guaranteed by design but not tested. 4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 50 pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 10.7 3 IDT74FST6800 IDT74FST6800 10-BIT 10-BIT BUS SWITCH WITH PRECHARGED OUTPUTS COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION Test V CC Open Drain Disable Low 7.0V 500 Pulse Generator Open All Other Tests DEFINITIONS: 3261 lnk 08 CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. D.U.T. 50pF RT Closed Enable Low V OUT VIN Switch 500 CL 3261 lnk 03 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 3261 drw 05 3261 drw 04 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 3261 drw 06 SWITCH OPEN 0V tPLZ 3.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 3261 drw 07 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 10.7 4 IDT74FST6800 IDT74FST6800 10-BIT 10-BIT BUS SWITCH WITH PRECHARGED OUTPUTS COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FST XX Temp. Range Device Type X Package X Process Blank Commercial P SO Q Plastic DIP Small Outline IC Quarter-size Small Outline Package 6800 10-Bit Bus Switch with Precharged Outputs 74 ­40°C to +85°C 3261 drw 08 10.7 5