IDT74FCT652T/AT/CT/DT FCT652T DSC-5508/- P24-1 D24-1 FCT652AT FCT652CT FCT652DT - Datasheet Archive

 

FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE FAST CMOS OCTAL TRANSCEIVER/ REGISTER (3-STATE)

 

IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE FAST CMOS OCTAL TRANSCEIVER/ REGISTER (3-STATE) IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FEATURES: DESCRIPTION: - - - - The FCT652T FCT652T consists of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT652T FCT652T utilizes GAB and GBA signals to control the transceiver functions. - - - - - - Low input and output leakage 1µ A (max.) Extended commercial range of ­40°C to +85°C CMOS power levels True TTL input and output compatibility · VOH = 3.3V (typ.) · VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Available in PDIP, SOIC, SSOP, and QSOP packages Std., A, C and D speed grades High drive outputs (-15mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" SAB and SBA control pins are provided to select either real- time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data and a high selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. FUNCTIONAL BLOCK DIAGRAM G AB G BA CPB A SBA CPA B SAB B REG ONE OF EIGHT CHANNELS 1D C1 A1 A REG B1 1D C1 TO SEVEN O THE R CHANNELS COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1999 1 c 1999 Integrated Device Technology, Inc. DSC-5508/- DSC-5508/- IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) 1 24 SAB 2 23 3 22 A1 4 21 GBA A2 5 20 B1 19 B2 18 B3 P24-1 P24-1 D24-1 D24-1 SO 24-2 SO 24-7 SO 24-8 Terminal Voltage with Respect to GND ­0.5 to VCC+0.5 V Storage Temperature ­65 to +150 °C IOUT V CC Max. ­0.5 to +7 TSTG SBA CPAB Rating Terminal Voltage with Respect to GND VTERM(3) CPBA GAB Symbol VTERM(2) Unit V DC Output Current ­65 to +120 mA 8T-link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. A3 6 A4 7 A5 8 17 B4 3. Outputs and I/O terminals only. A6 9 16 B5 CAPACITANCE (TA = +25OC, f = 1.0MHz) A7 10 15 B6 A8 11 14 B7 GND 12 13 2. Inputs and Vcc terminals only. Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 6 Max. 10 COUT Output Capacitance VOUT = 0V 8 12 Unit pF pF 8T-link B8 NOTE: 1. This parameter is measured at characterization but not tested. PDIP/ SOIC/ SSOP/ QSOP TOP VIEW PIN DESCRIPTION Pin Names A1 - A8 B1 - B8 CPAB, CPBA SAB, SBA GAB, GBA 2 Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE(2) Inputs Data I/O GAB GBA CPAB CPBA SAB SBA A1 - A8 B1 - B8 L L X H L L L L H H H H H H H X L L L H H L H or L H or L X X X H or L H or L H or L H or L X H or L X X H or L X X X X X X X X L H H X X X X X X L H X X H Input Input Input Input Unspecified(1) Output Output Unspecified(1) Output Input Input Input Input Output Output Output Operation or Function Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus NOTES: 1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2. H = HIGH L = LOW X = Don't Care = LOW-to-HIGH transition. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. 3 IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) BUS A G AB L COMMERCIAL TEMPERATURE RANGE BUS B G BA L CPAB X CPBA X BUS A SAB X G AB H SBA L REAL-TIME TRANSFER BUS B TO A BUS A G BA H BUS B CPAB X CPBA X SAB L SBA X REAL-TIME TRANSFER BUS A TO B BUS A BUS B G AB G BA CPAB CPBA SAB SBA X H X X X L X X X H X G BA L CPAB H or CPBA H or X L G AB H BUS B X TRANSFER STORES DATA TO A AND/OR B STORAGE FROM A AND/OR B 4 SAB H SBA H IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40°C to +85°C, VCC = 5.0V ± 5% Symbol VIH Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Min. 2 Typ.(2) - Max. - Unit V VIL Input LOW Level Guaranteed Logic LOW Level IIH Input HIGH Current(4) - - 0.8 V VCC = Max. IIL Input LOW Current(4) µA IOZH High Impedance Output Current IOZL (3-State Output pins)(4) - - ±1 II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) - - ±1 µA VIK Clamp Diode Voltage VCC = Min., IIN = ­18mA - ­0.7 ­1.2 V VH Input Hysteresis ICC Quiescent Power Supply Current VI = 2.7V - ±1 - - ±1 VO = 2.7V VCC = Max. - VI = 0.5V - - ±1 VO = 0.5V µA - - 200 - mV VCC = Max., VIN = GND or VCC - 0.01 1 mA Min. 2.4 Typ.(2) 3.3 Max. - Unit V OUTPUT DRIVE CHARACTERISTICS Test Conditions(1) IOH = ­8mA Symbol VOH Parameter Output HIGH Voltage VCC = Min. VIN = VIH or VIL IOH = ­15mA 2 3 - VOL Output LOW Voltage VCC = Min. IOL = 64mA - 0.3 0.55 V VIN = VIH or VIL IOS Short Circuit Current VCC = Max., VO = GND(3) ­60 ­120 ­225 mA IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO 4.5V - - ±1 µA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = ­55°C. 5. This parameter is guaranteed but not tested. 5 IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) IC Total Power Supply Current(6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open GAB = GBA = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle GAB = GBA = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle GAB = GBA = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. - Typ.(2) 0.5 Max. 2 Unit mA VIN = VCC VIN = GND - 0.15 0.25 mA/ MHz VIN = VCC VIN = GND - 1.5 3.5 mA VIN = 3.4 VIN = GND - 2 5.5 VIN = VCC VIN = GND - 3.8 7.3(5) VIN = 3.4 VIN = GND - 6 16.3(5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6 IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT652T FCT652T Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW Parameter Propagation Delay Bus to Bus Output Enable Time, GAB, GBA to Bus Output Disable Time, GAB, GBA to Bus Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Set-up Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width, HIGH or LOW (3) Condition(1) CL = 50pF RL = 500 Min.(2) FCT652AT FCT652AT Max. Min.(2) 2 9 2 FCT652CT FCT652CT FCT652DT FCT652DT Max. Min.(2) Max. Min.(2) Max. 2 6.3 1.5 5.4 1.5 4.4 Unit ns 14 2 9.8 1.5 7.8 1.5 5 ns 2 9 2 6.3 1.5 6.3 1.5 4.3 ns 2 9 2 6.3 1.5 5.7 1.5 4.4 ns 2 11 2 7.7 1.5 6.2 1.5 5 ns 4 - 2 - 2 - 1.5 - ns 2 - 1.5 - 1.5 - 1 - ns 6 - 5 - 5 - 3 - ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 7 IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC Test 7.0V Switch Open Drain 500 Disable Low V OUT V IN Pulse Generator D.U.T. All Other Tests 50pF R Closed Enable Low T C Open 8-link 500 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. L O ctal lin k PULSE WIDTH SET-UP, HOLD, AND RELEASE TIMES 3V 1.5V 0V 3V 1.5V 0V DATA INPUT tH t SU TIM ING INPUT ASYNCHRONOUS C ONTROL PRES ET CLEAR ETC. SYNCHRO NOUS CONTRO L PRES ET CLEAR CLOCK ENABLE ETC. t REM t SU LO W -HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW -HIGH PULSE 1.5V 3V 1.5V 0V tH O ctal lin k O ctal lin k PROPAGATION DELAY ENABLE AND DISABLE TIMES ENAB LE SAM E PHASE INPUT TRANSITION t PLH t PH L OUTPUT t PLH OPPOSITE P HASE INPUT TRANSITION t PH L 3V 1.5V 0V DISA BLE 3V CO NTROL INPUT 1.5V t PZL V OH 1.5V V OL OUTPUT NO RM A LLY LO W 3V 1.5V 0V SW ITCH CLOSE D O ctal lin k SW ITCH OPEN 3.5V 3.5V 1.5V 0.3V t PZH OUTPUT NO RM A LLY HIGH 0V t PLZ V OL t PHZ 0.3V V OH 1.5V 0V 0V O ctal lin k NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 8 IDT74FCT652T/AT/CT/DT IDT74FCT652T/AT/CT/DT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FC T Tem perature Range X Fam ily XXXX Device Type X Package X Process/ Tem perature Range Blank Com m ercial P D SO PY Q Plastic DIP (P24-1 P24-1) CERDIP (D24-1 D24-1) Small Outline IC (SO 24-2) Shrink Sm all Outline Package (SO24-7 SO24-7) Quarter-size Sm all Ou tline Package (SO24-8 SO24-8) 652T 652AT 652AT 652CT 652CT 652DT 652DT Octal Transceiver/R egister (3-State) Blank High D rive 74 - 40°C to +8 5°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9