IDT72V51546 IDT72V51556 DSC-5904/9 IDT72V51546/72V51556 BB256-1 D32-D35 ID1-A10 - Datasheet Archive

 

(32 QUEUES) 36 BIT WIDE CONFIGURATION IDT72V51546 IDT72V51556 1,179,648 bits 2,359,296 bits · · FEATURES: ·

 

3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION IDT72V51546 IDT72V51546 IDT72V51556 IDT72V51556 1,179,648 bits 2,359,296 bits · · FEATURES: · · · · · · · · · · · · Choose from among the following memory density options: IDT72V51546 IDT72V51546 Total Available Memory = 1,179,648 bits IDT72V51556 IDT72V51556 Total Available Memory = 2,359,296 bits Configurable from 1 to 32 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36 Independent Read and Write access per queue User programmable via serial port Default multi-queue device configurations ­ IDT72V51546 IDT72V51546 : 1,024 x 36 x 32Q ­ IDT72V51556 IDT72V51556 : 2,048 x 36 x 32Q 100% Bus Utilization, Read and Write on every clock cycle 166 MHz High speed operation (6ns cycle time) 3.7ns access time Individual, Active queue flags (OV, FF, PAE, PAF, PR) 8 bit parallel flag status on both read and write ports Shows PAE and PAF status of 8 Queues · · · · · · · · · Direct or polled operation of flag status bus Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width) User Selectable Bus Matching Options: ­ x36in to x36out ­ x18in to x36out ­ x9in to x36out ­ x36in to x18out ­ x36in to x9out FWFT mode of operation on read port Packet mode operation Partial Reset, clears data in single Queue Expansion of up to 8 multi-queue devices in parallel is available JTAG Functionality (Boundary Scan) Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm HIGH Performance submicron CMOS technology Industrial temperature range (-40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE FSTR WRADD 8 WEN WCLK Q0 RADEN READ CONTROL WRITE CONTROL WADEN Q1 ESTR RDADD 8 REN RCLK Q2 OE PAF PAFn 8 WRITE FLAGS FF x36 DATA OUT READ FLAGS x36 DATA IN Qout Din Q31 OV PR PAE 8 PAEn/PRn 5904 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JUNE 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5904/9 DSC-5904/9 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation provides the flag busses with all queues status. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES A packet mode of operation is also provided when the device is configured for 36 bit input and 36 bit output port sizes. The Packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 32, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. Both Master Reset and Partial Reset pins are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset. A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device. 2 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Din x9, x18, x36 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES D35 = TEOP D34 = TSOP D0 - D35 WCLK WEN TMS INPUT DEMUX JTAG Logic WRADD WADEN TDI TDO TCK 8 Write Control Logic TRST Write Pointers FSTR PAFn FSYNC 8 Packet Mode Logic PAF General Flag Monitor Upto 32 FIFO Queues FXO FXI FF PAF SI SO SCLK SENI 8 PRn/PAEn OV Active Q Flags 2.3 Mbit Dual Port Memory Active Q Flags PR PAE PAE General Flag Monitor Serial Multi-Queue Programming ESTR ESYNC EXI EXO SENO FM IW OW BM Read Pointers Reset Logic 8 Read Control Logic RDADD RADEN MAST REN PKT ID0 ID1 ID2 DF DFM RCLK Device ID 3 Bit OUTPUT MUX PAE/ PAF Offset 2 OUTPUT REGISTER PRS MRS Q35 = REOP Q34 = RSOP 5904 drw02 OE Q0 - Q35 Qout x9, x18, x36 Figure 1. Multi-Queue Flow-Control Device Block Diagram 3 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 D7 D4 D1 TCK TDO ID1 Q3 D15 D16 D11 D9 D6 D3 D0 TMS TDI ID0 Q2 D17 D18 D19 D8 D5 D2 TRST GND ID2 Q0 D20 D21 D22 VCC VCC VCC VCC VCC VCC D23 D24 D25 VCC VCC VCC VCC GND D26 D27 D28 VCC VCC GND GND D29 D30 D31 VCC VCC GND D32 D33 D34 VCC GND GND GND D35 VCC GND GND GND SI DFM SENO SENI Q6 Q9 Q12 Q14 Q15 Q5 Q8 Q11 Q13 Q19 Q1 Q4 Q7 Q10 Q17 Q18 VCC VCC VCC VCC Q16 Q21 Q20 GND VCC VCC VCC VCC Q24 Q23 Q22 GND GND GND GND VCC VCC Q27 Q26 Q25 GND GND GND GND GND VCC VCC Q30 Q29 Q28 GND GND GND GND GND GND GND VCC Q33 Q32 Q31 GND GND GND GND GND GND GND GND VCC PKT Q35 Q34 VCC VCC GND GND GND GND GND GND VCC VCC GND MAST FM DF VCC VCC GND GND GND GND GND GND VCC VCC BM SO VCC VCC VCC VCC GND GND VCC VCC VCC VCC OE SCLK VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RDADD2 RDADD3 RDADD4 WADEN PAF3 PAF6 PAF7 FF OV PAE PAE7 PAE6 PAE3 RDADD5 RDADD6 RDADD7 FSYNC FSTR PAF2 PAF5 PAF4 PAF PR DNC DNC PAE5 PAE2 RADEN ESTR ESYNC RCLK REN PAE4 PAE1 PAE0 EXO EXI 10 11 12 13 14 15 16 B C D E F G H J K L IW OW M RDADD0 RDADD1 N WRADD1 WRADD0 P WRADD4 WRADD3 WRADD2 R WRADD6 WRADD5 T WRADD7 FXI FXO PAF0 PAF1 WEN WCLK PRS MRS 1 2 3 4 5 6 7 8 9 5904 drw03 NOTE: 1. DNC - Do Not Connect. PBGA (BB256-1 BB256-1, order code: BB) TOP VIEW 4 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES respective queue is selected on the write port, the almost full flag provides status for that queue. Conversely, the read port has an output valid flag, providing status of the data being read from the queue selected on the read port. As well as the output valid flag the device provides a dedicated almost empty flag. This almost empty flag is similar to the almost empty flag of a conventional IDT FIFO. The device provides a user programmable almost empty flag for all 32 queues and when a respective queue is selected on the read port, the almost empty flag provides status for that queue. DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with up to 32 FIFO queues in parallel buffering between the two ports. The user can setup between 1 and 32 Queues within the device. These queues can be configured to utilize the total available memory, providing the user with full flexibility and ability to configure the queues to be various depths, independent of one another. PROGRAMMABLE FLAG BUSSES In addition to these dedicated flags, full & almost full on the write port and output valid & almost empty on the read port, there are two flag status busses. An almost full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag status bus is provided, again this bus is 8 bits wide. The purpose of these flag busses is to provide the user with a means by which to monitor the data levels within queues that may not be selected on the write or read port. As mentioned, the device provides almost full and almost empty registers (programmable by the user) for each of the 32 queues in the device. In the IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices the user has the option of utilizing anywhere between 1 and 32 queues, therefore the 8 bit flag status busses are multiplexed between the 32 queues, a flag bus can only provide status for 8 of the 32 queues at any moment, this is referred to as a "Quadrant", such that when the bus is providing status of queues 1 through 8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so on up to quadrant 4. If less than 32 queues are setup in the device, there are still 4 quadrants, such that in "Polled" mode of operation the flag bus will still cycle through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and 2 will reflect status of queues 1 through 8 and 9 through 16 respectively. Quadrant 3 will reflect the status of queues 17 through 22 on the least significant 6 bits, the most significant 2 bits of the flag bus are don't care and the 4th quadrant outputs will be don't care also. The flag busses are available in two user selectable modes of operation, "Polled" or "Direct". When operating in polled mode a flag bus provides status of each quadrant sequentially, that is, on each rising edge of a clock the flag bus is updated to show the status of each quadrant in order. The rising edge of the write clock will update the almost full bus and a rising edge on the read clock will update the almost empty bus. The mode of operation is always the same for both the almost full and almost empty flag busses. When operating in direct mode, the quadrant on the flag bus is selected by the user. So the user can actually address the quadrant to be placed on the flag status busses, these flag busses operate independently of one another. Addressing of the almost full flag bus is done via the write port and addressing of the almost empty flag bus is done via the read port. MEMORY ORGANIZATION/ ALLOCATION The memory is organized into what is known as "blocks", each block being 256 x36 bits. When the user is configuring the number of queues and individual queue sizes the user must allocate the memory to respective queues, in units of blocks, that is, a single queue can be made up from 0 to m blocks, where m is the total number of blocks available within a device. Also the total size of any given queue must be in increments of 256 x36. For the IDT72V51546 IDT72V51546 and IDT72V51556 IDT72V51556 the Total Available Memory is 128 and 256 blocks respectively (a block being 256 x36). Queues can be built from these blocks to make any size queue desired and any number of queues desired. BUS WIDTHS The input port is common to all queues within the device, as is the output port. The device provides the user with Bus Matching options such that the input port and output port can be either x9, x18 or x36 bits wide provided that at least one of the ports is x36 bits wide, the read and write port widths being set independently of one another. Because the ports are common to all queues the width of the queues is not individually set, so that the input width of all queues are equal and the output width of all queues are equal. WRITING TO & READING FROM THE MULTI-QUEUE Data being written into the device via the input port is directed to a discrete queue via the write queue select address inputs. Conversely, data being read from the device read port is read from a queue selected via the read queue select address inputs. Data can be simultaneously written into and read from the same queue or different queues. Once a queue is selected for data writes or reads, the writing and reading operation is performed in the same manner as a conventional IDT synchronous FIFO, utilizing clocks and enables, there is a single clock and enable per port. When a specific queue is addressed on the write port, data placed on the data inputs is written to that queue sequentially based on the rising edge of a write clock provided setup and hold times are met. Conversely, data is read on to the output port after an access time from a rising edge on a read clock. The operation of the write port is comparable to the function of a conventional FIFO operating in standard IDT mode. Write operations can be performed on the write port provided that the queue currently selected is not full, a full flag output provides status of the selected queue. The operation of the read port is comparable to the function of a conventional FIFO operating in FWFT mode. When a queue is selected on the output port, the next word in that queue will automatically fall through to the output register. All subsequent words from that queue require an enabled read cycle. Data cannot be read from a selected queue if that queue is empty, the read port provides an Output Valid flag indicating when data read out is valid. If the user switches to a queue that is empty, the last word from the previous queue will remain on the output register. As mentioned, the write port has a full flag, providing full status of the selected queue. Along with the full flag a dedicated almost full flag is provided, this almost full flag is similar to the almost full flag of a conventional IDT FIFO. The device provides a user programmable almost full flag for all 32 queues and when a PACKET MODE The multi-queue flow-control device also offers a "Packet Mode" operation. Packet Mode is user selectable and requires the device to be configured with both write and read ports as 36 bits wide. In packet mode, users can define the length of packets or frame by using the two most significant bits of the 36bit word. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to mark the End of Packet (EOP) as shown in Table 5). When writing data into a given queue, the first word being written is marked, by the user setting bit 34 as the "Start of Packet" (SOP) and the last word written is marked as the "End of Packet" (EOP) with all words written between the Start of Packet (SOP) marker (bit 34) and the End of packet (EOP) packet marker (bit 35) constituting the entire packet. A packet can be any length the user desires, up to the total available memory in the multi-queue flow-control device. The device monitors the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read 5 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits port is supplied with an additional status flag, "Packet Ready". The Packet Ready (PR) flag in conjunction with Output Valid (OV) indicates when at least one packet is available to read. When in packet mode the almost empty flag status, provides packet ready flag status for individual queues. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES memory blocks within a multi-queue device can be allocated to increase the depth of a queue. For example, depth expansion of 8 devices provides the possibility of 8 queues of 64K x36 deep, each queue being setup within a single device utilizing all memory blocks available to produce a single queue. This is the deepest queue that can setup within a device. For queue expansion a maximum number of 256 (8 x 32) queues may be setup, each queue being 2K x36 deep, if less queues are setup, then more memory blocks will be available to increase queue depths if desired. When connecting multi-queue devices in expansion mode all respective input pins (data & control) and output pins (data & flags), should be "connected" together between individual devices. EXPANSION Expansion of multi-queue devices is also possible, up to 8 devices can be connected in a parallel fashion providing the possibility of both depth expansion or queue expansion. Depth Expansion means expanding the depths of individual queues. Queue expansion means increasing the total number of queues available. Depth expansion is possible by virtue of the fact that more 6 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS Symbol & Pin No. BM (L14) Name Bus Matching I/O TYPE Description LVTTL INPUT This pin is setup before Master Reset and must not toggle during any device operation. This pin is used along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3 for details. D[35:0] Data Input Bus Din (See Pin No. table for details) LVTTL INPUT These are the 36 data input pins. Data is written into the device via these input pins on the rising edge of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 D32-D35 may be used as packet markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs may be used, any unused inputs should be tied LOW. DF(1) (L3) Default Flag LVTTL INPUT If the user requires default programming of the multi-queue device, this pin must be setup before Master Reset and must not toggle during any device operation. The state of this input at master reset determines the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128. DFM(1) (L2) Default Mode LVTTL INPUT The multi-queue device requires programming after master reset. The user can do this serially via the serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be selected, if HIGH then default mode is selected. ESTR (R15) PAEn Flag Bus Strobe LVTTL INPUT If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK and the RDADD bus to select a quadrant of queues to be placed on to the PAEn bus outputs. A quadrant addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed and SENO has gone LOW. ESYNC (R16) PAEn Bus Sync EXI (T16) PAEn Bus Expansion In EXO (T15) PAEn Bus Expansion Out LVTTL EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled OUTPUT PAEn bus operation has been selected . EXO of device `N' connects directly to EXI of device `N+1'. This pin pulses when device N has placed its final (4th) quadrant on to the PAEn bus with respect to RCLK. This pulse (token) is then passed on to the next device in the chain `N+1' and on the next RCLK rising edge the first quadrant of device N+1 will be loaded on to the PAEn bus. This continues through the chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device in the chain provides synchronization to the user of this looping event. FF (P8) Full Flag LVTTL OUTPUT This pin provides the full flag output for the active queue, that is, the queue selected on the input port for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue on the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common line. The device with a queue selected takes control of the FF bus, all other devices place their FF output into High-Impedance. When a queue selection is made on the write port this output will switch from High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK. FM(1) (K16) Flag Mode LVTTL INPUT This pin is setup before a master reset and must not toggle during any device operation. The state of the FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct. LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus OUTPUT during Polled operation of the PAEn bus. During Polled operation each quadrant of queue status flags is loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads quadrant 1 on to PAEn, the second RCLK rising edge loads quadrant 2 and so on. The fifth RCLK rising edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed on to the PAEn bus, the ESYNC output will be HIGH. For all other quadrants of that device, the ESYNC output will be LOW. LVTTL INPUT The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn bus operation has been selected. EXI of device `N' connects directly to EXO of device `N-1'. The EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI input must be connected to the EXO output of the same device. In expansion mode the EXI of the first device should be tied LOW, when direct mode is selected. 7 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Pin No. FSTR (R4) Name PAFn Flag Bus Strobe I/O TYPE LVTTL INPUT Description If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK and the WRADD bus to select a quadrant of queues to be placed on to the PAFn bus outputs. A quadrant addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed and SENO has gone LOW. FSYNC (R3) PAFn Bus Sync LVTTL FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads quadrant 1 on to PAFn, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC output will be LOW. FXI (T2) PAFn Bus Expansion In FXO (T3) PAFn Bus Expansion Out ID[2:0](1) (ID2-C9 ID1-A10 ID1-A10 ID0-B10 ID0-B10) Device ID Pins LVTTL INPUT For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue selection takes place the 3 MSb's of this 8 bit address bus are used to address the specific device (the 5 LSb's are used to address the queue within that device). During write/read operations the 3 MSb's of the address are compared to the device ID pins. The first device in a chain of multi-queue's (connected in expansion mode), may be setup as `000', the second as `001' and so on through to device 8 which is `111', however the ID does not have to match the device order. In single device mode these pins should be setup as `000' and the 3 MSb's of the WRADD and RDADD address busses should be tied LOW. The ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during any device operation. Note, the device selected as the `Master' does not have to have the ID of `000'. IW(1) (L15) Input Width LVTTL INPUT This pin is used in conjunction with OW and BM to setup the input and output bus widths to be a combination of x9, x18 or x36, (providing that one port is x36). MAST(1) (K15) Master Device LVTTL INPUT The state of this input at Master Reset determines whether a given device (within a chain of devices), is the Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The master device is the first to take control of all outputs after a master reset, all slave devices go to High-Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this pin must be set HIGH. MRS (T9) Master Reset LVTTL INPUT A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required after master reset. OE (M14) Output Enable LVTTL INPUT The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue data output bus, Qout. If a device has been configured as a "Master" device, the Qout data outputs will be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be in High Impedance. If a device is configured a "Slave" device, then the Qout data outputs will always be in High Impedance until that device has been selected on the Read Port, at which point OE provides threestate of that respective device. LVTTL INPUT The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn bus operation has been selected . FXI of device `N' connects directly to FXO of device `N-1'. The FXI receives a token from the previous device in a chain. In single device mode the FXI input must be tied LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input must be connected to the FXO output of the same device. In expansion mode the FXI of the first device should be tied LOW, when direct mode is selected. LVTTL FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled OUTPUT PAFn bus operation has been selected . FXO of device `N' connects directly to FXI of device `N+1'. This pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK. This pulse (token) is then passed on to the next device in the chain `N+1' and on the next WCLK rising edge the first quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the chain provides synchronization to the user of this looping event. 8 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Pin No. OV (P9) Name Output Valid Flag I/O TYPE Description LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control OUTPUT device data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV flag represents the data in that respective queue. When a selected queue on the read port is read to empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-Impedance capability, required when multiple devices are used and the OV flags are tied together. OW(1) (L16) Output Width PAE (P10) Programmable LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is synchronized to RCLK. LVTTL INPUT This pin is setup during Master Reset and must not toggle during any device operation. This pin is used in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9, x18 or x36, (providing that one port is x36). PAEn/PRn Programmable LVTTL On the 32Q device the PAEn/ PRn bus is 8 bits wide. During a Master Reset this bus is setup for either (See Pin No. Almost-Empty Flag OUTPUT Almost Empty mode or Packet mode. This output bus provides PAE/ PRn status of 8 queues (1 quadrant), table for details) Bus/Packet Ready within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs Flag Bus provide programmable empty flag status or packet ready status, in either direct or polled mode. The mode of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation the PAEn/PRn bus is updated to show the PAE/PR status of a quadrant of queues within a selected device. Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded with the PAE/ PRn status of multi-queue flow-control quadrants sequentially based on the rising edge of RCLK. PAE or PR operation is determined by the state of PKT during master reset. PAF (R8) Programmable Almost-Full Flag LVTTL This pin provides the Almost-Full flag status for the queue that has been selected on the input port for write OUTPUT operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized to WCLK. PAFn Programmable (See Pin No. Almost-Full Flag table for details) Bus LVTTL On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of OUTPUT 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs provide programmable full flag status, in either direct or polled mode. The mode of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation the PAFn bus is updated to show the PAF status of a quadrant of queues within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn bus is loaded with the PAF status of multi-queue flow-control quadrants sequentially based on the rising edge of WCLK. PKT(1) (J14) Packet Mode PR (R9) Packet Ready Flag LVTTL INPUT The state of this pin during a Master Reset will determine whether the part is operating in Packet mode providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output, or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional. If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected. Packet Ready utilizes user marked locations to identify start and end of packets being written into the device. Packet Mode can only be selected if both the input port width and output port width are 36 bits. LVTTL If packet mode has been selected this flag output provides Packet Ready status of the queue selected OUTPUT for read operations. During a master reset the state of the PKT input determines whether Packet mode of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP) markers, the multi-queue device sets PR LOW if one or more "complete" packets are available in the queue. A complete packet(s) must be written before the user is allowed to switch queues. 9 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Pin No. PRS (T8) Name Partial Reset Q[35:0] Data Output Bus Qout (See Pin No. table for details) I/O TYPE LVTTL INPUT Description A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial Reset can be performed on a queue, that queue must be selected on both the write port and read port 2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to the first memory location, none of the devices configuration will be changed. LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Note, that in Packet mode Q32-Q35 Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected. RADEN (R14) Read Address Enable LVTTL INPUT The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note, that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. RCLK (T10) Read Clock LVTTL INPUT When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the PAEn/PRn flag quadrant to be placed on the PAEn/PRn bus during direct flag operation. During polled flag operation the PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE, PR and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are based on RCLK. RCLK must be continuous and free-running. RDADD Read Address Bus [7:0] (RDADD7-P16 RDADD7-P16 RDADD6-P15 RDADD6-P15 RDADD5-P14 RDADD5-P14 RDADD4-N16 RDADD4-N16 RDADD3-N15 RDADD3-N15 RDADD2-N14 RDADD2-N14 RDADD1-M16 RDADD1-M16 RDADD0-M15 RDADD0-M15) LVTTL INPUT For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first function of RDADD is to select a queue to be read from. The least significant 5 bits of the bus, RDADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits, RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. These 3 MSB's will address a device with the matching ID code. The address present on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On the next rising RCLK edge after a read queue select, a data word from the previous queue will be placed onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue select, data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the first word fall through effect. The second function of the RDADD bus is to select the quadrant of queues to be loaded on to the PAEn/PRn bus during strobed flag mode. The least significant 2 bits, RDADD[1:0] are used to select the quadrant of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[4:2] are don't care during quadrant selection. The quadrant address present on the RDADD bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). Please refer to Table 2 for details on RDADD bus. REN (T11) Read Enable LVTTL INPUT The REN input enables read operations from a selected queue based on a rising edge of RCLK. A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not required to cycle the PAEn/PRn bus (in polled mode) or to select the PAEn quadrant , (in direct mode). SCLK (N3) Serial Clock LVTTL INPUT If serial programming of the multi-queue device has been selected during master reset, the SCLK input clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed the SCLK of all devices should be connected to the same source. SENI (M2) Serial Input Enable LVTTL INPUT During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are 10 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Pin No. SENI (Continued) (M2) Name I/O TYPE Description Serial Input Enable LVTTL INPUT SENO (M1) Serial Output Enable SI (L1) Serial In SO (M3) Serial Out TCK(2) (A8) JTAG Clock LVTTL INPUT Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needsto be tied to GND. TDI(2) (B9) JTAG Test Data Input LVTTL INPUT One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) (A9) JTAG Test Data Output TMS(2) (B8) JTAG Mode Select LVTTL INPUT TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) (C7) JTAG Reset LVTTL INPUT TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected. WADEN (P4) Write Address Enable LVTTL INPUT The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. WCLK (T7) Write Clock LVTTL INPUT When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus, Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag quadrant to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI input of the master device (or single device), should be controlled by the user. LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO wil also go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations. If multiple devices are cascaded and serial programming of the devices will be used, the SENO output should be connected to the SENI input of the next device in the chain. When serial programming of the first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and so on throughout the chain. When a given device in the chain is fully programmed the SENO output essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain. When this output goes LOW, serial loading of all devices has been completed. LVTTL INPUT During serial programming this pin is loaded with the serial data that will configure the multi-queue devices. Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers. LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the chain. The SO of the final device in a chain should not be connected. LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. 11 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Pin No. WCLK (Continued) (T7) WEN (T6) Name I/O TYPE Description Write Clock LVTTL INPUT bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based on WCLK. The WCLK must be continuous and free-running. Write Enable LVTTL INPUT The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in polled mode) or to select the PAFn quadrant , (in direct mode). LVTTL INPUT For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The first function of WRADD is to select a queue to be written to. The least significant 5 bits of the bus, WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. These 3 MSB's will address a device with the matching ID code. The address present on the WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data present on the Din bus can be written into the previously selected queue on this WCLK edge and on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select, data can be written into the newly selected queue. The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the PAFn bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits WRADD[4:2] are don't care during quadrant selection. The quadrant address present on the WRADD bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus. WRADD Write Address Bus [7:0] (WRADD7-T1 WRADD6-R1 WRADD5-R2 WRADD4-P1 WRADD3-P2 WRADD2-P3 WRADD1-N1 WRADD0-N2) VCC (See below) +3.3V Supply Power These are VCC power supply pins and must all be connected to a +3.3V supply rail. GND (See below) Ground Pin Ground These are Ground pins and must all be connected to the GND supply rail. NOTES: 1. Inputs should not change after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 53-57 and Figures 33-35. PIN NUMBER TABLE Symbol D[35:0] Din Name Data Input Bus I/O TYPE LVTTL INPUT Pin Number D35-J3 D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1), D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3 D11-B3, D10-A4 D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7 PAEn/PRn Programmable AlmostEmpty Flag Bus/Packet Ready Flag Bus LVTTL PAE7-P11 PAE7-P11, PAE6-P12 PAE6-P12, PAE5-R12 PAE5-R12, PAE4-T12 PAE4-T12, PAE3-P13 PAE3-P13, PAE2-R13 PAE2-R13, PAE1-T13 PAE1-T13, PAE0-T14 PAE0-T14 OUTPUT PAFn Programmable AlmostFull Flag Bus LVTTL PAF7-P7, PAF6-P6, PAF5-R6, PAF4-R7, PAF3-P5, PAF2-R5, PAF1-T5, PAF0-T4 OUTPUT Q[35:0] Qout Data Output Bus LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16), OUTPUT Q(21,20)-D(15,16), Q19-B16 Q19-B16, Q(18,17)-C(16,15), Q16-D14 Q16-D14, Q(15,14)-A(16,15), Q13-B15 Q13-B15, Q12-A14 Q12-A14, Q11-B14 Q11-B14, Q10-C14 Q10-C14, Q9-A13 Q9-A13, Q8-B13 Q8-B13, Q7-C13 Q7-C13, Q6-A12 Q6-A12, Q5-B12 Q5-B12, Q4-C12 Q4-C12, Q3-A11 Q3-A11, Q2-B11 Q2-B11, Q(1,0)-C(11,10) VCC +3.3V Supply Power D(4-13), E(4-7,10-13), F(4,5,12,13), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(4,5,12,13), M(4-7,10-13), N(4-13) GND Ground Pin Ground C8, E(8-9), F(6-11), G(6-11), H(5-12), J(1,2,5-12), K(1-3,14,6-11), L(6-11), M(8-9) DNC Do Not Connect R(10,11) 12 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol VTERM Rating Terminal Voltage with respect to GND Com'l & Ind'l ­0.5 to +4.5 TSTG Storage Temperature ­55 to +125 DC Output Current ­50 to +50 RECOMMENDED DC OPERATING CONDITIONS °C IOUT COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Unit V mA Symbol VCC(1) GND Parameter Supply Voltage (Com'l/Ind'l) Min. Typ. Max. Unit 3.15 3.3 3.45 V 0 0 V Input High Voltage (Com'l/Ind'l) 2.0 - VCC+0.3 V VIL Input Low Voltage (Com'l/Ind'l) - - 0.8 V TA Operating Temperature Commercial 0 - +70 °C TA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 0 VIH Supply Voltage (Com'l/Ind'l) Operating Temperature Industrial -40 - +85 °C NOTE: 1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant) Symbol ILI(1) ILO(2) VOH VOL ICC1(3,4,5) ICC2(3,6) Parameter Min. Unit ­10 ­10 2.4 - - - Input Leakage Current Output Leakage Current Output Logic "1" Voltage, IOH = ­8 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Standby Current Max. 10 10 - 0.4 100 25 µA µA V V mA mA NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). 4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 5. Typical ICC1 = 16 + 3.14*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 6. RCLK and WCLK, toggle at 20 MHz. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, RADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs. The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST. All other inputs are don't care, and should be pulled HIGH or LOW. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit (2) CIN Input Capacitance VIN = 0V 10 pF COUT(1,2) Output Capacitance VOUT = 0V 10 pF NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested. 13 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS 6 tCD (Typical, ns) 5 VCC/2 50 3 2 1 Z0 = 50 I/O 4 20 30 50 5904 drw04 80 100 Capacitance (pF) 200 5904 drw04a Figure 2b. Lumped Capacitive Load, Typical Derating Figure 2a. AC Test Load AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 2a & 2b OUTPUT ENABLE & DISABLE TIMING Output Enable Output Disable VIH OE VIL tOE & tOLZ Output Normally LOW Output Normally HIGH tOHZ VCC/2 VCC/2 100mV 100mV VOL VOH 100mV 100mV VCC/2 VCC/2 5904 drw04b 14 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tPRSS tPRSH tOLZ (OE-Qn)(2) tOHZ(2) tOE fC tSCLK tSCKH tSCKL tSDS tSDH tSENS tSENH tSDO tSENO tSDOP tSENOP tPCWQ tPCRQ tAS tAH tWFF tROV tSTS tSTH tQS tQH tWAF tRAE tPAF tPAE Commercial IDT72V51546L6 IDT72V51546L6 IDT72V51556L6 IDT72V51556L6 Min. Max. Clock Cycle Frequency (WCLK & RCLK) Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time Reset Recovery Time Partial Reset Setup Partial Reset Hold Output Enable to Output in Low-Impedance Output Enable to Output in High-Impedance Output Enable to Data Output Valid Clock Cycle Frequency (SCLK) Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data In Setup Serial Data In Hold Serial Enable Setup Serial Enable Hold SCLK to Serial Data Out SCLK to Serial Enable Out Serial Data Out Propagation Delay Serial Enable Propagation Delay Programming Complete to Write Queue Selection Programming Complete to Read Queue Selection Address Setup Address Hold Write Clock to Full Flag Read Clock to Output Valid Strobe Setup Strobe Hold Queue Setup Queue Hold WCLK to PAF flag RCLK to PAE flag Write Clock to Synchronous Almost-Full Flag Bus Read Clock to Synchronous Almost-Empty Flag Bus Unit - 0.6 6 2.7 2.7 2 0.5 2 0.5 10 15 10 2.0 0.5 0.6 0.6 0.6 - 100 45 45 20 1.2 20 1.2 - - 1.5 1.5 20 20 2.5 1 - - 2 0.5 2 0.5 0.6 0.6 0.6 0.6 Parameter Com'l & Ind'l(1) IDT72V51546L7-5 IDT72V51546L7-5 IDT72V51556L7-5 IDT72V51556L7-5 Min. Max. - 0.6 7.5 3.5 3.5 2.0 0.5 2.0 0.5 10 15 10 2.5 0.5 0.6 0.6 0.6 - 100 45 45 20 1.2 20 1.2 - - 1.5 1.5 20 20 3.0 1 - - 2 0.5 2.5 0.5 0.6 0.6 0.6 0.6 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 166 3.7 - - - - - - - - - - - - 3.7 3.7 3.7 10 - - - - - - - 20 20 3.7 3.7 - - - - 3.7 3.7 - - - - 3.7 3.7 3.7 3.7 NOTES: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested. 15 133 4 - - - - - - - - - - - - 4 4 4 10 - - - - - - - 20 20 4 4 - - - 5 5 - - - - 4 4 4 4 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant) Symbol tPAELZ(2) tPAEHZ(2) tPAFLZ(2) tPAFHZ(2) tFFHZ(2) tFFLZ(2) tOVLZ(2) tOVHZ(2) tFSYNC tFXO tESYNC tEXO tPR tSKEW1 tSKEW2 tSKEW3 . tSKEW4 tSKEW5 tXIS tXIH Commercial IDT72V51546L6 IDT72V51546L6 IDT72V51556L6 IDT72V51556L6 Min. Max. Parameter RCLK to PAE Flag Bus to Low-Impedance RCLK to PAE Flag Bus to High-Impedance WCLK to PAF Flag Bus to Low-Impedance WCLK to PAF Flag Bus to High-Impedance WCLK to Full Flag to High-Impedance WCLK to Full Flag to Low-Impedance RCLK to Output Valid Flag to Low-Impedance RCLK to Output Valid Flag to High-Impedance WCLK to PAF Bus Sync to Output WCLK to PAF Bus Expansion to Output RCLK to PAE Bus Sync to Output RCLK to PAE Bus Expansion to Output RCLK to Packet Ready Flag SKEW time between RCLK and WCLK for FF and OV SKEW time between RCLK and WCLK for PAF and PAE SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7] SKEW time between RCLK and WCLK for PR and OV SKEW time between RCLK and WCLK for OV when in Packet Mode Expansion Input Setup Expansion Input Hold Com'l & Ind'l(1) IDT72V51546L7-5 IDT72V51546L7-5 IDT72V51556L7-5 IDT72V51556L7-5 Min. Max. 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 4.5 6 6 6 10 1.0 0.5 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 5.75 7.5 7.5 7.5 12 1.3 0.5 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 - - - - - - - NOTES: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested. 16 4 4 4 4 4 4 4 4 4 4 4 4 4 - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits FUNCTIONAL DESCRIPTION MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset all internal multi-queue device setup and control registers are initialized and require programming either serially by the user via the serial port, or using the default settings. During a master reset the state of the following inputs determine the functionality of the part, these pins should be held HIGH or LOW. PKT ­ Packet Mode FM ­ Flag bus Mode IW, OW, BM ­ Bus Matching options MAST ­ Master Device ID0, 1, 2 ­ Device ID DFM ­ Programming mode, serial or default DF ­ Offset value for PAE and PAF Once a master reset has taken place, the device must be programmed either serially or via the default method before any read/write operations can begin. See Figure 4, Master Reset for relevant timing. PARTIAL RESET A Partial Reset is a means by which the user can reset both the read and write pointers of a single queue that has been setup within a multi-queue device. Before a partial reset can take place on a queue, the respective queue must be selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK cycles before the PRS goes LOW. The partial reset is then performed by toggling the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can occur. A Partial Reset only resets the read and write pointers of a given queue, a partial reset will not effect the overall configuration and setup of the multi-queue device and its queues. See Figure 5, Partial Reset for relevant timing. SERIAL PROGRAMMING The multi-queue flow-control device is a fully programmable device, providing the user with flexibility in how queues are configured in terms of the number of queues, depth of each queue and position of the PAF/PAE flags within respective queues. All user programming is done via the serial port after a master reset has taken place. Internally the multi-queue device has setup registers which must be serially loaded, these registers contain values for every queue within the device, such as the depth and PAE/PAF offset values. The IDT72V51546/72V51556 IDT72V51546/72V51556 devices are capable of up to 32 queues and therefore contain 32 sets of registers for the setup of each queue. During a Master Reset if the DFM (Default Mode) input is LOW, then the device will require serial programming by the user. It is recommended that the user utilize a `C' program provided by IDT, this program will prompt the user for all information regarding the multi-queue setup. The program will then generate a serial bit stream which should be serially loaded into the device via the serial port. For the IDT72V51546/72V51556 IDT72V51546/72V51556 devices the serial programming requires a total number of serially loaded bits per device, (SCLK cycles with SENI enabled), calculated by: 19+(Qx72) where Q is the number of queues the user wishes to setup within the device. Please refer to the separate Application Note, AN-303 AN-303 for recommended control of the serial programming port. Once the master reset is complete and MRS is HIGH, the device can be serially loaded. Data present on the SI (serial in), input is loaded into the serial port on a rising edge of SCLK (serial clock), provided that SENI (serial in 17 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES enable), is LOW. Once serial programming of the device has been successfully completed the device will indicate this via the SENO (serial output enable) going active, LOW. Upon detection of completion of programming, the user should cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI once programming of a device is complete. Therefore, SENO will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also go HIGH. The operation of the SO output is similar, when programming of a given device is complete, the SO output will follow the SI input. If devices are being used in expansion mode the serial ports of devices should be cascaded. The user can load all devices via the serial input port control pins, SI & SENI, of the first device in the chain. Again, the user may utilize the `C' program to generate the serial bit stream, the program prompting the user for the number of devices to be programmed. The SENO and SO (serial out) of the first device should be connected to the SENI and SI inputs of the second device respectively and so on, with the SENO & SO outputs connecting to the SENI & SI inputs of all devices through the chain. All devices in the chain should be connected to a common SCLK. The serial output port of the final device should be monitored by the user. When SENO of the final device goes LOW, this indicates that serial programming of all devices has been successfully completed. Upon detection of completion of programming, the user should cease all programming and take SENI of the first device in the chain inactive, HIGH. As mentioned, the first device in the chain has its serial input port controlled by the user, this is the first device to have its internal registers serially loaded by the serial bit stream. When programming of this device is complete it will take its SENO output LOW and bypass the serial data loaded on the SI input to its SO output. The serial input of the second device in the chain is now loaded with the data from the SO of the first device, while the second device has its SENI input LOW. This process continues through the chain until all devices are programmed and the SENO of the final device goes LOW. Once all serial programming has been successfully completed, normal operations, (queue selections on the read and write ports) may begin. When connected in expansion mode, the IDT72V51546/72V51556 IDT72V51546/72V51556 devices require a total number of serially loaded bits per device to complete serial programming, (SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)] where Q is the number of queues the user wishes to setup within the device, where n is the number of devices in the chain. See Figure 6, Serial Port Connection and Figure 7, Serial Programming for connection and timing information. DEFAULT PROGRAMMING During a Master Reset if the DFM (Default Mode) input is HIGH the multiqueue device will be configured for default programming, (serial programming is not permitted). Default programming provides the user with a simpler, however limited means by which to setup the multi-queue flow-control device, rather than using the serial programming method. The default mode will configure a multi-queue device such that the maximum number of queues possible are setup, with all of the parts available memory blocks being allocated equally between the queues. The values of the PAE/PAF offsets is determined by the state of the DF (default) pin during a master reset. For the IDT72V51546/72V51556 IDT72V51546/72V51556 devices the default mode will setup 32 queues, each queue being 1024 x36 and 2048 x36 deep respectively. For both devices the value of the PAE/PAF offsets is determined at master reset by the state of the DF input. If DF is LOW then both the PAE & PAF offset will be 8, if HIGH then the value is 128. When configuring the IDT72V51546/72V51556 IDT72V51546/72V51556 devices in default mode the user simply has to apply WCLK cycles after a master reset, until SENO goes LOW, this signals that default programming is complete. These clock cycles are required for the device to load its internal setup registers. When a single multi- IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES queue selection. The queue selection is requires 2 WCLK cycles. All subsequent data writes will be to this queue until another queue is selected. Standard mode operation is defined as individual words will be written to the device as opposed to Packet Mode where complete packets may be written. The write port is designed such that 100% bus utilization can be obtained. This means that data can be written into the device on every WCLK rising edge including the cycle that a new queue is being addressed. Changing queues requires a minimum of 2 WCLK cycles on the write port (see Figure 9, Write Queue Select, Write Operation and Full flag Operation). WADEN goes high signaling a change of queue (clock cycle "A"). The address on WRADD at that time determines the next queue. Data presented during that cycle ("A") and the next cycle ("B"), will be written to the active (old) queue, provided WEN is active LOW. If WEN is HIGH (inactive) for these two clock cycles, data will not be written in to the previous queue. The write port discrete full flag will update to show the full status of the newly selected queue (QX) at this last cycle's rising edge ("B"). Data present on the data input bus (Din), can be written into the newly selected queue (QX) on the rising edge of WCLK on the second cycle ("C") following a change of queue, provided WEN is LOW and the new queue is not full. If the newly selected queue is full at the point of its selection, any writes to that queue will be prevented. Data cannot be written into a full queue. Refer to Figure 9, Write Queue Select, Write Operation and Full flag Operation, Figure 10, Write Operations & First Word Fall Through for timing diagrams and Figure 11, Full Flag Timing in Expansion Mode for timing diagrams. queue device is used, the completion of device programming is signaled by the SENO output of a device going from HIGH to LOW. Note, that SENI must be held LOW when a device is setup for default programming mode. When multi-queue devices are connected in expansion mode, the SENI of the first device in a chain can be held LOW. The SENO of a device should connect to the SENI of the next device in the chain. The SENO of the final device is used to indicate that default programming of all devices is complete. When the final SENO goes LOW normal operations may begin. Again, all devices will be programmed with their maximum number of queues and the memory divided equally between them. Please refer to Figure 8, Default Programming. READING AND WRITING TO THE IDT MULTI-QUEUE FLOW CONTROL MANAGER The IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices can be configured in two distinct modes, namely Standard Mode and Packet Mode. STANDARD MODE OPERATION (PKT = LOW on Master Reset) WRITE QUEUE SELECTION AND WRITE OPERATION (STANDARD MODE) The IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues into which data can be written via a common write port using the data inputs (Din), write clock (WCLK) and write enable (WEN). The queue to be written is selected by the address present on the write address bus (WRADD) during a rising edge on WCLK while write address enable (WADEN) is HIGH. The state of WEN does not impact the TABLE 1 - WRITE ADDRESS BUS, WRADD[7:0] Operation WCLK WADEN Write Queue Select 1 PAFn Quadrant Select FSTR 0 0 WRADD[7:0] 7 6 5 4 3 2 1 0 Device Select Write Queue Address (Compared to (5 bits = 32 Queues) ID0,1,2) 1 Quadrant Address 00 01 10 11 7 6 5 Device Select (Compared to ID0,1,2) 4 3 2 X X X 1 0 Quadrant Address Queue Status on PAFn Bus Q0 : Q7 PAF0 : PAF7 Q8 : Q15 PAF0 : PAF7 Q16 : Q23 PAF0 : PAF7 Q24 : Q31 PAF0 : PAF7 5904 drw05 18 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES queue (QF). The internal pipeline is also loaded at this time ("D") with the last word from the previous (old) queue (QP) as well as the next word from the new queue (QF). Both of these words will fall through to the output register( provided the OE is asserted) consecutively (cycles "E" and "F" respectively) following the selection of the new queue regardless of the state of REN, unless the new queue (QF) is empty. If the newly selected queue is empty, any reads from that queue will be prevented. Data cannot be read from an empty queue. The last word in the data output register (from the previous queue), will remain on the data bus, but the output valid flag, OV will go HIGH, to indicate that the data present is no longer valid. This pipelining effect provides the user with 100% bus utilization, and brings about the possibility that a "NULL" queue may be required within a multi-queue device. Null queue operation is discussed in the next section. Remember that OE allows the user to place the data output bus (Qout) into High-Impedance and the data can be read in to the output register regardless of OE. Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures 12, 14, and 15 for read queue selection and read port operation timing diagrams. READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues which data can be read via a common read port using the data outputs (Qout), read clock (RCLK) and read enable (REN). An output enable, OE control pin is also provided to allow HighImpedance selection of the Qout data outputs. The multi-queue device read port operates in a mode similar to "First Word Fall Through" on a SuperSync IDT FIFO, but with the added feature of data output pipelining (see Figure 10, Write Operations & First Word Fall Through). The queue to be read is selected by the address presented on the read address bus (RDADD) during a rising edge on RCLK while read address enable (RADEN) is HIGH. The state of REN does not impact the queue selection. The queue selection is requires 2 RCLK cycles. All subsequent data reads will be from this queue until another queue is selected. Standard mode operation is defined as individual words will be read from the device as opposed to Packet Mode where complete packets may be read. The read port is designed such that 100% bus utilization can be obtained. This means that data can be read out of the device on every RCLK rising edge including the cycle that a new queue is being addressed. Changing queues requires a minimum of two RCLK cycles on the read port (see Figure 12, Read Queue Select, Read Operation). RADEN goes high signaling a change of queue (clock cycle "D"). The address on RDADD at that time determines the next queue. Data presented during that cycle ("D") will be read at "D" (+ tA), can be read from the active (old) queue (QP), provided REN is active LOW. If REN is HIGH (inactive) for this clock cycle, data will not be read from the previous queue. The next cycle's rising edge ("E"), the read port discrete empty flag will update to show the empty status of the newly selected PACKET MODE OPERATION (PKT = HIGH on Master Reset) The Packet mode operation provides the capability where, user defined packets or frames can be written to the device as opposed to Standard mode where individual words are written. For clarification, in Packet Mode, a packet can be written to the device with the starting location designated as Transmit Start of Packet (TSOP) and the ending location designated as Transmit End of Packet (TEOP). In conjunction, a packet read from the device will be designated as Receive Start of Packet (RSOP) and a Receive End of Packet TABLE 2 - READ ADDRESS BUS, RDADD[7:0] Operation RCLK RADEN ESTR Read Queue Select 1 0 PAEn/PRn Quadrant Select 0 RDADD[7:0] 7 6 5 4 3 2 1 0 Device Select Read Queue Address (Compared to (5 bits = 32 Queues) ID0,1,2) 1 Quadrant Address 00 01 10 11 7 6 5 Device Select (Compared to ID0,1,2) 4 3 2 X X X 1 0 Quadrant Address Queue Status on PAEn/PRn Bus Q0 : Q7 PAE0 : PAE7 Q8 : Q15 PAE0 : PAE7 Q16 : Q23 PAE0 : PAE7 Q24 : Q31 PAE0 : PAE7 5904 drw06 19 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits (REOP). The minimum size for a packet is four words (SOP, two words of data and EOP). The almost empty flag bus becomes the "Packet Ready" PR flag bus when the device is configured for packet mode. Valid packets are indicated when both PR and OV are asserted. WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE) It is required that a full packet be written to a queue before moving to a different queue. The device requires two cycles to change queues. Packet mode, has 2 restrictions: An extra word (or filler word) is required to be written after each packet on the cycle following the queue change to ensure the RSOP in the old queue is not read out on a queue change because of the first word fall through. No SOP/EOP is allowed to read/written at cycle ("C" or "I") the next cycle after a queue change. For clock frequency (fs) of 133MHz and below see Application Note AN-398 AN-398. In this mode, the write port may not obtain 100% bus utilization. Changing queues requires a minimum of two WCLK cycles on the write port (see Figure 16, Writing in Packet Mode during a Queue Change). WADEN goes high signaling a change of queue (clock cycle "B" or "H"). The address on WRADD at the rising edge of WCLK determines the next queue. Data presented on Din during that cycle ("B" or "H") can continue to be written to the active (old) queue (QA or QB respectively), provided WEN is LOW (active). If WEN is HIGH (inactive) for this clock cycle (H), data will not be written in to the previous queue (QB). The cycle following a request for queue change ("C" or "I") will require a filler word to be written to the device. This can be done by clocking the TEOP twice or by writing a filler word. In packet mode, the multiqueue is designed under the 2 restrictions listed previously. Note, an erroneous Packet Ready flag may occur if the EOP or SOP marker shows up at the next cycle after a queue change. To prevent an erroneous Packet Ready flag from occurring a filler word should be written into the old queue at the last clock cycle of writing. It is important to know that no SOP or EOP may be written into the device during this cycle ("C" or "I"). The write port discrete full flag will update to show the full status of the newly selected queue (QB) at this last cycle's rising edge ("C" or "I"). Data values presented on the data input bus (Din), can be written into the newly selected queue (QX) on the rising edge of WCLK on the second cycle ("D" or "J") following a request for change of queue, provided WEN is LOW (active) and the new queue is not full. If a selected queue is full (FF is LOW), then writes to that queue will be prevented. Note, data cannot be written into a full queue. Refer to Figure 16, Writing in Packet Mode during a Queue Change and Figure 18, Data Input (Transit) packet mode of Operation for timing diagrams. READ QUEUE SELECTION AND READ OPERATION (PACKET MODE) In packet Mode it is required that a full packet is read from a queue before moving to a different queue. The device requires two cycles to change queues. In Packet Mode, there are 2 restrictions An extra word (or filler word) should have been inserted into the data stream after each packet to insure the RSOP in the old queue is not read out on a queue change because of the first word fall through and this word should be discarded. No EOP/SOP is allowed to be read/written at cycle ("C" or "I") the next cycle after a queue change). For clock frequency of 133Mhz and below see Application Note AN398 AN398. In this mode, the read port may not obtain 100% bus utilization. Changing queues requires a minimum of two RCLK cycles on the read port (see Figure 17, Reading in Packet Mode during a Queue Change). RADEN goes high signaling a change of queue (clock cycle "B" or "I"). The address on RDADD at the rising edge of RCLK determines the queue. As illustrated in Figure 17 during cycle ("B"), data can be read from the active (old) queue (QA), provided both REN and OE are LOW (active) simultaneously with changing queues. REOP for packet located in queue (QA) must be read before COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES a queue change request is made ("B"). If REN is HIGH (inactive) for this clock cycle ("I"), data will not be read from the previous queue (QB). In applications where the multi-queue flow-control device is connected to a shared bus, an output enable, OE control pin is also provided to allow High-Impedance selection of the data outputs (Qout). With reference to Figure 17 when changing queues, a packet marker (SOP or EOP) should not be read on cycle ("C" or "I"). Reading a SOP or EOP should not occur during the cycles required for a queue change. It is also recommended that a queue change should not occur once the reading of the packet has commenced. The EOP marker of the packet prior to a queue change should be read on or before the queue change. If the EOP word is read before a queue change, REN can be pulled high to disable further reads. When the queue change is initiated, the filler word written into the current queue after the EOP word will fall through followed by and the first word from the new queue. Refer to Figure 17, Reading in Packet Mode during a Queue Change as well as Figures 12, 14, and 15 for timing diagrams and Table 2, for Read Address bus arrangement. Note, the almost empty flag bus becomes the "Packet Ready" flag bus when the device is configured for packet mode. PACKET READY FLAG The multi-queue flow-control device provides the user with a Packet Ready feature. During a Master Reset the logic "1" (HIGH) on the PKT input signal (packet mode select), configures the device in packet mode. The PR discrete flag, provides a packet ready status of the active queue selected on the read port. A packet ready status is individually maintained on all queues; however only the queue selected on the read port has its packet ready status indicated on the PR output flag. A packet is available on the output for reading when both PR and OV are asserted LOW. If less than a full packet is available, the PR flag will be HIGH (packet not ready). In packet mode, no words can be read from a queue until a complete packet has been written into that queue, regardless of REN. When packet mode is selected the Programmable Almost Empty bus, PAEn, becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM = LOW during a master reset), the PRn bus provides packet ready status in 8 queue increments. The PRn bus supports either Polled or Direct modes of operation. The PRn mode of operation is configured through the Flag Mode (FM) bit during a Master Reset. When the multi-queue is configured for packet mode operation, the device must also be configured for 36 bit write data bus and 36 bit read data bus. The two most significant bits of the 36-bit data bus are used as "packet markers". On the write port these are bits D34 (Transmit Start of Packet,) D35 (Transmit End of Packet) and on the read port Q34, Q35. All four bits are monitored by the packet control logic as data is written into and read out from the queues. The packet ready status for individual queues is then determined by the packet ready logic. On the write port D34 is used to "mark" the first word being written into the selected queue as the "Transmit Start of Packet", TSOP. To further clarify, when the user requires a word being written to be marked as the start of a packet, the TSOP input (D34) must be HIGH for the same WCLK rising edge as the word that is written. The TSOP marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port. On the write port D35 is used to "mark" the last word of the packet currently being written into the selected queue as the "Transmit End of Packet" TEOP. When the user requires a word being written to be marked as the end of a packet, the TEOP input must be HIGH for the same WCLK rising edge as the word that is written in. The TEOP marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port. 20 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES BYTE D TMOD1 (D33) RMOD1 (Q33) 0 0 1 1 BYTE C TMOD2 (D32) RMOD2 (Q32) 0 1 0 1 D0/Q0 D7/Q7 D15/Q15 D15/Q15 D23/Q23 D23/Q23 D31/Q31 D31/Q31 MOD 2 D32/Q32 D32/Q32 D34/Q34 D34/Q34 SOP MOD 1 D33/Q33 D33/Q33 D35/Q35 D35/Q35 EOP TABLE 5 - PACKET MODE VALID BYTE BYTE B BYTE A VALID BYTES A, B, C, D A A, B A, B, C 5904 drw07 NOTE: Packet Mode is only available when the Input Port and Output Port are 36 bits wide. The packet ready logic monitors all start and end of packet markers both as they enter respective queues via the write port and as they exit queues via the read port. The multi-queue internal logic increments and decrements a packet counter, which is provided for each queue. The functionality of the packet ready logic provides status as to whether at least one full packet of data is available within the selected queue. A partial packet in a queue is regarded as a packet not ready and PR (active LOW) will be HIGH. In Packet mode, no words can be read from a queue until at least one complete packet has been written into the queue, regardless of REN. For example, if a TSOP has been written and some number of words later a TEOP is written a full packet of data is deemed to be available, and the PR flag and OV will go active LOW. Consequently if reads begin from a queue that has only one complete packet and the RSOP is detected on the output port as data is being read out, PR will go inactive HIGH. OV will remain LOW indicating there is still valid data being read out of that queue until the REOP is read. The user may proceed with the reading operation until the current packet has been read out and no further complete packets are available. If during that time another complete packet has been written into the queue and the PR flag will again gone active, then reads from the new packet may follow after the current packet has been completely read out. The packet counters therefore look for start of packet markers followed by end of packet markers and regard data in between the TSOP and TEOP as a full packet of data. The packet monitoring has no limitation as to how many packets are written into a queue, the only constraint is the depth of the queue. Note, there is a minimum allowable packet size of four words, inclusive of the TSOP marker and TEOP marker. The packet logic does expect a TSOP marker to be followed by a TEOP marker. If a second TSOP marker is written after a first, it is ignored and the logic regards data between the first TSOP and the first subsequent TEOP as the full packet. The same is true for TEOP; a second consecutive TEOP mark is ignored. On the read side the user should regard a packet as being between the first RSOP and the first subsequent REOP and disregard consecutive RSOP markers and/or REOP markers. This is why a TEOP may be written twice, using the second TEOP as the filler word. As an example, the user may also wish to implement the use of an "Almost End of Packet"(AEOP) marker. For example, the AEOP can be assigned to data input bit D33. The purpose of this AEOP marker is to provide an indicator that the end of packet is a fixed (known) number of reads away from the end of packet. This is a useful feature when due to latencies within the system, monitoring the REOP marker alone does not prevent "over reading" of the data from the queue selected. For example, an AEOP marker set 4 writes before the TEOP marker provides the device connected to the read port with and "almost end of packet" indication 4 cycles before the end of packet. The AEOP can be set any number of words before the end of packet determined by user requirements or latencies involved in the system. See Figure 17, Reading in Packet Mode during a Queue Change, Figure 18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data Output (Receive) Packet Mode of Operation. PACKET MODE ­ MODULO OPERATION The internal packet ready control logic performs no operation on these modulo bits, they are only informational bits that are passed through with the respective data byte(s). When utilizing the multi-queue flow-control device in packet mode, the user may also want to consider the implementation of "Modulo" operation or "valid byte marking". Modulo operation may be useful when the packets being transferred through a queue are in a specific byte arrangement even though the data bus width is 36 bits. In Modulo operation the user can concatenate bytes to form a specific data string through the multi-queue device. A possible scenario is where a limited number of bytes are extracted from the packet for either analysis or filtered for security protection. This will only occur when the first 36 bit word of a packet is written in and the last 36 bit word of packet is written in. The modulo operation is a means by which the user can mark and identify specific data within the Queue. On the write port data input bits, D32 (transmit modulo bit 2, TMOD2) and D33 (transmit modulo bit 1, TMOD1) can be used as data markers. An example of this could be to use D32 and D33 to code which bytes of a word are part of the packet that is also being marked as the "Start of Marker" or "End of Marker". Conversely on the read port when reading out these marked words, data outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo bit 1, RMOD1) will pass on the byte validity information for that word. Refer to Table 5 for one example of how the modulo bits may be setup and used. See Figure 18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data Output (Receive) Packet Mode of Operation. 21 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard mode. Data can be read out of the multi-queue flow-control device on every RCLK cycle regardless of queue switches or other operations. The device architecture is such that the pipeline is constantly filled with the next words in a selected queue to be read out, again providing 100% bus utilization. This type of architecture does assume that the user is constantly switching queues such that during a queue switch, the last data word required from the previous queue will fall through the pipeline to the output. Note, that if reads cease at the empty boundary of a queue, then the last word will automatically flow through the pipeline to the output. Null Q operation requires that a user only uses 31 queues in the 32 multiqueue flow-control device, the 32nd queue address (xxx 11111) of the device now is assigned as the null queue. (Note, any unused queue can be assigned as the Null queue). During device programming the user should simply program between 1 and 31 queues, the 32nd queue will automatically default to a null queue. (Note, that in expansion mode a user may want to assign a null queue in each device). Note, this option requires that the user must select serial programming and configure the device to be 31 queues, (or less). The default mode of device programming should not be selected, (default mode automatically sets up 32 queues, with the memory equally divided between queues). If Default mode is selected and the user wishes to assign one queue as the "Null-Q", extra care must be taken so as not to write data to the "NullQ", this is very important. A null queue can be selected when no further reads are required from a previously selected queue. Changing to a null queue will continue to propagate data in the pipeline to the previous queue's output. The Null Q can remain selected until a data becomes available in another queue for reading. The NullQ can be utilized in either standard or packet mode. Note: If the user switches the read port to the null queue, this queue is seen as and treated as an empty queue, therefore after switching to the null queue the last word from the previous queue will remain in the output register and the OV flag will go HIGH, indicating data is not valid. The Null queue operation only has significance to the read port of the multiqueue, it is a means to force data through the pipeline to the output. Null Q selection and operation has no meaning on the write port of the device. Also, refer to Figure 20, Read Operation and Null Queue Select for diagram. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (MSbs) are used when a device is connected in expansion mode with up to 8 devices connected in width expansion, each device having its own 3-bit address. When logically expanded with multiple parts, each device is statically setup with a unique chip ID code on the ID pins, ID0, ID1, and ID2. A device is selected when the 3 Most Significant bits of the WRADD address bus matches a 3-bit ID code. The maximum logical expansion is 256 queues (32 queues x 8 devices) or a minimum of 8 queues (1 queue per device x 8 devices), each of the maximum size of the individual memory device. Note: The WRADD bus is also used in conjunction with FSTR (almost full flag bus strobe), to address the almost full flag bus during direct mode of operation. Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure 11, Full Flag Timing Expansion Mode, Figure 13, Output Valid Flag Timing (In Expansion Mode), and Figure 32, Multi-Queue Expansion Diagram, for timing diagrams. BUS MATCHING OPERATION Bus Matching operation between the input port and output port is available. During a master reset of the multi-queue the state of the three setup pins, BM (Bus Matching), IW (Input Width) and OW (Output Width) determine the input and output port bus widths as per the selections shown in Table 3, "Bus Matching Set-Up". 9 bit bytes, 18 bit words and 36 bit long words can be written into and read from the queues provided that at least one of the ports is setup for x36 operation. When writing to or reading from the multi-queue in a bus matching mode, the device orders data in a "Little Endian" format. See Figure 3, Bus Matching Byte Arrangement for details. The Full flag and Almost Full flag operation is always based on writes and reads of data widths determined by the write port width. For example, if the input port is x36 and the output port is x9, then four data reads from a full queue will be required to cause the full flag to go HIGH (queue not full). Conversely, the Output Valid flag and Almost Empty flag operations are always based on writes and reads of data widths determined by the read port. For example, if the input TABLE 3 BUS-MATCHING SET-UP x36 DEVICE BM IW OW Write Port Read Port 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 x36 x36 x36 x18 x9 x36 x18 x9 x36 x36 PAFn FLAG BUS OPERATION The IDT72V51546/72V51556 IDT72V51546/72V51556 multi-queue flow-control devices can be configured for up to 32 queues, each queue having its own almost full status. An active queue has its flag status output to the discrete flags, FF and PAF, on the write port. Queues that are not selected for a write operation can have their PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide, so that 8 queues at a time can have their status output to the bus. If 9 or more queues are setup within a device then there are 2 methods by which the device can share the bus between queues, "Direct" mode and "Polled" mode depending on the state of the FM (Flag Mode) input during a Master Reset. If 8 or less queues are setup within a device then each will have its own dedicated output from the bus. If 8 or less queues are setup in single device mode, it is recommended to configure the PAFn bus to polled mode as it does not require using the write address (WRADD). port is x18 and the output port is x36, two write operations will be required to cause the output valid flag of an empty queue to go LOW, output valid (queue is not empty). Note, that the input port serves all queues within a device, as does the output port, therefore the input bus width to all queues is equal (determined by the input port size) and the output bus width from all queues is equal (determined by the output port size). EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES Expansion can take place using either the standard mode or the packet mode. In the 32 queue multi-queue device, the WRADD address bus is 8 bits wide. The 5 Least Significant bits (LSbs) are used to address one of the 32 available queues within a single multi-queue device. The 3 Most Significant bits FULL FLAG OPERATION The multi-queue flow-control device provides a single Full Flag output, FF. The FF flag output provides a full status of the queue currently selected on the write port for write operations. Internally the multi-queue flow-control device monitors and maintains a status of the full condition of all queues within it, however 22 IDT72V51546/72V51556 IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits only the queue that is selected for write operations has its full status output to the FF flag. This dedicated flag is often referred to as the "active queue full flag". When queue switches are being made on the write port, the FF flag output will switch to the new queue and provide the user with the new queue status, on the cycle after a new queue selection is made. The user then has a full status for the new queue one cycle ahead of the WCLK rising edge that data can be written into the new queue. That is, a new queue can be selected on the write port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the next rising edge of WCLK, the FF flag output will show the full status of the newly selected queue. On the second rising edge of WCLK following the queue selection, data can be written into the newly selected queue provided that data and enable setup & hold times are met. Note, the FF flag will provide status of a newly selected queue one WCLK cycle after queue selection, which is one cycle before data can be writ