NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| IDT72V36110 | Integrated Device Technology, Inc. | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO |
36 pages, |
Original |  |
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| IDT72V36110L10PF | Integrated Device Technology, Inc. | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO |
36 pages, |
Original | |
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| IDT72V36110L10PF | Integrated Device Technology, Inc. | 3.3 V High-Density Supersync II 36 Bit FIFO 131,072 x 36 |
48 pages, |
Original | |
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| IDT72V36110L10PF8 | Integrated Device Technology, Inc. | 128K x 36 SuperSync II FIFO, 3.3V |
48 pages, |
Original | |
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| IDT72V36110L15PF | Integrated Device Technology, Inc. | 3.3 V High-Density Supersync II 36 Bit FIFO 131,072 x 36 |
48 pages, |
Original | |
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| IDT72V36110L15PF | Integrated Device Technology, Inc. | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO |
36 pages, |
Original | |
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| IDT72V36110L15PF8 | Integrated Device Technology, Inc. | 128K x 36 SuperSync II FIFO, 3.3V |
48 pages, |
Original | |
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| IDT72V36110L15PFI | Integrated Device Technology, Inc. | 3.3 V High-Density Supersync II 36 Bit FIFO 131,072 x 36 |
48 pages, |
Original | |
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| IDT72V36110L15PFI | Integrated Device Technology, Inc. | 3.3V, high-density, low power, 131072 x 36-bit FIFO, 15ns |
36 pages, |
Original | |
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| IDT72V36110L15PFI8 | Integrated Device Technology, Inc. | 128K x 36 SuperSync II FIFO, 3.3V |
48 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Commercial TQFP Only IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7-5 IDT72V36110L10 Min. Max. Min. , 8 - 8 - 8 - 8 IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36110L7-5 Min. Max. - 83 0.6 10 12 - 5 , IDT72V36110. The offset "m" is the full offset value. The default setting for these values are stated in the , : IDT72V36100 IDT72V36100 65,536 x 36 IDT72V36110 131,072 x 36 Higher density, 2Meg and 4Meg SuperSync II FIFOs Up to , programmable settings · · · · · · · · · · · · IDT72V36100 IDT72V36100 IDT72V36110 Empty, Full and ... | Original |
48 pages, |
IDT72V36100 72V36100 IDT72V36110 36-BIT 36-BIT abstract |
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| Abstract: IDT72V36100L10 IDT72V36100L10 IDT72V36110L7-5 IDT72V36110L10 Min. Max. Min. Max. - 133.3 - 100 (5) (5) 1 5 1 , IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36110L7-5 Min. Max. - 83 0.6 10 12 - 5 - 5 - 10 - - 10 - 10 - , ) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the full , bits for the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag Registers, for the , ,536 x 36 IDT72V36110 131,072 x 36 Higher density, 2Meg and 4Meg SuperSync II FIFOs Up to 166 MHz ... | Original |
48 pages, |
36-BIT IDT72V36100 IDT72V36110 36-BIT abstract |
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| Abstract: Commercial TQFP Only IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7-5 IDT72V36110L10 Min. Max. Min. , Flag Com'l & Ind'l IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36110L7-5 Min. Max. - 83 0.6 10 12 - 5 - 5 , ,536-m) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the , : IDT72V36100 IDT72V36100 65,536 x 36 IDT72V36110 131,072 x 36 Higher density, 2Meg and 4Meg SuperSync II FIFOs Up to , programmable settings · · · · · · · · · · · · IDT72V36100 IDT72V36100 IDT72V36110 Empty, Full and ... | Original |
48 pages, |
IDT72V36110 IDT72V36100 72V36100 36-BIT 36-BIT abstract |
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| Abstract: Commercial TQFP Only IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7-5 IDT72V36110L10 Min. Max. Min. , apply to the PBGA package only. 10 IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36110L7-5 Min. Max. - 83 0.6 10 , IDT72V36110. The offset "m" is the full offset value. The default setting for these values are stated in the , ,536 x 36 IDT72V36110 131,072 x 36 Higher density, 2Meg and 4Meg SuperSync II FIFOs Up to 166 MHz , programmable settings · · · · · · · · · · · · · IDT72V36100 IDT72V36100 IDT72V36110 Empty, Full and ... | Original |
47 pages, |
IDT72V36110 IDT72V36100 72V36100 72V36110 36-BIT 36-BIT abstract |
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| Abstract: IDT72V3680L7 IDT72V3680L7.5 IDT72V3680L10 IDT72V3680L10 IDT72V3690L7 IDT72V3690L7.5 IDT72V3690L10 IDT72V3690L10 IDT72V36100L7 IDT72V36100L7.5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7.5 , ) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the full offset , 65,536 x 36 IDT72V36110 131,072 x 36 133 MHz operation (7.5 ns read/write cycle time) User , IDT72V3680 IDT72V3680, IDT72V3690 IDT72V3690 IDT72V36100 IDT72V36100, IDT72V36110 · · · · · · · · · · · · · · · Zero latency , IDT72V3650L IDT72V3650L IDT72V3660L IDT72V3660L IDT72V3670L IDT72V3670L IDT72V3680L IDT72V3680L IDT72V3690L IDT72V3690L IDT72V36100L IDT72V36100L IDT72V36110L Commercial and ... | Original |
36 pages, |
IDT72V36100 IDT72V36110 IDT72V3640 IDT72V3650 IDT72V3660 IDT72V3670 IDT72V3680 IDT72V3690 quad 2-input or gate expandable IR 536 36-BIT 36-BIT abstract |
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| Abstract: IDT72V36100L7-5 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7-5 IDT72V36110L10 Symbol fS tA tCLK tCLKH tCLKL tDS tDH , ) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the full , IDT72V36110. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this , ,537 for the IDT72V36100 IDT72V36100 and 131,073 for the IDT72V36110. If IDT Standard mode is selected, the FIFO , 3.3 VOLT HIGH-DENSITY SUPERSYNCTM II 36-BIT 36-BIT FIFO IDT72V36100 IDT72V36100 IDT72V36110 65,536 x36 131,072 ... | Original |
36 pages, |
IDT72V36110 IDT72V36100 72V36110 72V36100 36-BIT 36-BIT abstract |
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| Abstract: IDT72V3690L10 IDT72V3690L10 IDT72V36100L7 IDT72V36100L7.5 IDT72V36100L10 IDT72V36100L10 IDT72V36110L7.5 IDT72V36110L10 tPAFS tPAEA tPAES tHF , ) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the full offset , , IDT72V3670 IDT72V3670 IDT72V3680 IDT72V3680, IDT72V3690 IDT72V3690 IDT72V36100 IDT72V36100, IDT72V36110 Zero latency retransmit Auto , 65,536 x 36 IDT72V36110 131,072 x 36 133 MHz operation (7.5 ns read/write cycle time) User , ) IDT72V3640L IDT72V3640L IDT72V3650L IDT72V3650L IDT72V3660L IDT72V3660L IDT72V3670L IDT72V3670L IDT72V3680L IDT72V3680L IDT72V3690L IDT72V3690L IDT72V36100L IDT72V36100L IDT72V36110L ... | Original |
36 pages, |
Time Clock IDT72V3690 IDT72V3680 IDT72V3670 IDT72V3660 IDT72V3650 IDT72V3640 IDT72V36110 IDT72V36100 36-BIT 36-BIT abstract |
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| Abstract: for the IDT72V36110. The offset "m" is the full offset value. The default setting operations, the PAE , for the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing , 32,768 x 36, 65,536 x36 IDT72V3690 IDT72V3690, IDT72V36100 IDT72V36100 131,072 x 36 IDT72V36110 FEATURES , IDT72V36110 131,072 x 36 100 MHz operation (10 ns read/write cycle time) User selectable input and output , IDT72V36100L IDT72V36100L IDT72V36110L Commercial tCLK = 10, 15 ns Symbol (1) Parameter Min. Max. Unit ... | Original |
33 pages, |
IDT72V3690 IDT72V3680 IDT72V3670 IDT72V3660 IDT72V3650 IDT72V3640 IDT72V36110 IDT72V36100 36-BIT IDT72V3630 36-BIT abstract |
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| Abstract: the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset "m" is the full offset value. , IDT72V36110. See Figure 14, Serial Loading of Programmable Flag Registers, for the timing diagram for this , ,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 the IDT72V36110. In FWFT , the IDT72V3690 IDT72V3690, 65,537 for the IDT72V36100 IDT72V36100 and 131,073 for the IDT72V36110. If IDT Standard mode is , IDT72V3690 IDT72V3690 32,768 x 36 IDT72V36100 IDT72V36100 65,536 x 36 IDT72V36110 131,072 x 36 · 100 MHz operation (10 ns read ... | Original |
32 pages, |
IDT72V3690 IDT72V3680 IDT72V3670 IDT72V3660 IDT72V36110 IDT72V36100 72V3660 72V36110 36-BIT 36-BIT abstract |
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| Abstract: IDT72V3690 IDT72V3690, (65,536-m) writes for the IDT72V36100 IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset , , 30 bits for the IDT72V3690 IDT72V3690, 32 bits for the IDT72V36100 IDT72V36100 and 34 bits for the IDT72V36110. See Figure , and 131,072 for the IDT72V36110. In FWFT mode, D = 4,097 for the IDT72V3660 IDT72V3660, 8,193 for the , for the IDT72V36110. If IDT Standard mode is selected, the FIFO will mark the beginning of the , IDT72V3690 IDT72V3690 32,768 x 36 IDT72V36100 IDT72V36100 65,536 x 36 IDT72V36110 131,072 x 36 · 100 MHz operation (10 ns read ... | Original |
35 pages, |
IDT72V3690 IDT72V3680 IDT72V3670 IDT72V3660 IDT72V36110 IDT72V36100 72V3660 72V36110 36-BIT 36-BIT abstract |
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| . Trademarks Email: webmaster@idt.com IDT72V36110 www.datasheetarchive.com/files/idt/docs/rp00008/rp008ce.htm |
IDT | 06/10/2000 | 19.79 Kb | HTM | rp008ce.htm |
| @idt.com Page updated Wednesday, January 05, 2000 at 03:30 PM IDT72V36110 www.datasheetarchive.com/files/idt/docs/wcd0000b/wcd00b84.htm |
IDT | 24/01/2000 | 11.67 Kb | HTM | wcd00b84.htm |
| > www.datasheetarchive.com/files/idt/docs/wcd00010/wcd010db.htm |
IDT | 17/06/1999 | 9.59 Kb | HTM | wcd010db.htm |
| @idt.com Page updated Wednesday, January 05, 2000 at 03:30 PM IDT72V36110 www.datasheetarchive.com/files/idt/docs/wcd00001/wcd001cd.htm |
IDT | 24/01/2000 | 10.2 Kb | HTM | wcd001cd.htm |
| MHz 128Kx36 IDT72V36110 100MHz www.datasheetarchive.com/files/idt/docs/wcd00002/wcd00231-v1.htm |
IDT | 30/06/1999 | 9.61 Kb | HTM | wcd00231-v1.htm |