IDT72T6480 IDT72T6360 DSC-6358/- 128MB BB324-1 BA1-B11 BA0-C11 MIC2-U10 - Datasheet Archive

 

48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM · IDT Standard mode or FWFT mode of operation ·

 

2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM · IDT Standard mode or FWFT mode of operation · Empty and full flags for monitoring memory status · Programmable Almost-Empty and Almost-Full flags, each flag FEATURES · Product to be used with single or multiple external DDR SDRAM to provide significant storage capability of up to 1Gb density can default to one of four preselected offsets or serially programmed to a specific value · Selectable synchronous/asynchronous timing modes for Almost-Empty and Almost-Full flags · Master Reset clears all data and settings · Partial Reset clears data, but retains programmable settings · Depth expandable with multiple devices for densities greater than 1Gb · Width expandable with multiple devices for bus widths greater than 36 bits · JTAG functionality (Boundary Scan) · Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm · HIGH performance 0.18µm CMOS technology µ · Industrial temperature range (-40°C to +85°C) is available ° ° · Supports industry standard DDR specifications, including Samsung, Micron, and Infineon memories · 133MHz operation (7.5ns read/write cycle time) · User selectable input and output port bus-sizing · · · · ADVANCE INFORMATION IDT72T6480 IDT72T6480 - x48in to x48out - x48in to x24out - x48in to x12out - x24in to x48out - x24in to x24out - x24in to x12out - x12in to x48out - x12in to x24out - x12in to x12out For other bus configurations see IDT72T6360 IDT72T6360 (x9, x18, or x36) 2.5V-LVTTL or 3.3V-LVTTL independently configured ports Independent and simultaneous read and write access User selectable synchronous/asynchronous read and write port timing FUNCTIONAL BLOCK DIAGRAM FWFT 36-bits 8 MCLK 13 64 I/O Bus Configuration PRS IOSEL BM[3:0] x48, x24, or x12 Read Control Logic 36-bits Output Register 36-bits CK DQS WE CAS RAS Addr MRS REN RCLK/RD RCS ASYR 6358 drw01 TDI/SI CK JTAG Control (Boundary Scan) TDO/SO DDR SDRAM Control Logic TMS WCS ASYW TCK/SCLK WCLK/WR Data WEN Write Control Logic x48, x24, or x12 Input Register FF/IR PAF EF/OR PAE Flag Logic Reset Logic IDT72T6480 IDT72T6480 Sequential Flow Control Device FSEL[1:0] High Density DDR SDRAM x16, x32, x36, or x64 128Mb to 256Mb IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6358/- DSC-6358/- COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION List of Contents Features . 1 Device Overview . 4 Pin Configuration . 6 Pin Descriptions . 7 Detailed Descriptions . 11 Functional Descriptions . 17 Signal Descriptions . 18 Device Characteristics . 22 AC Test Conditions . 24 AC Electrical Characteristics . 25 JTAG Timing Specifications . 40 Depth Expansion Configuration . 44 Width Expansion Configuration . 45 List of Tables Table 1 ­ DDR SDRAM Specifications . 11 Table 2 ­ Supported Memory Vendors . 11 Table 3 ­ Total Possible External Memory Configurations . 12 Table 4 ­ DDR SDRAM Static Connections . 13 Table 5 ­ Maximum I/O Operating Frequency Based On Various Configurations . 14 Table 6 ­ Error Detection and Correction Configuration . 14 Table 7 ­ Memory Configurations Settings . 16 Table 8 ­ Device configuration . 17 Table 9 ­ Default Programmable Flag Offsets . 17 Table 10 ­ Number of Bits Required for Offset Registers . 17 Table 11 ­ Bus-Matchings . 19 Table 12 ­ MTYPE[1:0] Configurations . 20 2 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES List of Figures Figure 1. Sequential Flow-Control Device Block Diagram . 5 Figure 2a. Configuration 1 - Two Chip Solution . 13 Figure 2b. Configuration 2 - Two Chip Solution . 13 Figure 2c. Configuration 3 - Three Chip Solution . 13 Figure 2d. Configuration 4 - Three Chip Solution . 13 Figure 2e. Configuration 5 - Three Chip Solution . 13 Figure 2f. Configuration 6 - Four Chip Solution . 13 Figure 2g. Configuration 7 - Five Chip Solution . 13 Figure 3. Memory Interface Connection (Single Chip) . 15 Figure 4. Memory Interface Connection (Two Chip) . 15 Figure 5a. AC Test Load . 24 Figure 5b. Lumped Capacitive Load, Typical Derating . 24 Figure 6. Master Reset and Initialization . 27 Figure 7. Partial Reset . 28 Figure 8. Write First Word Cycles - IDT Standard Mode . 29 Figure 9. Write First Word Cycles - FWFT Mode . 29 Figure 10. Empty Boundary - IDT Standard Mode . 30 Figure 11. Empty Boundary - FWFT Mode . 30 Figure 12. Full Boundary - IDT Standard Mode . 31 Figure 13. Full Boundary - FWFT Mode . 31 Figure 14. Output Enable . 32 Figure 15. Read Chip Select . 32 Figure 16. Write Chip Select . 32 Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode . 33 Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode . 33 Figure 19. Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode . 34 Figure 20. Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode . 34 Figure 21. Synchronous PAE Flag - IDT Standard Mode and FWFT Mode . 35 Figure 22. Synchronous PAF Flag - IDT Standard Mode and FWFT Mode . 35 Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode . 36 Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode . 36 Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode . 36 Figure 26. Asynchronous Empty Boundary - IDT Standard Mode . 37 Figure 27. Asynchronous Full Boundary - IDT Standard Mode. 37 Figure 28. Asynchronous Read and PAE Flag - IDT Standard Mode . 37 Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) . 38 Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes) . 38 Figure 31. Standard JTAG Timing . 39 Figure 32. JTAG Architecture . 40 Figure 33. TAP Controller State Diagram . 41 Figure 34. Depth Expansion Configuration in IDT Standard Mode . 44 Figure 35. Depth Expansion Configuration in FWFT Mode . 44 Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode . 45 3 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION DESCRIPTION The IDT72T6480 IDT72T6480 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports of the sequential flow-control can operate independently at up to 133MHz. There is a user selectable correction feature that will correct any erroneous single data bit when reading from the SDRAM. The independent read and write ports each has associated read and write clocks, enables, and chip selects. Both ports can operate either synchronously or asynchronously. Other features include bus-matching, programmable status flags with selectable synchronous/asynchronous timing modes, IDT Standard or FWFT mode timing, and JTAG boundary scan functionality. The bus-matching feature will allow the inputs and outputs to be configured to x48, x24, or x12 bus width. There are four default offset values available for the programmable flags (PAE/PAF), as well as the option of serially programming the offsets to a specific value. The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM will be 2.5V SSTL only and not 3.3V tolerant. Both industrial and commercial temperature ranges will be offered. The sequential flow-control device controls individual DDR SDRAM of either 128Mb or 256Mb. The device will support industry standard DDR specification memories (note DDR II is not supported), which include vendors such as Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can independently control up to four separate external memories for a maximum of density of 1Gb (128MB 128MB). Depth expansion mode is available for applications that require more than 1Gb of storage memory. 4 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION D[47:0] Input Register 48 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Output Register 48 48 Q[47:0] 48 Output Bus-Matching Logic Input Bus-Matching Logic 144 144 Refresh Counter QP Cache Control Logic 144 144 QP Cache 72 x 36 72 Error 72 Detection Correction optional bypass optional 72 bypass Check Bit Generator 72 Error 72 72 Detection Correction optional bypass 72 State Machine Memory Interface Multi-Clock Arbitration Circuits QP Cache 72 x 36 optional 72 bypass Check Bit Generator 72 DQS[7:0] Logic Control Circuits DQ[63:0] ADDR[12:0] Memory 13 Interface BA[1:0] Address and WE Control CAS 72 RAS CK 72 72 CK Memory Interface Data and Bus-Matching PLL MCLK DLL 64 8 DQ[63:0] DQS[7:0] TMS TDI JTAG TDO TCK 6358 drw02 Figure 1. Sequential Flow-Control Device Block Diagram 5 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN CONFIGURATION A1 BALL PAD CORNER A GND GND DQ10 DQ8 DQ4 DQ1 CK A1 A5 A9 WE RAS DQ35 DQ36 DQ38 DQ40 GND GND GND GND DQS1 DQ9 DQ5 DQ2 AVCC A0 A4 A10 BA1 DQ32 DQS4 DQ39 DQ44 DQS5 GND GND DQ14 DQ13 DQ11 DQ12 DQ6 DQ3 CK A2 A6 A11 BA0 DQ34 DQ37 DQ41 DQ47 DQ45 DQ49 DQ50 DQ16 DQ15 DQ17 DQ7 DQS0 DQ0 AVCC A3 A7 A8 A12 CAS DQ33 DQ43 DQ46 VREF DQ51 DQS6 DQ19 DQ18 DQS2 DQ20 DQ21 AGND AGND VCC VCC VCC VCC VCC VCC DQ42 DQ23 DQ22 DQ24 DQ25 DQ26 VCC VCC VCC VCC VCC VCC VCC VCC DQ59 DQS3 DQ27 DQ28 DQ29 DQ30 VCC VCC GND GND GND GND VCC VCC VCC MCLK DQ31 D0 D1 D2 VCC GND GND GND GND GND GND VDDQ D4 D3 D5 D6 D7 VCC GND GND GND GND GND GND D11 D12 D10 D9 D8 VCC GND GND GND GND GND D16 D17 D15 D14 GND GND GND D21 D22 D20 D19 D26 D27 D25 D24 D31 D32 D30 D34 D35 D36 B C D E Y R DQ54 DQ48 DQ52 DQ53 DQ58 DQ55 DQ56 DQ57 DQ62 DQ61 DQS7 DQ60 VDDQ Q2 Q1 DQ63 Q0 VDDQ VDDQ Q6 Q5 Q3 Q4 GND VDDQ VDDQ Q7 Q12 Q8 Q9 GND GND VDDQ VDDQ Q13 Q11 Q10 Q14 Q15 Q16 Q17 F A IN G H J IM L K E R L D13 VCC VCC D18 VCC VCC VCC GND GND GND VDDQ VDDQ VDDQ D23 VCC VCC VCC VCC VCC VCC VDDQ VDDQ Q23 Q29 Q19 Q20 Q18 D29 D28 FSEL1 IOSEL VCC BM3 MIC0 JSEL TDO/SO Q47 Q32 Q33 Q31 Q25 Q21 D33 D38 D45 FSEL0 IDEM MTYPE0 BM2 MIC1 TDI/SI FF/ IR Q46 Q42 Q34 Q30 Q26 Q22 D37 D39 D40 D41 ASYW WCS MSPEED BM1 TMS SWEN PAF Q45 Q41 Q35 Q36 Q27 Q24 GND GND D42 D43 D46 PRS FWFT MTYPE1 BM0 MIC2 TCK/ SCLK OE PAE Q43 Q39 Q37 GND GND GND GND D44 D47 MRS ASYR WEN WCLK/ WR RCLK/ RD REN SREN RCS EF/ OR Q44 Q40 Q38 GND GND 3 4 6 7 8 9 10 11 12 13 14 15 16 17 M N P P Q28 R T U V 1 2 5 18 6358 drw03 PBGA (BB324-1 BB324-1, order code: BB) TOP VIEW 6 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS Symbol A[12:0] Pin No. Name Location See Pin Memory Address Bus No. table ASYR(1) V6 Asynchronous Read Port ASYW(1) T6 Asynchronous Write Port BA[1:0] BA1-B11 BA1-B11 BA0-C11 BA0-C11 Memory Bank Address Input Bit BM[3:0](1) See Pin tbl. Bus-Matching Bit I/O TYPE Description OUTPUT Output address bus to be connected to the input address bus of the external memory to provide row and column address. INPUT A HIGH on this input during master reset will select synchronous read operation for the output port. A LOW will select asynchronous operation. If asynchronous is selected the device must operate in IDT Standard mode and the read enable must be tied to GND. INPUT A HIGH on this input during master reset will select synchronous write operation for the input port. A LOW will select asynchronous operation. If asynchronous is selected the device must operate in IDT Standard mode and the write enable must be tied to GND. OUTPUT Address bits to be connected to the external memory's BA inputs to determine which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. INPUT Selects the bus width of the read and write ports. CK C7 Memory Clock CK A7 Memory Clock Inverted OUTPUT Differential clock output to be connected to the external memory's differential input clock. CAS D12 Memory Column Address Strobe D[47:0] See Pin tbl. Data Inputs DQ[63:0] See Pin No. table Memory Data Bus DQS[7:0] See Pin Memory Data Strobe No. table OUTPUT Clock output to be connected to the external memory's input clock. OUTPUT Output enable signal to be connected to the external memory's CAS pin to activate and deactivate the column address strobe. INPUT Data inputs for a 48, 24, and 12-bit bus. BiInput/output data bus for the external memory's data bus. Directional BiInput/output data strobe to be connected to the external memory's data strobe. Directional EF/OR V13 Empty Flag/ Output Ready OUTPUT In IDT Standard mode, the EF function is selected. EF indicates whether or not the device memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. FF/IR R12 Full Flag/Input Ready OUTPUT In IDT Standard mode, the FF function is selected. FF indicates whether or not the device memory is full. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the device memory. FSEL[1:0](1) FSEL1-P6 Flag Select Bit INPUT During master reset, these inputs will select one of four default values for the programmable flags PAE and PAF. The selected value will apply to both PAE and PAF offset. FSEL0-R6 FWFT(1) U7 First Word Fall Through INPUT During master reset, a HIGH on this input selects FWFT timing mode. A LOW selects IDT Standard timing mode. IDEM(1) R7 IDT Standard Mode Depth Expansion Mode Select INPUT This select pin is used for depth expansion configuration in IDT Standard mode. If this pin is tied HIGH, then the FF/IR signal will be inverted to provide a seamless depth expansion interface. If this pin is tied LOW, the depth expansion in IDT Standard mode will be deactivated. IOSEL(1) P7 I/O VDDQ Select INPUT This input determines whether the inputs and outputs will tolerate a 2.5V or 3.3V voltage signals. If IOSEL is HIGH, then all I/Os will be 2.5V tolerant. If IOSEL is LOW, then all I/Os will be 3.3V tolerant. JSEL(1) P11 JTAG Select INPUT This pin selects whether the JTAG pins will be used for serial programming. If JSEL is HIGH, the JTAG pins will only be used for JTAG boundary-scan function. If JSEL is LOW, the JTAG function is disabled and the JTAG pins will be used for serial programming of the PAE/PAF offset registers. MIC[2:0](1) MIC2-U10 MIC2-U10 Memory Configuration MIC1-R10 MIC1-R10 MIC0-P10 MIC0-P10 INPUT These signals enable the EDC feature of the device. See Table 6, Error Detection and Correction Configuration (EDC) for all possible configurations. MCLK H1 Master Clock INPUT 33MHz reference clock used to generate CK and CK for external memory interface. MRS V5 Master Reset INPUT Master reset initializes the read and write pointers to zero and sets the output register to all zeros. All initialized settings for the device will be configured during master reset. 7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (CONTINUED) Symbol MSPEED(1) Pin No. Name Location T8 Memory Speed I/O TYPE Description INPUT This input select the speed of the external memory interfacing the sequential flow-control device. A LOW selects 133MHz, and HIGH selects 166MHz. MTYPE(1) MTYPE1-U8 Memory Type [1:0] MTYPE0-R8 [1:0] INPUT These inputs select which type of external memory is interfacing the sequential flow-control device. See Table 10 for the list of selectable memories. OE U12 Output Enable INPUT Asynchronous three-state control of the data outputs. All data outputs Q[35:0] will be placed in high-impedance if this pin is HIGH. Conversely, all data outputs will be active when this pin is LOW. PAE U13 Programmable Almost Empty Flag OUTPUT This is the programmable almost empty flag that can be used as an early indicator for the empty boundary condition of the internal memory. PAE goes LOW if the number of words in the sequential flow-control device is less than offset n, which is stored in the empty offset register. PAE goes HIGH if the number of words in the sequential flow-control device is greater than or equal to the offset n. PAF T12 Programmable Almost Full Flag OUTPUT This is the programmable almost full flag that can be used as an early indicator for the full boundary condition of the internal memory. PAF goes HIGH if the number of free locations in the sequential flow-control device is more than offset m, which is stored in the full offset register. PAF goes LOW if the number of free locations in the sequential flow-control device is less than or equal to the offset m. PRS U6 Partial Reset Q[47:0] See Pin tbl. Data Output Bus INPUT Partial reset initializes the read and write pointers to zero and sets the output registers to all zeros. All existing configurations in the sequential flow-control device will not be affected. This includes the IDT Standard or FWFT mode timing, programmable flag settings, and bus width and data rate mode. OUTPUT Data outputs for a 48, 24, and 12-bit bus. RAS A12 Memory Row Address OUTPUT Output strobe signal to be connected to the external memory's RAS pin to activate and Strobe deactivate the row address strobe. RCLK/ RD V9 Read Clock/ Read Strobe INPUT This is a dual function pin. If synchronous operation of the read port is selected, the rising edge of RCLK reads data from the sequential flow-control device when REN is enabled. If asynchronous operation of the read port is selected, a rising edge on RD reads data from the sequential flow-control device without the need of a free-running input read clock. RCS V12 Read Chip Select INPUT Synchronous three-state control of the data outputs. Provides another means of controlling the data outputs synchronous to RCLK. Can be regarded as a second output enable signal. REN V10 Read Enable INPUT REN enables RCLK for reading data from the sequential flow-control device. If asynchronous mode is selected on the read port, this signal should be tied to GND. SREN V11 Serial Read Enable INPUT When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin. SWEN T11 Serial Write Enable INPUT On each rising edge of SCLK when SWEN is LOW, data from the FWFT pin is serially loaded into the PAE and PAF registers. TCK/ SCLK U11 JTAG Clock/ Serial Clock INPUT This is a dual function pin. When the JSEL pin is HIGH, this is the clock input for JTAG boundaryscan function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. When the JSEL pin is LOW, this is the serial clock input for writing and reading the PAE/PAF offset registers. On the rising edge of every SCLK when SWEN is LOW, one bit of data from the SI pin is shifted into the PAE and PAF offset registers. On the rising edge of each SCLK when SREN is LOW, one bit of data from the SO pin is shifted out of the PAE and PAF offset registers. If the JTAG or serial programming is not used this signal needs to be tied to GND. 8 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol TDI/SI Pin No. Name Location R11 JTAG Test Data Input/ Serial Input I/O TYPE INPUT Description This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data input pin. One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to the Instruction Register, ID Register and Bypass Register. When the JSEL pin is LOW, this is the serial input pin for the PAE/PAF offset registers. An internal pull-up resistor forces TDI/SI HIGH if left unconnected. TDO/SO P12 JTAG Test Data Output/ OUTPUT This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data output pin. Serial Output One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high-impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. When the JSEL pin is LOW, this is the serial data output pin for the PAE/PAF offset registers. TMS T10 JTAG Mode Select INPUT TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. WCLK/WR V8 Write Clock/Write Strobe INPUT This is a dual function pin. If synchronous operation of the write port is selected, the rising edge of WCLK writes data into the sequential flow-control device when WEN is enabled. If asynchronous operation of the write port is selected, a rising edge on WR writes data into the sequential flow-control device without the need of a free-running input write clock. WCS T7 Write Chip Select Synchronous three-state control of the data inputs. Provides a means of controlling the data inputs synchronous to WCLK. Typically used to avoid bus-contention when multiple devices are sharing the same input data bus. WE A11 Memory Write Enable WEN V7 Write Enable V CC See Pin No. table Core VCC and Output Power voltage for DDR SDRAM The core power supply pins for the device as well as to the external DDR SDRAM. Needs to be connected to a +2.5V VCC power plane. AVCC B7, D7 Internal PLL VCC Power The power supply pins for the internal PLL of the device. Needs to be connected to a +2.5V supply rail. VDDQ See Pin No. table Output rail voltage for I/Os Power This pin is used to provide power to the output drivers. The nominal values are 2.5V or 3.3V, depending on the state of the IOSEL pin. V REF D16 Reference Voltage Power This is a voltage reference input to the SDRAM and must be connected to VCC/2 or 1.25V. Ground The ground pins for the device that must be connected to the ground plane. Ground The ground pins for the analog circuitry in the device that must be connected to the ground plane. GND AGND See Pin table Ground Pin E6, E7 Ground pin for analog circuit INPUT OUTPUT Output strobe signal to be connected to the external memory's WE pin to activate and deactivate the write address strobe. INPUT WEN enables WCLK for writing data into the sequential flow-control device. If asynchronous mode is selected on the write port, this signal should be tied to GND. NOTE: 1. These pins should not change after master reset. Please see next page for Pin Number Location Table 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN NUMBER LOCATION TABLE Symbol Name I/O TYPE Pin Number A[12:0] Memory Address Bus OUTPUT BM[3:0] Bus-Matching INPUT BM3-P9, BM2-R9, BM1-T9, BM0-U9 D[47:0] Data Inputs INPUT D47-V4 D47-V4, D46-U5 D46-U5, D45-R5 D45-R5, D44-V3 D44-V3, D43-U4 D43-U4, D42-U3 D42-U3, D41-T5 D41-T5, D40-T4 D40-T4, D39-T3 D39-T3, D38-R4 D38-R4, D37-T2 D37-T2, D36-T1 D36-T1, D35-R2 D35-R2, D34-R1 D34-R1, D33-R3 D33-R3, D32-P2 D32-P2, D31-P1 D31-P1, D30-P3 D30-P3, D29-P4 D29-P4, D28-P5 D28-P5, D27-N2 D27-N2, D26-N1 D26-N1, D25-N3 D25-N3, D24-N4 D24-N4, D23-N5 D23-N5, D22-M2 D22-M2, D21-M1 D21-M1, D20-M3 D20-M3, D19-M4 D19-M4, D18-M5 D18-M5, D17-L2 D17-L2, D16-L1 D16-L1, D15-L3 D15-L3, D14-L4 D14-L4, D13-L5 D13-L5, D12-K2 D12-K2, D11-K1 D11-K1, D10-K3 D10-K3, D9-K4, D8-K5, D7-J5, D6-J4, D5-J3, D4-J1, D3-J2, D2-H5, D1-H4, D0-H3 A12-D11 A12-D11, A11-C10 A11-C10, A10-B11 A10-B11, A9-A10 A9-A10, A8-D10 A8-D10, A7-D9, A6-C9, A5-A9, A4-B9, A3-D8, A2-C8, A1-A8, A0-B8 DQ[63:0] Memory Data Bus BiDQ63-H17, DQ62-G15 DQ62-G15, DQ61-G16 DQ61-G16, DQ60-G18 DQ60-G18, DQ59-F14 DQ59-F14, DQ58-F15 DQ58-F15, DQ57-F18 DQ57-F18, DQ56-F17 DQ56-F17, Directional DQ55-F16 DQ55-F16, DQ54-E15 DQ54-E15, DQ53-E18 DQ53-E18, DQ52-E17 DQ52-E17, DQ51-D17 DQ51-D17, DQ50-C18 DQ50-C18, DQ49-C17 DQ49-C17, DQ48-E16 DQ48-E16, DQ47-C15 DQ47-C15, DQ46-D15 DQ46-D15, DQ45-C16 DQ45-C16, DQ44-B15 DQ44-B15, DQ43-D14 DQ43-D14, DQ42-E14 DQ42-E14, DQ41-C14 DQ41-C14, DQ40-A16 DQ40-A16, DQ39-B14 DQ39-B14, DQ38-A15 DQ38-A15, DQ37-C13 DQ37-C13, DQ36-A14 DQ36-A14, DQ35-A13 DQ35-A13, DQ34-C12 DQ34-C12, DQ33-D13 DQ33-D13, DQ32-B12 DQ32-B12, DQ31-H2 DQ31-H2, DQ30-G5 DQ30-G5, DQ29-G4 DQ29-G4, DQ28-G3 DQ28-G3, DQ27-G2 DQ27-G2, DQ26-F5 DQ26-F5, DQ25-F4 DQ25-F4, DQ24-F3 DQ24-F3, DQ23-F1 DQ23-F1, DQ22-F2 DQ22-F2, DQ21-E5 DQ21-E5, DQ20-E4 DQ20-E4, DQ19-E1 DQ19-E1, DQ18-E2 DQ18-E2, DQ17-D3 DQ17-D3, DQ16-D1 DQ16-D1, DQ15-D2 DQ15-D2, DQ14-C1 DQ14-C1, DQ13-C2 DQ13-C2, DQ12-C4 DQ12-C4, DQ11-C3 DQ11-C3, DQ10-A3 DQ10-A3, DQ9-B4, DQ8-A4, DQ7-D4, DQ6-C5, DQ5-B5, DQ4-A5, DQ3-C6, DQ2-B6, DQ1-A6, DQ0-D6, DQS[7:0] Memory Data Strobe BiDQS7-G17, DQS6-D18 DQS6-D18, DQS5-B16 DQS5-B16, DQS4-B13 DQS4-B13, DQS3-G1, DQS2-E3, DQS1-B3, DQS0-D5 Directional Q[47:0] Data Outputs Output Q47-P13 Q47-P13, Q46-R13 Q46-R13, Q45-T13 Q45-T13, Q44-V14 Q44-V14, Q43-U14 Q43-U14, Q42-R14 Q42-R14, Q41-T14 Q41-T14, Q40-V15 Q40-V15, Q39-U15 Q39-U15, Q38-V16 Q38-V16, Q37-U16 Q37-U16, Q36-T16 Q36-T16, Q35-T15 Q35-T15, Q34-R15 Q34-R15, Q33-P15 Q33-P15, Q32-P14 Q32-P14, Q31-P16 Q31-P16, Q30-R16 Q30-R16, Q29-N15 Q29-N15, Q28-M15 Q28-M15, Q27-T17 Q27-T17, Q26-R17 Q26-R17, Q25-P17 Q25-P17, Q24-T18 Q24-T18, Q23-N14 Q23-N14, Q22-R18 Q22-R18, Q21-P18 Q21-P18, Q20-N17 Q20-N17, Q19-N16 Q19-N16, Q18-N18 Q18-N18, Q17-M18 Q17-M18, Q16-M17 Q16-M17, Q15-M16 Q15-M16, Q14-L18 Q14-L18, Q13-L15 Q13-L15, Q12-K16 Q12-K16, Q11- L16, Q10-L17 Q10-L17, Q9-K18 Q9-K18, Q8-K17 Q8-K17, Q7-K15 Q7-K15, Q6-J15 Q6-J15, Q5-J16 Q5-J16, Q4-J18 Q4-J18, Q3-J17 Q3-J17, Q2-H15 Q2-H15, Q1-H16 Q1-H16, Q0-H18 Q0-H18 VCC Core VCC & Output voltage for DDR SDRAM Power E(8-13), F(6-13), G(6,7,12-14), H6, J6, K6, L(6,7), M(6-8), N(6-11), R(4,5), T(1-5), U(3-5), V(3,4) VDDQ Output rail voltage for I/Os Power H(13,14), J(13,14), K(13,14), L(13,14), M(12-14), N(12,13) GND Ground Pin Ground G(8-11), H(7-12), J(7-12), K(7-12), L(8-12), M(9-11), P8 DNC Do Not Connect - P13, R(13,14), T(13,14,16), U(14-16), V(14-16) 10 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Reading from the SFC device is accomplished by setting the read enable signal (REN) and read chip select (RCS) low with a free running read clock (RCLK). Data will be sent to the output bus on the rising edge of every RCLK. This data will be accessed either from the QP cache or the external DDR SDRAM. DETAILED DESCRIPTIONS SEQUENTIAL FLOW-CONTROL STRUCTURE The IDT sequential flow-control (SFC) device is comprised of three interfaces: input port, output port, and memory interface. The input and output port can operate independently of each other with selectable bus widths of x12, x24, or x48 bits wide. The third interface, or memory interface, is connected directly to an external memory, which can be used to offload data entering the SFC device. EXTERNAL MEMORY SELECTION The DDR SDRAM interface of the SFC device can support DDR SDRAM with standard DDR I specifications. The SFC device can support any external memory within the following characteristics: WRITING AND READING FROM THE SEQUENTIAL FLOW-CONTROL DEVICE Writing into the SFC device is accomplished by setting the write enable signal (WEN) and write chip select (WCS) low with a free running write clock (WCLK). Data will be written on the rising edge of every WCLK into the Quad-Port (QP) cache of the SFC device. The internal state machine of the device will determine whether to send the data to the DDR SDRAM or send it directly through to the output bus, depending on when the data is to be accessed. This provides "data coherency" and minimizes the path that the data has to travel. · · · Bus width: 16-bit or 32-bit wide Speed: 133MHz or 166MHz Density: 128Mb or 256Mb Table 1 lists the DDR SDRAM specifications that are required to meet the sequential flow-control device requirements. Table 2 lists the memory vendors and associated part numbers of DDR SDRAMs that have been validated by IDT to meet the requirements for the DDR SDRAM interface. TABLE 1 ­ DDR SDRAM SPECIFICATIONS DDR SDRAM Specifications DDR SDRAM Bus-Width 16-bit 32-bit CL tRCWD tWR 3 2 3 3 2.5 3 tRCDR tRP tRFC 3 4 3 4 tWR + tRP Units 12 14 6 7 ns ns TABLE 2 ­ SUPPORTED MEMORY VENDORS Density 128Mb Bus Width 16 Vendor Samsung 128Mb 16 Micron 128Mb 16 Infineon 128Mb 256Mb 32 16 Samsung Samsung 256Mb 16 Micron 256Mb 16 Infineon 256Mb 32 Samsung Part# K4M281638E-TCLB3 K4M281638E-TCLB3 K4M281638E-TCLA2 K4M281638E-TCLA2 MT46V8M16TG-6T MT46V8M16TG-6T MT46V8M16TG-75 MT46V8M16TG-75 HYB25D128160ATL-6 HYB25D128160ATL-6 HYB25D128160ATL-7 HYB25D128160ATL-7 K4D263238E-GC45 K4D263238E-GC45 K4H561638F-TCLB3 K4H561638F-TCLB3 K4H561638F-GCLB3 K4H561638F-GCLB3 MT46V16M16TG-6T MT46V16M16TG-6T MT46V16M16TG-75 MT46V16M16TG-75 HYB25D256160BTL-6 HYB25D256160BTL-6 HYB25D256160BTL-7 HYB25D256160BTL-7 K4D553238E-JC50 K4D553238E-JC50 11 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION · Two 16-bit devices connecting a x32 interface to the DDR SDRAM · Two 32-bit devices connecting a x36 interface to the DDR SDRAM · Two 32-bit devices connecting a x64 interface to the DDR SDRAM EXTERNAL MEMORY CONFIGURATIONS The DDR SDRAM interface of the sequential flow-control (SFC) device has a 64-bit output data bus that provides up to four (16-bit SDRAM) external DDR SDRAM connections. For multiple memory connections, they must be of the same density configuration and speed grade. For example, two device connected cannot consist of one 128Mb and one 256Mb memory nor two 128Mb with one at 100MHz and the other at 133MHz. Below is a summary of the possible configurations: · Three 16-bit devices connecting a x36 interface to the DDR SDRAM · Four 16-bit devices connecting a x64 interface to the DDR SDRAM These various configurations determine the storage density of the SFC device. The storage density can range from a minimum of 128Mb to a maximum of 1Gb. Table 3 lists the possible ways to connect the DDR SDRAMs and the number of chipset solutions to obtain the various storage densities. · One 16-bit device connecting a x16 interface to the DDR SDRAM · One 32-bit device connecting a x32 interface to the DDR SDRAM TABLE 3 ­ TOTAL POSSIBLE EXTERNAL MEMORY CONFIGURATIONS Two Chip Solution(1) (2) Configuration 1, 2 1 x128Mb [4M x 32] Total memory: 128Mb 1 x 256Mb [8M x 32] Total memory: 256Mb 1 x 128Mb [8M x 16] Total memory: 128Mb 1 x 256Mb [16M x 16] Total memory: 256Mb Three Chip Solution(1) (2) Configurations 3, 4, 5 2 x 128Mb [4M x 32] Total memory: 256Mb 2 x 256Mb [8M x 32] Total memory: 512Mb 2 x 128Mb [8M x 16] Total memory: 256Mb 2 x 256Mb [16M x 16] Total memory: 512Mb Four Chip Solution(1) (2) Configuration 6 N/A Five Chip Solution(1) (2) Configuration 7 N/A N/A N/A 3 x 128Mb [8M x 16] Total memory: 384Mb 3 x 256Mb [16M x 16] Total memory: 768Mb 4 x 128Mb [8M x 16] Total memory: 512Mb 4 x 256Mb [16M x 16] Total memory: 1Gb NOTES: 1. The chip solution number includes the sequential flow-control device and external DDR SDRAM 2. See Figure 2a-2g for the 7 different configurations referenced in the table above. 12 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Below are the various chipset solution configurations available to the sequential flow-control device (see Figure 2a-2g). The external memory interface is designed to seamlessly connect one or more DDR SDRAMs. There are a number of pins on the DDR SDRAM that requires the user to tie to a specified state, which are listed in Table 4. DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Density: 256Mb or 512Mb 4 12 TABLE 4 ­ DDR SDRAM STATIC CONNECTIONS SDRAM Pin CKE IDT SFC 128Mb or 256Mb DDR SDRAM 32 36 Address Bus 12 Static Connections VCC CS DM Data Bus GND GND 6358 drw07 Figure 2d. Configuration 4 - Three Chip Solution DDR SDRAM: 128Mb [8Mb x 16] or 256Mb [16Mb x 16] Total Density: 256Mb or 512Mb DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Density: 128Mb or 256Mb 16 13 128Mb or 256Mb DDR SDRAM Data Bus 32 IDT SFC Address Bus 12 Data Bus IDT SFC 128Mb or 256Mb DDR SDRAM 16 32 Address Bus 13 6358 drw08 6358 drw04 Figure 2e(1). Configuration 5 - Three Chip Solution Figure 2a. Configuration 1 - Two Chip Solution DDR SDRAM: 128Mb [8Mb x 16] or 256Mb [16Mb x 16] Total Density: 384Mb or 768Mb DDR SDRAM: 128Mb [8Mb x 16] or 256Mb [16Mb x 16] Total Density: 128Mb or 256Mb 4 13 16 128Mb or 256Mb DDR SDRAM Data Bus 16 IDT SFC Address Bus 13 13 Data Bus IDT SFC 36 128Mb or 256Mb DDR SDRAM 16 Address Bus 13 6358 drw05 6358 drw09 (1) (1) Figure 2b . Configuration 2 - Two Chip Solution Figure 2f . Configuration 6 - Four Chip Solution DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Density: 256Mb or 512Mb DDR SDRAM: 128Mb [8Mb x 16] or 256Mb [16Mb x 16] Total Density: 512Mb or 1Gb 16 32 13 12 IDT SFC Data Bus 64 32 Address Bus 12 Data Bus 128Mb or 256Mb DDR SDRAM IDT SFC 64 16 Address Bus 128Mb or 256Mb DDR SDRAM 13 6358 drw06 6358 drw10 (1) Figure 2c. Configuration 3 - Three Chip Solution Figure 2g . Configuration 7 - Five Chip Solution NOTE: 1. · 12-bit address bus for 8Mb x16 · 13-bit address bus for 16Mb x16 13 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION MAXIMUM I/O OPERATING FREQUENCY The sequential flow-control (SFC) device is designed to operate at the maximum frequency of 133MHz. There are certain configurations however, that can increase or decrease the maximum frequency of the input and output ports. In some configurations (e.g. x24 I/O width), the I/O speeds can run up to 166MHz. The main factors that determine the usable memory are the I/O buswidth of the SFC, the density and number of DDR SDRAMs connected, and whether or not EDC is used. Table 5 lists the maximum frequency for the input and output ports of the SFC based on the various configurations. TABLE 5 ­ MAXIMUM I/O OPERATING FREQUENCY BASED ON VARIOUS CONFIGURATIONS SFC Bus-Width DDR SDRAM Freq (MHz) With EDC on or off Configurations 3, 7 Configurations 4, 6 Configurations 1, 5 Configuration 2 EDC on EDC off EDC on EDC off EDC on EDC off EDC on EDC off EDC on EDC off EDC on EDC off 66.67 100 100 133.33 133.33 166.67 166.67 166.67 166.67 166.67 166.67 166.67 50 50 66.67 66.67 100 100 133.33 133.33 166.67 166.67 166.67 166.67 33.33 50 50 66.67 66.67 100 100 133.33 133.33 166.67 166.67 166.67 25 25 33.33 33.33 50 66.67 66.67 66.67 100 133.33 133.33 133.33 133.33 x48 166.66 133.33 x24 166.66 133.33 x12 166.66 NOTE: 1. See Figure 2a-2g for a list of all configurations. ERROR DETECTION AND CORRECTION The optional Error Detection and Correction (EDC) feature implemented in this device is used to ensure data integrity between the DDR SDRAM and the Sequential Flow Control (SFC) device. The EDC will correct single bit errors that are accessed from the DDR SDRAM. Multiple bit errors are not detected nor corrected. The EDC circuit uses a syndrome bit generator to generate 8 syndrome bits that will detect whether there are single bit errors in each data word. The EDC is enabled using the MIC[2:0] pins. When the EDC is enabled, the dynamics of the total usable memory in the DDR SDRAM and SFC operating frequency will vary. Table 6 shows how to enable or disable the EDC feature for the various memory configurations. TABLE 6 ­ ERROR DETECTION AND CORRECTION CONFIGURATION External Memory Characteristic External Pins MIC0 x64 off EDC x64 on EDC x36 off EDC x36 on EDC x32 off EDC x32 on EDC x16 off EDC x16 on EDC 1 1 0 0 0 0 1 1 MIC1 MIC2 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 14 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CONNECTING THE DDR SDRAM The memory interface of the sequential flow-control device is designed for seamless connection to the DDR SDRAM. The output signal names should be connected directly to it's corresponding input signal on the DDR SDRAM. There are three signals on the DDR SDRAM that must be tied to a static state: CKE, CS, and DM. Figure 3 and 4 are some examples of the memory interface connections for various density configurations. For information on DDR SDRAM layout recommendations, please see IDT application note AN-423 AN-423. DDR SDRAM 2M x 16 x 4 128M Sequential Flow-Control Device CK CK CK CK DQS[3:0] WE DQS[3:0] WE 4 CAS CAS RAS DQ[31:0] VCC RAS 32 12 A[11:0] DQ[31:0] CKE DM[3:0] A[11:0] CS 6358 drw11 Figure 3. Memory Interface Connection (Single Chip) DDR SDRAM 8M x 32 256M Sequential Flow-Control Device CK CK CK CK DQS[7:0] WE 8 4 DQS[3:0] VCC WE CAS CAS RAS DQ[31:0] RAS A[11:0] 64 32 12 12 DQ[31:0] CKE DM[3:0] CS A[11:0] CK CK 4 DQS[3:0] WE VCC CAS CKE RAS 32 DQ[31:0] 12 DM[3:0] A[11:0] CS 6358 drw12 Figure 4. Memory Interface Connection (Two Chip) 15 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION SETTING THE MEMORY INTERFACE SIGNALS The configurations listed in Figure 2a-2g can be programmed into the sequential flow-control device by using the MIC[2:0], MTYPE[1:0], and MSPEED. For information about these signals, please refer to the Signal Description section. Table 7 is a list that shows the settings for the different configurations. TABLE 7 ­ MEMORY CONFIGURATIONS SETTINGS MIC[2:0] Configuration 1 Configuration 2 Configuration 3 Configuration 4 Configuration 5 Configuration 6 Configuration 7 MTYPE[1:0] MSPEED 000 - EDC Off 010 - EDC On 001 - EDC Off 011 - EDC On 111 - EDC Off 101 - EDC On 110 - EDC Off 100 - EDC On 000 - EDC Off 010 - EDC On 110 - EDC Off 100 - EDC On 111 - EDC Off 101 - EDC On 00 - (4Mb x 32) 10 - (8Mb x 32) 01 - (8Mb x 16) 11 - (16Mb x 16) 00 - (4Mb x 32) 10 - (8Mb x 32) 00 - (4Mb x 32) 10 - (8Mb x 32) 01 - (8Mb x 16) 11 - (16Mb x 16) 01 - (8Mb x 16) 11 - (16Mb x 16) 01 - (8Mb x 16) 11 - (16Mb x 16) 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 -166MHz 0 - 133MHz 1 - 166MHz 16 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTIONS TABLE 8 ­ DEVICE CONFIGURATION Signal Pins Static State MASTER RESET AND DEVICE CONFIGURATION During master reset the sequential flow-control configuration and settings are determined, this includes the following: 1. Synchronous or Asynchronous read and write port operation 2. Bus-width configuration 3. Default offset register values 4. IDT standard or first word fall through (FWFT) timing mode 5. Depth expansion in IDT standard or FWFT mode 6. I/O voltage set to 2.5V or 3.3V levels 7. JTAG function enabled or disabled 8. Configuration of the external memory interface The state of the configuration inputs during master reset will determine which of the above modes are selected. A master reset comprises of pulsing the MRS input pin from high to low for a period of time (tRS) with the configuration inputs held in their respective states. Table 8 summarizes the configuration modes available during master reset. These signals are described in detail in the signal description section. Configuration ASYR 0 1 Read port configured in asynchronous mode Read port configured in synchronous mode ASYW 0 1 Write port configured in asynchronous mode Write port configured in synchronous mode BW[3:0] - See Table 11 - Bus-Matching Configurations FSEL[1:0] 00 01 10 11 Programmable flag register offset value = 127 Programmable flag register offset value = 1,023 Programmable flag register offset value = 4,095 Programmable flag register offset value = 16,383 FWFT 0 1 IDT Standard mode FWFT mode IDEM 0 1 Depth expansion in FWFT mode Depth expansion in IDT Standard mode IOSEL 0 1 I/O voltage set to 2.5V levels I/O voltage set to 3.3V levels JSEL 0 1 JTAG function is disabled JTAG function is enabled MIC[2:0] - See Table 6 - EDC Configuration for description MSPEED 0 1 External memory interface clocks set to 133MHz External memory interface clocks set to 166MHz MTYPE[1:0] 00 01 10 11 External memory configuration is: 4M x 32 External memory configuration is: 8M x 32 External memory configuration is: 8M x 16 External memory configuration is: 16M x 16 PROGRAMMABLE ALMOST EMPTY/ALMOST FULL FLAGS The SFC has a set of programmable flags (PAE/PAF) that can be used as an early indicator for the empty and full boundary conditions. These flags have an offset value (n, m) that will determine the almost empty and almost full boundary conditions. There are four default offset values selectable during master reset, these values are shown in Table 9, Default Programmable Flag Offsets. Offset values can also be programmed using the serial programming pins (SCLK, SI, and SWEN). The SFC has two internal offset registers that are used to store the specific offset value, one for the PAE and one for the PAF. The total number of bits (shown in Table 10, Number of Bits Required for Offset Registers) must be completely programmed to the offset registers. The serial programming sequence begins by writing data into the PAE register followed by the PAF register. See Figure 29, Serial Loading of Programmable Flag Registers for the associated timing diagram. The total number of bits required to program the offset registers will vary depending on the type of configuration that is shown in Figure 2a-2g, the bus-width selected, and whether EDC is used. The values of n, m are used such that the PAE will become active (LOW) when there are at least one to n words written in the device. Similarly PAF will become active (LOW) when there are at least D ­ M words or more in the device, where D is the density of the SFC. TABLE 9­ DEFAULT PROGRAMMABLE FLAG OFFSETS FSEL1 0 0 1 1 FSEL0 0 1 0 1 Offset n,m 127 1,023 4,095 16,383 TABLE 10­ NUMBER OF BITS REQUIRED FOR OFFSET REGISTERS Write Port Bus-Width Configuration 1 (128Mb) Configuration 1 (256Mb) Configuration 2 (128Mb) Configuration 2 (256Mb) Configuration 3 (256Mb) Configuration 3 (512Mb) Configuration 4 (256Mb) Configuration 4 (512Mb) Configuration 5 (256Mb) Configuration 5 (512Mb) Configuration 6 (384Mb) Configuration 6 (768Mb) Configuration 7 (512Mb) Configuration 7 (1Gb) x48 EDC On 21 22 21 22 22 23 22 23 22 23 23 24 23 24 x24 EDC Off 22 23 22 23 23 24 22 23 23 24 23 24 24 25 EDC On 22 23 22 23 23 24 23 24 23 24 24 25 24 25 17 x12 EDC Off 23 24 23 24 24 25 23 24 24 25 24 25 25 26 EDC On 23 24 23 24 24 25 24 25 24 25 25 26 25 26 EDC Off 24 25 24 25 25 26 24 25 25 26 25 26 26 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION ASYNCHRONOUS READ (ASYR) The read port can be configured for either synchronous or asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then asynchronous operation of the read port will be selected. During asynchronous operation of the read port the RCLK input becomes RD input, this is the asynchronous read strobe input. A rising edge on RD will read data from the SFC via the output register and data output port. (REN must be tied LOW during asynchronous operation of the read port). The OE input provides three-state control of the Qn output bus, in an asynchronous manner. When the read port is configured for asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is asynchronous. The Empty Flag (EF) and programmable almost empty flag (PAF) operates in an asynchronous manner, that is, the empty flag and PAE will be updated based on both a read operation and a write operation. Refer to Figure 23, Asynchronous Read and PAF flag ­ IDT Standard mode, Figure 26, Asynchronous Empty Boundary ­ IDT Standard mode, Figure 27, Asynchronous Full Boundary ­ IDT Standard mode, and Figure 28, Asynchronous Read and PAE flag ­ IDT Standard mode, for relevant timing and operational waveforms. SIGNAL DESCRIPTIONS INPUTS DATA INPUTS (D0 - D47) Data inputs for 48-bit wide data (D0 - D47), data inputs for 24-bit wide data (D0 - D23) or data inputs for 12-bit wide data (D0 - D11). CONTROLS MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is toggled LOW then HIGH. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH. If FWFT is LOW during Master Reset then the IDT Standard mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW. All configuration control signals must be set prior to the LOW to HIGH transition of MRS. During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is an asynchronous function. See Figure 6, Master Reset and Initialization, for the relevant timing diagram. FIRST WORD FALL THROUGH (FWFT) During Master Reset, the state of the FWFT input determines whether the device will operate in IDT standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the SFC. It also uses the Full Flag function (FF) to indicate whether or not the SFC has any free space for writing. In IDT Standard mode, every word read from the SFC, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the SFC has any free space for writing. In the FWFT mode, the first word written to an empty SFC goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is toggled LOW then HIGH. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, and PAF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. See Figure 7, Partial Reset, for the relevant timing diagram. WRITE STROBE AND WRITE CLOCK (WR/WCLK) If synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK. A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/IR, and PAF flags will not be updated. The Write and Read Clocks can either be independent or coincident. If asynchronous operation has been selected this input is WR (write strobe). Data is asynchronously written into the SFC via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be LOW. ASYNCHRONOUS WRITE (ASYW) The write port can be configured for either synchronous or asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then asynchronous operation of the write port will be selected. During asynchronous operation of the write port the WCLK input becomes WR input, this is the asynchronous write strobe input. A rising edge on WR will write data present on the data inputs into the sequential flow-control device (SFC). (WEN must be LOW when using the write port in asynchronous mode). When the write port is configured for asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissable. The full flag (FF) and programmable almost full flag (PAF) operates in an asynchronous manner, that is, the full flag and PAF flag will be updated based in both a write operation and read operation. Note, if asynchronous mode is selected, FWFT is not permissible. Refer to Figure 24, Asynchronous Write and PAE flag ­ IDT Standard mode and Figure 25, Asynchronous Write and PAF flag ­ IDT Standard mode for relevant timing and operational waveforms. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the SFC on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the SFC. 18 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle. To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the SFC is full in either FWFT or IDT Standard mode. If asynchronous operation of the write port has been selected, then WEN must be held active. input that can place the output bus Qn, into High-Impedance. During Reset the RCS input can be HIGH or LOW, it has no effect on the Qn outputs. READ CHIP SELECT (RCS) The Read Chip Select input provides synchronous control of the Read output port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only input that provides High-Impedance control of the Qn outputs. If OE is LOW the Qn data outputs will be Low-Impedance regardless of RCS until the first rising edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs will go to HighImpedance. The RCS input does not effect the operation of the flags. For example, when the first word is written to an empty SFC, the EF will still go from LOW to HIGH based on a rising edge of RCLK, regardless of the state of the RCS input. Also, when operating the SFC in FWFT mode the first word written to an empty SFC will still be clocked through to the output register based on RCLK, regardless of the state of RCS. For this reason the user must take care when a data word is written to an empty SFC in FWFT mode. If RCS is disabled when an empty SFC is written into, the first word will fall through to the output register, but will not be available on the Qn outputs which are in HIGH-Z. The user must take RCS active LOW to access this first word, place the output bus in LOW-Z. REN must remain disabled HIGH for at least one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and REN active LOW, will read out the next word. Care must be taken so as not to lose the first word written to an empty SFC when RCS is HIGH. See Figure 15 for Read Chip Select. If asynchronous operation of the Read port has been selected, then RCS must be held active, (tied LOW). OE provides three-state control of Qn. READ STROBE AND READ CLOCK (RD/RCLK) If synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR and PAE flags will not be updated. The Write and Read Clocks can be independent or coincident. If asynchronous operation has been selected this input is RD (Read Strobe). Data is asynchronously read from the SFC whenever there is a rising edge on RD. In this mode the REN and RCS inputs must be tied LOW. The OE input is used to provide asynchronous control of the three-state Qn outputs. WRITE CHIP SELECT (WCS) The WCS disables all Write data operations (data only) if it is held HIGH. To perform normal operations on the write port, the WCS must be enabled, held LOW. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and then no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty cache, must be requested using REN provided that RCS is LOW. When the last word has been read from the SFC, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the SFC is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. Both RCS and REN must be active, LOW for data to be read out on the rising edge of RCLK. In the FWFT mode, the first word written to an empty SFC automatically goes to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW after the first write. REN and RCS do not need to be asserted LOW for the First Word to fall through to the output register. In order to access all other words, a read must be executed using REN and RCS. The RCLK LOW-to-HIGH transition after the last word has been read from the SFC, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW;RCS = LOW), inhibiting further read operations. REN is ignored when the SFC is empty. If asynchronous operation of the Read port has been selected, then REN must be held active, (LOW). BUS-MATCHING (BM[3:0]) These pins are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. All flags will operate on the word/byte size boundary as defined by the selection of bus width. See Figures 17-20 for Bus-Matching Configurations. See Table 11, BusMatching Configurations for the available configurations. TABLE 11 ­ BUS-MATCHINGS BM0 BM1 BM2 BM3 Read Bus Width Write Bus Width 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 x48 x24 x12 x48 x48 x24 x12 x24 x12 x48 x48 x48 x24 x12 x24 x24 x12 x12 FLAG SELECT (FSEL[1:0]) During master reset, these inputs will select one of four default values for the programmable flags PAE and PAF. The selected value (listed in Table 12 MTYPE[1:0] Configurations) will apply to both PAE and PAF offset. OUTPUT ENABLE (OE) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. During Master or a Partial Reset the OE is the only 19 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION MEMORY CONFIGURATION (MIC[2:0]) These signals enable the EDC feature of the device. See Table 6, Error Detection and Correction (EDC) for more information. modes. See Figure 29, Serial Loading of Programmable Flag Registers, for the timing diagram. I/O VDDQ SELECT (IOSEL) This input determines whether the inputs and outputs will tolerate a 2.5V or 3.3V voltage signals. If IOSEL is HIGH, then all I/Os will be 3.3V levels. If IOSEL is LOW, then all I/Os will be 2.5V levels. MEMORY SPEED (MSPEED) This pin is used to determine the memory interface clock speed (CK and CK) for the external memory used. If MSPEED is HIGH, external memory CK and CK will be operating at 166MHz. If MSPEED is LOW, then the external memory CK and CK will be operating at 133MHz. JTAG SELECT (JSEL) This input determines whether the JTAG port will be activated or deactivated. If JSEL is HIGH, then the JTAG port is activated and the associated JTAG pins (TCK, TDI, TDO, TMS) are used for the boundary-scan function. If JSEL is LOW, the JTAG port is disabled and the serial programming pins (SCLK, SI, SO) will be used to program and read the offset register values for PAE and PAF. See Figure 29 and 30, Serial Loading and Reading of Programmable Registers for information on how to program the registers. MASTER CLOCK (MCLK) 33MHz reference clock used to generate CK and CK for external memory interface. MEMORY TYPE (MTYPE[1:0]) These signals select the density configuration of the external DDR SDRAM used. See Table 12, for selection of the memory density configuration. OUTPUTS TABLE 12 ­ MTYPE[1:0] CONFIGURATIONS FULL FLAG/INPUT READY (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the SFC is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the SFC is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW See Figure 12, Full Boundary - IDT Standard Mode, for the relevant timing information. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH see Figure 9 Write First Word Cycles - FWFT Mode, for the relevant timing information. The IR status not only measures the contents of the SFC memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to de-assert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. Density Configurations 4M x 32 MTYPE0 MTYPE1 8M x 32 8M x 16 16M x 16 0 0 0 1 1 0 1 1 DEPTH EXPANSION MODE SELECT (IDEM) This select pin is used for depth expansion configuration in IDT Standard mode. If this pin is tied HIGH, then the FF/IR signal will be inverted to provide a seamless depth expansion interface. If this pin is tied LOW, the depth expansion in IDT Standard mode will be deactivated. For details on depth expansion configuration, see Figure 34, Depth Expansion Configuration in IDT Standard Mode and Figure 35, Depth Expansion Configuration in FWFT Mode. SERIAL READ ENABLE (SREN) The serial read enable input is an enable used for reading the value of the programmable offset registers. By setting the JSEL pin to LOW, the serial data output (SO) and serial clock (SCLK) signals can be used with SREN to program the offset registers. When SREN is LOW, data at the SO can be read from the offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial read enable is HIGH, the reading of the offset registers will stop. SREN must be kept LOW in order to read the entire contents of the scan out register. If at any point SREN is toggled HIGH, the read pointer of the offset registers will reset to the first location. The next time SREN is enabled the first contents in the offset register will be read back. Serial read enable functions the same way in both IDT Standard and FWFT modes. See Figure 30, Reading of Programmable Flag Registers, for the timing diagram. EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the SFC is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the SFC is not empty. Figure 10, Empty Boundary ­ IDT Standard Mode for the relevant timing information. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty SFC appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the SFC to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 11, Empty Boundary (FWFT Mode), for the relevant timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered output. SERIAL WRITE ENABLE (SWEN) The serial write enable input is an enable used for serial programming of the programmable offset registers. By setting the JSEL pin to LOW, the serial input (SI) and serial clock (SCLK) signals can be used with SWEN to program the offset registers. When SWEN is LOW, data at the SI input are loaded into the offset register, one bit for each LOW-to-HIGH transition of SCLK. When SWEN is HIGH, the offset registers retain the previous settings and no offsets are loaded. Serial write enable functions the same way in both Standard IDT and FWFT PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the SFC reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D - m) words are written 20 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES to the SFC. See Figure 22, Synchronous PAF Flag - IDT Standard Mode and FWFT Mode, for the relevant timing information. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK. MEMORY BANK ADDRESS INPUT BIT (BA[1:0]) These signals are to be connected to the external DDR SDRAM's bank address input bits. MEMORY COLUMN ADDRESS STROBE (CAS) These signals are to be connected to the external DDR SDRAM's column address strobe input. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the SFC reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the SFC. The offset "n" is the empty offset value. The default setting for this value is in Table 8, Device Configuration. In FWFT mode, the PAE will go LOW when there are n+1 words or less in the SFC. See Figure 21, Synchronous PAE Flag - IDT Standard Mode and FWFT Mode, for the relevant timing information. If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE configuration is selected, the PAE is updated on the rising edge of RCLK. MEMORY ADDRESS BUS (A[12:0]) These signals are to be connected to the external DDR SDRAM's address bus. MEMORY WRITE ENABLE (WE) These signals are to be connected to the external DDR SDRAM's write enable. MEMORY ROW ADDRESS STROBE (RAS) These signals are to be connected to the external DDR SDRAM's row address strobe input. DATA OUTPUTS (Q0-Q47 Q0-Q47) (Q0-Q47 Q0-Q47) are data outputs for 48-bit wide data, (Q0 - Q23) are data outputs for 24-bit wide data or (Q0-Q11 Q0-Q11) are data outputs for 12-bit wide data. BI-DIRECTIONAL I/O MEMORY DATA INPUTS/OUTPUTS DQ[63:0] These signals are to be connected to the external DDR SDRAM's data input bus. MEMORY CLOCK OUTPUT (CK) These signals are to be connected to the external DDR SDRAM's clock input. MEMORY DATA STROBE OUTPUT DQS[7:0] These signals are to be connected to the external DDR SDRAM's data strobe inputs. MEMORY CLOCK OUTPUT INVERTED (CK) These signals are to be connected to the external DDR SDRAM's differential clock input. 21 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION ABSOLUTE MAXIMUM RATINGS CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol VTERM Rating Terminal Voltage with respect to GND Com'l & Ind'l ­0.5 to +3.6(2) Unit V ­55 to +125 °C 150 °C ­50 to +50 mA TSTG Storage Temperature TJMAX Maximum Junction Temp. IOUT DC Output Current Parameter(1) Symbol CIN (2,3) Conditions Max. (3) Input Capacitance VIN = 0V 10 pF Output Capacitance COUT(1,2) VOUT = 0V 10 pF NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested. 3. CIN for Vref is 20pF. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Compliant with JEDEC JESD8-5. VCC terminal only. PACKAGE THERMAL DATA Symbol JC JA Parameter Industrial/ Commercial Junction to case thermal resistance 3.8 Junction to air thermal resistance MSL Unit C/W C/W airflow @ 0m/s @ 1m/s @ 2m/s @ 3m/s @ 4m/s @ 5m/s Moisture sensitivity level 27.4 22.8 20.3 19.5 18.2 17.8 3 RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol VCC Supply Voltage Min. 2.375 Typ. 2.5 Max. 2.625 Unit V VDDQ Output Rail Voltage for I/Os 2.375 - 3.45 V GND Supply Ground 0 0 0 V VIH Input High Voltage @ 3.3V @ 2.5V 2.0 1.7 - - 5.5 3.45 V V VIL Input Low Voltage @ 3.3V @ 2.5V - -0.3 - - 0.8 0.7 V V 1.15 1.25 1.35 V 0 - 70 -40 - 85 °C °C VREF Voltage Reference Input TA Operating Temperature (Commercial) TA Operating Temperature (Industrial) 22 Unit IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C) Symbol ILI(1) Input leakage current Parameter ILO(2) Output leakage current VOH1 Read/Write interface output logic "1" voltage VOH2 Memory interface output logic "1" voltage VOL1 Read/Write interface output logic "0" voltage VOL2 IOH1 Min. -10 Typ. - Max. 10 Unit mA -10 - 10 mA VDDQ ­ 0.4 VDDQ ­ 0.4 - - - - V V 1.46 - 2.8 V - - - - 0.4 0.4 V V Memory interface output logic "0" voltage - - 1.04 V Read/Write interface output high current (source current) -8 - - mA IOH2 Read/Write interface output low current (sink current) -16 - - mA IOL1 Read/Write interface output low current (sink current) 8 - - mA IOL2 Memory interface output low current (sink current) 16 - - mA ICC(5) Active VCC current - 380 1300 mA ISB Standby VCC current - - 50 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). 4. RCLK and WCLK toggle at 20MHz and data inputs switch at 10MHz. 5. Typical values represent frequency = 0MHz. Maximum values represent frequency = 166MHz. 6. This is the formula used for calculating ICC: P = C x V2 x f x D x BW ICC = P V f C V D BW = = = = = operating frequency capacitive load VCC voltage duty cycle bus width 23 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION 2.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC TEST LOADS GND to 2.5V 1ns VCC/2 VDDQ/2 VDDQ/2 50 I/O Z0 = 50 6358 drw13 Figure 5a. AC Test Load 3.3V AC TEST CONDITIONS GND to 3.0V 3ns 1.5V 1.5V 6 tCD (Typical, ns) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 5 4 3 2 1 20 30 50 80 100 Capacitance (pF) 200 6358 drw13a Figure 5b. Lumped Capacitive Load, Typical Derating 24 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) SYNCHRONOUS TIMING (Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C) Commercial IDT72T6480L7-5 IDT72T6480L7-5 Commercial IDT72T6480L7-5 IDT72T6480L7-5 Com'l & Ind'l(2) IDT72T6480L10 IDT72T6480L10 Min. - 1 7.5 3.5 3.5 2.5 0.5 2.5 0.5 10 15 10 20 - 1 1 32 29.4 0.45 0.45 - 100 45 45 15 5 5 5 - - - - - 5 7 2.5 0.5 - 128 - 7.8 - 0.45 - 0.45 Min. - 1 10 4.5 4.5 3.5 0.5 3.5 0.5 10 15 10 20 - 1 1 32 29.4 0.45 0.45 - 100 45 45 15 5 5 5 - - - - - 7 10 3.5 0.5 - 128 - 7.8 - 0.45 - 0.45 (x24 or x12 I/O width only)(3) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSU tRSH tPL tRSF tOHZ tOE fMC tMCYC tMCKH tMCKL fSC tSCLK tSCLKH tSCLKL tSDS tSDH tSENS tSENH tASO tWFFs tREFs tPAFs tPAEs tSKEW1 tSKEW2 tWCSS tWCSH fC1 fC2 tCK1 tCK2 tCKH1 tCKH2 tCKL1 tCKL2 Parameter Synchronous Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output Output enable to High-Z Output Enable Valid Master Clock Cycle Frequency Master Clock Cycle Time Master Clock Cycle HIGH Master Clock Cycle LOW Serial Clock Cycle Frequency Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data Setup Serial Data Hold Serial Enable Setup Serial Enable Hold Serial Output Data Access Time Write Clock to Synchronous FF/IR Read Clock to Synchronous EF/OR WCLK to Synchronous PAF RCLK to Synchronous PAE Skew time between RCLK & WCLK for EF/OR and FF/IR in SDR Skew time between RCLK and WCLK for PAE/PAF WCS Setup Time WCS Hold Time Memory Clock Cycle Frequency at 166MHz Memory Clock Cycle Frequency at 133MHz Memory Clock Cycle Time at 166MHz Memory Clock Cycle Time at 133MHz Memory Clock Cycle HIGH at 166MHz Memory Clock Cycle HIGH at 133MHz Memory Clock Cycle LOW at 166MHz Memory Clock Cycle LOW at 133MHz Min. - 1 6 2.7 2.7 2 0.5 2 0.5 10 15 10 20 - 1 1 32 29.4 0.45 0.45 - 100 45 45 15 5 5 5 - - - - - 4 5 2 0.5 160 128 6.2 7.8 0.45 0.45 0.45 0.45 Max. 166 4 - - - - - - - - - - - 15 4 4 34 31.3 0.55 0.55 10 - - - - - - - 20 4 4 4 4 - - - - 170 136 5.9 7.3 0.55 0.55 0.55 0.55 Max. 133 5 - - - - - - - - - - - 15 5 5 34 31.3 0.55 0.55 10 - - - - - - - 20 5 5 5 5 - - - - - 136 - 7.3 - 0.55 - 0.55 NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order. 3. To achieve 166MHz read and write port operation, the input and/or output bus must be configured to x24 or x18. 25 Max. 100 6.5 - - - - - - - - - - - 15 6.5 6.5 34 31.3 0.55 0.55 10 - - - - - - - 20 6.5 6.5 6.5 6.5 - - - - - 136 - 7.3 - 0.55 - 0.55 Unit MHz ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns MHz ns tMCYC tMCYC MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns tCK1 tCK2 tCK1 tCK2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION AC ELECTRICAL CHARACTERISTICS ASYNCHRONOUS TIMING (Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C) Commercial Parameter Asynchronous Clock Cycle Frequency Data Access Time Cycle Time Cycle High Time Cycle Low Time Rising Edge to FF Rising Edge to EF Rising Edge to PAF Rising Edge to PAE Read Pulse after EF HIGH Com'l & Ind'l(2) IDT72T6480L7-5 IDT72T6480L7-5 (x24 or x12 I/O width only)(3) Symbol fA tAa tCYC tCYCH tCYCL tFFa tEFa tPAFa tPAEa tRPE Commercial IDT72T6480L7-5 IDT72T6480L7-5 IDT72T6480L10 IDT72T6480L10 Min. - 0.6 10 4.5 4.5 - - - - 8 Max. 100 8 - - - 8 8 8 8 - Min. - 0.6 12 5 5 - - - - 10 Max. 83 10 - - - 10 10 10 10 - Min. - 1 20 8 8 - - - - 14 NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order. 26 Max. 50 6.4 - - - 14 14 14 14 - Unit MHz ns ns ns ns ns ns ns ns ns IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tRS MRS tRSU tRH tRSU tRH tRSU tRH tRSU tRH REN WEN SREN SWEN tRSF EF If IDT mode is selected tRSF OR If FWFT mode is selected tPL FF If IDT mode is selected tPL IR If FWFT mode is selected tPL CK The clock may not be locked to the required operation frequency before tPL tPL CK The clock may not be locked to the required operation frequency before tPL If OE = HIGH Q[47:0] tRSU FWFT FWFT Mode If OE = LOW IDT Standard Mode tRSU ASYR Synchronous read port selected Asynchronous read port selected tRSU ASYW Synchronous write port selected Asynchronous write port selected tRSU IOSEL 3.3V I/O voltage selected 2.5V I/O voltage selected tRSF PAF tRSF PAE tRSU IDEM Depth Expansion in IDT Standard Mode Depth Expansion in FWFT Standard Mode 6358 drw14 NOTE: 1. For other signals that are latched during master reset, refer to Master Reset and Device Configuration section. Symbol tRS tRSU tRSH tPL tRSF Parameter Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output Min. 200 15 10 20 - Max. - - - - 15 Unit ns ns ns µs ns Figure 6. Master Reset and Initialization 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION tRS PRS tRSU tRH tRSU tRH tRSU tRH tRSU tRH REN WEN SREN SWEN tRSF EF If IDT mode is selected OR If FWFT mode is selected tRSF FF tRSF If IDT mode is selected tRSF IR If FWFT mode is selected If OE = HIGH Q[47:0] If OE = LOW tRSF PAF tRSF PAE 6358 drw15 Symbol tRS tRSU tRSH tPL tRSF Parameter Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output Min. 200 15 10 20 - Max. - - - - 15 Unit ns ns ns µs ns Figure 7. Partial Reset 28 IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES WCLK tENS tENH WEN tENH tENS D[47:0] Word 0 Word 1 Word 2 tSKEW1 RCLK 1 2 tENH tENS REN tREFs tREFs EF tA Q[47:0] tA tA Word 0 Word 1 Word 2 6358 drw16 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 8. Write First Word Cycles - IDT Standard Mode WCLK tENS tENH WEN tENS D[47:0] tENH Word 0 Word 1 Word 2 tSKEW1 RCLK 1 2 3 tENH tENS REN tREFs tREFs OR tA Q[47:0] tA tA Word 0 Word 1 Word 2 6358 drw17 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH. Figure 9. Write First Word Cycles - FWFT Mode 6ns 7-5ns 10ns (x24 or x12 I/O only) Symbol tSENS tSENH tA tSKEW1 tREFs Parameter Serial Enable Setup Serial Enable Hold Data Access Time Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR Read Clock to Synchronous EF/OR Min. 5 5 1 4 Max. - - 4 - Min. 5 5 1 5 Max. - - 5 - Min. 5 5 1 7 Max. - - 6.5 - Unit ns ns ns ns - 4 - 5 - 6.5 ns 29 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION tCLK tCLKH 1 RCLK tENS tCLKL 2 tENH tENH tENS REN tENH tENS NO OPERATION NO OPERATION tREF tREF tREF EF tA tA Last Word Q[47:0] tA Word 0 Last Word Word 1 tOLZ tOHZ tOE OE (1) tSKEW1 WCLK tENS tENH tENH tENS WEN tDH tDS Word 0 D[47:0] tDS tDH Word 1 6358 drw18 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 10. Empty Boundary - IDT Standard Mode RCLK 1 2 3 REN tREFs tREFs OR tA Q[47:0] Last Word - 3 tA Last Word - 2 tA tA Last Word Last Word - 1 Word 0 tSKEW1 WCLK tENS tENH WEN tDS D[47:0] tDH Word 0 6358 drw19 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH. Figure 11. Empty Boundary - FWFT Mode 6ns 7-5ns 10ns (x24 or x12 I/O only) Symbol tCLK tCLKH tCLKL tDS tDH tENS tENH tA tREFs tSKEW1 Parameter Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Read Clock to Synchronous EF/OR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 30 Min. 6 2.7 2.7 2 0.5 2 0.5 1 - 4 Max. - - - - - - - 4 4 - Min. 7.5 3.5 3.5 2.5 0.5 2.5 0.5 1 - 5 Max. - - - - - - - 5 5 - Min. 10 4.5 4.5 3.5 0.5 3.5 0.5 1 - 7 Max. - - - - - - - 6.5 6.5 - Unit ns ns ns ns ns ns ns ns ns ns IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 WCLK tENS 2 tSKEW1 tENH WEN tDH tDS D[47:0] WD-1 WD tWFFs tWFFs FF RCLK tENS REN tA Q[47:0] tA Previous Word in Register Word 0 tA Word 1 tA Word 2 Word 3 6358 drw20 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle (plus tWFFs). If tSKEW1 is not met, then FF de-assertion may be delayed one extra WCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 12. Full Boundary - IDT Standard Mode 1 WCLK tENS 2 tSKEW1 tENH WEN tDS D[47:0] WD-1 tDH WD tWFFs tWFFs IR RCLK tENS REN tA Q[47:0] tA Word 0 Word 1 tA Word 2 tA Word 3 Word 4 6358 drw21 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH. Figure 13. Full Boundary - FWFT Mode 6ns 7-5ns 10ns (x24 or x12 I/O only) Symbol tDS tDH tENS tENH tA tWFFs tSKEW1 Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Write Clock to Synchronous FF/IR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 31 Min. 2 0.5 2 0.5 1 - 4 Max. - - - - 4 4 - Min. 2.5 0.5 2.5 0.5 1 - 5 Max. - - - - 5 5 - Min. 3.5 0.5 3.5 0.5 1 - 7 Max. - - - - 6.5 6.5 - Unit ns ns ns ns ns ns ns COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION RCLK REN tA Q[47:0] Word 1 tA Word 2 tA Word 3 Word 4 Word 4 tOHZ tOE OE 6358 drw22 NOTE: 1. Settings: RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 14. Output Enable RCLK tENH REN tA Q[47:0] Word 1 tA Word 2 Word 3 tRCSHZ tRCSLZ tA tA Word 4 Word 4 tENS tENS RCS 6358 drw23 NOTE: 1. Settings: OE = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 15. Read Chip Select WCLK tENS WEN tDS D[47:0] Word 0 tDH Word 1 Word 2 tWCSS tWCSH WCS 6358 drw24 NOTE: 1. Settings: BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 16. Write Chip Select 6ns 7-5ns 10ns (x24 or x12 I/O only) Symbol tDS tDH tENS tENH tA tOHZ tOE tWCSS tWCSH Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Output enable to High-Z Output Enable Valid WCS Setup Time WCS Hold Time Min. 2 0.5 2 0.5 1 1 1 2 0.5 32 Max. - - - - 4 4 4 - - Min. 2.5 0.5 2.5 0.5 1 1 1 2.5 0.5 Max. - - - - 5 5 5 - - Min. 3.5 0.5 3.5 0.5 1 1 1 3.5 0.5 Max. - - - - 6.5 6.5 6.5 - - Unit ns ns ns ns ns ns ns ns ns IDT72T6480 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES WCLK tENS tENH WEN tDS D[47:0] tDH Word 0 tSKEW1 RCLK 1 2 tENS tENH REN tREFs tREFs EF tA tA Previous Word in Register D[47:24] Q[23:0] Word 0 D[23:0] Word 0 D[47:24] 6358 drw25 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1011, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode WCLK tENS tENH WEN tDS D[47:0] tDH Word 0 tSKEW1 RCLK 1 2 tENS REN tREFS tREFS EF tA Q[11:0] tA Word 0 D[11:0] Previous Word in Register D[47:36] tA Word 0 D[23:12] tA Word 0 D[35:24] Word 0 D[47:36] 6358 drw26 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1111, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode 6ns