IDT71256SA ID71256SA 144-BIT DSC-2948/3 SO28-5 P28-2 P28-1 71256SA12 71256SA15 - Datasheet Archive

 

CMOS STATIC RAM 256K (32K x 8-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: · 32K x 8 advanced high-speed

 

IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: · 32K x 8 advanced high-speed CMOS static RAM · Equal access and cycle times - Commercial: 12/15/20/25ns · One Chip Select plus one Output Enable pin · Bidirectional data inputs and outputs directly TTL-compatible · Low power consumption via chip deselect · Available in 28-pin 300 and 600 mil Plastic DIP and 300 mil Plastic SOJ The ID71256SA ID71256SA is a 262,144-bit high-speed Static RAM organized as 32K x 8. It is fabricated using IDT's highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71256SA IDT71256SA has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71256SA IDT71256SA are TTLcompatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA IDT71256SA is packaged in 28-pin 300 and 600 mil Plastic DIP and 28-pin 300 mil Plastic SOJ. FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 ADDRESS 262,144-BIT 144-BIT MEMORY ARRAY DECODER I/O 0 ­ I/O 7 8 8 I/O CONTROL 2948 drw 01 CS WE OE CONTROL LOGIC The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. MAY 1996 7.2 DSC-2948/3 DSC-2948/3 1 IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS Symbol (2) Rating Com'l. Unit ­0.5 to +7.0 V VTERM TA A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 27 26 4 25 24 °C Temperature Under Bias ­55 to +125 °C TSTG Storage Temperature ­55 to +125 °C PT Power Dissipation 1.0 W IOUT A13 A8 A9 A11 0 to +70 DC Output Current 50 mA WE 3 Operating Temperature TBIAS VCC 2 Terminal Voltage with Respect to GND 5 6 7 23 22 SO28-5 SO28-5 P28-2 P28-2 P28-1 P28-1 OE 21 A10 20 CS 10 19 11 18 12 17 13 16 14 15 I/O7 I/O6 I/O5 I/O4 I/O3 8 9 NOTES: 2948 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 2948 drw 02 DIP/SOJ TOP VIEW CAPACITANCE (TA = +25°C, f = 1.0MHz, SOJ package) Symbol CIN Symbol Parameter Min. Typ. Max. Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 - VCC+0.5 I/O Capacitance Conditions Max. Unit VIN = 3dV 11 pF VOUT = 3dV 11 pF NOTE: 2948 tbl 03 1. This parameter is guaranteed by device characterization, but not production tested. Unit VCC Input Capacitance CI/O RECOMMENDED DC OPERATING CONDITIONS Parameter(1) V TRUTH TABLE(1,2) Input Low Voltage ­0.5(1) - 0.8 OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Outputs Disabled H VIL CS X X High-Z Deselected - Standby (ISB) X X High-Z Deselected - Standby (ISB1) V NOTE: 2948 tbl 01 1. VIL (min.) = ­1.5V for pulse width less than 10ns, once per cycle. VHC(3) Function NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC ­0.2V. 3. Other inputs VHC or VLC. 2948 tbl 04 DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% IDT71256SA IDT71256SA Symbol Parameter Test Condition Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC - 5 µA |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC - 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. - 0.4 V VOH Output High Voltage IOH = ­4mA, VCC = Min. 2.4 - V 2948 tbl 05 7.2 2 IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC­0.2V) Symbol Parameter 71256SA12 71256SA12 71256SA15 71256SA15 71256SA20 71256SA20 71256SA25 71256SA25 Unit ICC Dynamic Operating Current (2) CS VIL, Outputs Open, VCC = Max., f = fMAX 160 150 145 145 mA ISB Standby Power Supply Current (TTL Level) (2) CS VIH, Outputs Open, VCC = Max., f = fMAX 50 40 40 40 mA ISB1 Standby Power Supply Current (CMOS Level) (2) CS VHC, Outputs Open, VCC = Max., f = 0 VIN VLC or VIN VHC 15 15 15 15 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 2948 tbl 06 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2948 tbl 07 5V 5V 480 480 DATA OUT 30pF* DATA OUT 255 5pF* 255 2948 drw 03 2948 drw 04 *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load 7.2 3 IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) 71256SA12 71256SA12 Symbol Parameter 71256SA15 71256SA15 71256SA20 71256SA20 71256SA25 71256SA25 Min. Max. Min. Max. Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 - 15 - 20 - 25 - ns tAA Address Access Time - 12 - 15 - 20 - 25 ns tACS Chip Select Access Time - 12 - 15 - 20 - 25 ns (1) tCLZ Chip Select to Output in Low-Z 4 - 4 - 4 - 4 - ns tCHZ(1) Chip Deselect to Output in High-Z 0 6 0 7 0 10 0 11 ns tOE Output Enable to Output Valid - 6 - 7 - 10 - 11 ns (1) Output Enable to Output in Low-Z 0 - 0 - 0 - 0 - ns tOHZ(1) Output Disable to Output in High-Z 0 6 0 6 0 8 0 10 ns tOH Output Hold from Address Change 3 - 3 - 3 - 3 - ns tOLZ tPU (1) Chip Select to Power Up Time 0 - 0 - 0 - 0 - ns Chip Deselect to Power Down Time tPD(1) - 12 - 15 - 20 - 25 ns Write Cycle tWC Write Cycle Time 12 - 15 - 20 - 25 - ns tAW Address Valid to End of Write 9 - 10 - 15 - 20 - ns tCW Chip Select to End of Write 9 - 10 - 15 - 20 - ns tAS Address Set-up Time 0 - 0 - 0 - 0 - ns tWP Write Pulse Width 9 - 10 - 15 - 20 - ns tWR Write Recovery Time 0 - 0 - 0 - 0 - ns tDW Data Valid to End of Write 6 - 7 - 11 - 13 - ns tDH Data Hold Time 0 - 0 - 0 - 0 - ns tOW(1) Output Active from End of Write 4 - 4 - 4 - 4 - ns tWHZ(1) Write Enable to Output in High-Z 0 6 0 6 0 10 0 11 ns NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2948 tbl 08 TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS1 CS2 tACS tCLZ (3) (5) tOHZ tCHZ HIGH IMPEDANCE DATAOUT VCC SUPPLY CURRENT (5) ICC (5) (5) DATA OUT VALID tPD tPU ISB 2948 drw 05 7.2 4 IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID 2948 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5) tWC ADDRESS tAW CS tWP(3) tAS tWR WE tWHZ DATAOUT (6) tOW (6) HIGH IMPEDANCE (4) tDW DATAIN tCHZ (6) (4) tDH DATAIN VALID 2948 drw 07 TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 2948 drw 08 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state. 7.2 5 IDT71256SA IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT 71256 Device Type SA XX XXX X Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) P TP Y 600-mil Plastic DIP (P28-1 P28-1) 300-mil Plastic DIP (P28-2 P28-2) 300-mil SOJ (SO28-5 SO28-5) 12 15 20 25 Speed in nanoseconds 2948 drw 09 7.2 6