ICX054BK ICX054AK E98222A99 CXD1267AN 3200K CM500S 1/10V 2SA1175 22/20V 10/16V - Datasheet Archive

 

Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras For the availability of this product, please contact the

 

ICX054BK ICX054BK Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras For the availability of this product, please contact the sales office. Description The ICX054BK ICX054BK is an interline CCD solid-state image sensor suitable for NTSC color video cameras. Compared with the current product ICX054AK ICX054AK, sensitivity is improved drastically through the adoption of Super HAD CCD technology. Ye, Cy, Mg, and G complementary color mosaic filters are used. This chip features a field period readout system, and an electronic shutter with variable charge-storage time. 16 pin DIP (Plastic) Features · High sensitivity (+3dB at F5.6, +1.5dB at F1.2 compared with ICX054AK ICX054AK) · High saturation signal (+1dB compared with ICX054AK ICX054AK) · Low smear and low dark current · Excellent antiblooming characteristics · Continuous variable-speed shutter V · Ye, Cy, Mg and G complementary color mosaic filters on chip · Horizontal register: 5V drive · Reset gate: 5V drive Pin 1 1 12 2 Device Structure · Interline CCD image sensor · Image size: · Number of effective pixels: · Number of total pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material: Pin 9 H 25 Optical black position (Top View) Diagonal 6mm (Type 1/3) 510 (H) × 492 (V) approx. 250K pixels 537 (H) × 505 (V) approx. 270K pixels 6.00mm (H) × 4.96mm (V) 9.6µm (H) × 7.5µm (V) Horizontal (H) direction: Front 2 pixels, Rear 25 pixels Vertical (V) direction: Front 12 pixels, Rear 1 pixel Horizontal 16 Vertical 1 (even field only) Silicon Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ­1­ E98222A99 E98222A99 ICX054BK ICX054BK VOUT VSS VGG GND V1 V2 V3 V4 Block Diagram and Pin Configuration (Top View) 8 7 6 5 4 3 2 1 Vertical register Cy Ye Cy Ye G Mg G Mg Cy Ye Cy Ye G Mg G Mg Cy Ye Cy Ye G Mg G Mg Note Horizontal register Pin No. Symbol 12 13 14 15 SUB VL RG NC H1 Description Pin No. : Photo sensor 16 H2 11 GND Pin Description 10 VDD Note) 9 Symbol Description 1 V4 Vertical register transfer clock 9 VDD Output amplifier drain supply 2 V3 Vertical register transfer clock 10 GND GND 3 V2 Vertical register transfer clock 11 SUB Substrate (Overflow drain) 4 V1 Vertical register transfer clock 12 VL Protective transistor bias 5 GND GND 13 RG Reset gate clock 6 VGG Output amplifier gate bias 14 NC 7 VSS Output amplifier source 15 H1 Horizontal register transfer clock 8 VOUT Signal output 16 H2 Horizontal register transfer clock Absolute Maximum Ratings Item Ratings Unit ­0.3 to +55 V VDD, VOUT, VSS ­ GND ­0.3 to +18 V VDD, VOUT, VSS ­ SUB ­55 to +10 V V1, V2, V3, V4 ­ GND ­15 to +20 V V1, V2, V3, V4 ­ SUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V H1, H2 ­ V4 ­17 to +17 V H1, H2, RG, VGG ­ GND ­10 to +15 V H1, H2, RG, VGG ­ SUB ­55 to +10 V VL ­ SUB ­65 to +0.3 V V1, V2, V3, V4, VDD, VOUT ­ VL ­0.3 to +30 V RG ­ VL ­0.3 to +24 V VGG, Vss, H1, H2 ­ VL ­0.3 to +20 V Storage temperature ­30 to +80 °C Operating temperature ­10 to +60 °C Substrate voltage SUB ­ GND Supply voltage Vertical clock input voltage 1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. ­2­ Remarks 1 ICX054BK ICX054BK Bias Conditions Item Symbol Min. Typ. Max. Unit Output amplifier drain voltage VDD 14.55 15.0 15.45 V Output amplifier gate voltage VGG 1.75 2.0 2.25 V Output amplifier source VSS Substrate voltage adjustment range VSUB 9.0 18.5 V Fluctuation range after substrate voltage adjustment VSUB ­3 +3 % Reset gate clock voltage adjustment range VRGL 1.0 4.0 V Fluctuation range after reset gate clock voltage adjustment VRGL ­3 +3 % Protective transistor bias VL Remarks Grounded with 680 resistor ±5% 1 1 2 DC Characteristics Item Symbol Min. Typ. Max. Unit 3 Remarks Output amplifier drain current IDD mA Input current IIN1 1 µA 3 Input current IIN2 10 µA 4 1 Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is ±3%. VSUB code VRGL code one character indication one character indication VRGL code VSUB code Code and optimal setting correspond to each other as follows. VRGL code 1 2 3 4 5 6 7 Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSUB code E Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 f G h J K L m N P Q R S T U V W X Y Z "5L" VRGL = 3.0V VSUB = 12.0V 2 VL setting is the VVL voltage of the vertical transfer clock waveform. 3 1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested are grounded. 2) Current to each pin when 20V is applied sequentially to V1, V2, V3 and V4 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin. 3) Current to each pin when 15V is applied sequentially to RG, H1, H2 and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin. 4) Current to VL pin when 30V is applied to V1, V2, V3, V4, VDD and VOUT pins or when, 24V is applied to RG pin or when, 20V is applied to VGG, Vss, H1 and H2 pins, while VL pin is grounded. However, GND and SUB pins are left open. 4 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. ­3­ ICX054BK ICX054BK Clock Voltage Conditions Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 ­0.05 0 0.05 V 2 ­0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 ­9.0 ­8.5 ­8.0 V 2 VVL = (VVL3 + VVL4) /2 VV Vertical transfer clock voltage Typ. VVH3, VVH4 Readout clock voltage Min. VVH1, VVH2 Item 7.8 8.5 9.05 V 2 VV = VVHn ­ VVLn (n = 1 to 4) 0.1 V 2 Symbol |VVH1 ­ VVH2| Remarks VVH = (VVH1+VVH2) /2 VVH3 ­ VVH ­0.25 0.1 V 2 VVH4 ­ VVH ­0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling Horizontal transfer clock voltage VH 4.75 5.0 5.25 V 3 VHL ­0.05 0 0.05 V 3 Reset gate clock voltage VRG 4.5 5.0 5.5 V 4 1 0.8 V 4 Low-level coupling Substrate clock voltage VSUB 24.5 V 5 VRGLH ­ VRGLL 22.5 23.5 1 The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Symbol Min. Typ. Max. Unit Waveform diagram VRGL ­0.2 0 0.2 V 4 VRG 8.5 9.0 9.5 V 4 ­4­ Remarks ICX054BK ICX054BK Clock Equivalent Circuit Constant Symbol Item Min. Typ. Max. Unit CV1, CV3 1500 pF CV2, CV4 820 pF CV12, CV34 470 pF CV23, CV41 230 pF CV13 150 pF CV24 230 pF Capacitance between horizontal transfer clock and GND CH1, CH2 47 pF Capacitance between horizontal transfer clocks CHH 47 pF Capacitance between reset gate clock and GND CRG 5 pF Capacitance between substrate clock and GND CSUB 320 pF R1, R3 51 R2, R4 100 Vertical transfer clock ground resistor RGND 15 Horizontal transfer clock series resistor RH 10 Reset gate clock series resistor RRG 40 Remarks Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor V1 V2 CV12 R1 R2 RH RH H1 CV1 H2 CV2 CV41 CHH CV23 CH1 CH2 CV13 CV24 CV4 R4 RGND CV3 R3 CV34 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RRG RG CRG Reset gate clock equivalent circuit ­5­ ICX054BK ICX054BK Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT M 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform V1 V3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL V2 V4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn ­ VVLn (n = 1 to 4) ­6­ VVL ICX054BK ICX054BK (3) Horizontal transfer clock waveform tr twh tf 90% VH twl 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl Point A VRG RG waveform VRGL + 0.5V VRGLH VRGL VRGLL H1 waveform 10% VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH ­ VRGL ­7­ ICX054BK ICX054BK (5) Substrate clock waveform 100% 90% M M 2 VSUB VSUB 10% 0% tr twh tf Clock Switching Characteristics Item Symbol twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT Vertical transfer clock V1, V2, V3, V4 Horizontal transfer clock H Horizontal transfer clock H1 Horizontal transfer clock H2 Reset gate clock RG 11 Substrate clock SUB 1.5 2.0 2.3 2.5 0.5 41 38 42 12 µs 0.5 15 2 During readout 0.25 µs 1 0.015 37 Unit Remarks 10 15 ns During imaging 0.012 0.012 5.6 0.012 0.012 µs During parallelserial µs conversion 79 6.5 4.5 ns 5.6 15 75 0.5 1 When vertical transfer clock driver CXD1267AN CXD1267AN is used. 2 tf tr ­ 2ns. ­8­ 0.5 µs During drain charge ICX054BK ICX054BK Image Sensor Characteristics Item (Ta = 25°C) Symbol Min. Typ. Sensitivity S 800 970 Saturation signal Ysat 800 Smear Sm Video signal shading Unit Measurement method mV 1 mV 2 % 3 SHy 20 % 4 Zone 0, I 25 % 4 Zone 0 to II' Sr 10 % 5 Sb 10 % 5 Dark signal Ydt 2 mV 6 Ta = 60°C Dark signal shading Ydt 1 mV 7 Ta = 60°C Flicker Y Fy 2 % 8 Flicker R-Y Fcr 5 % 8 Flicker B-Y Fcb 5 % 8 Line crawl R Lcr 3 % 9 Line crawl G Lcg 3 % 9 Line crawl B Lcb 3 % 9 Line crawl W Lcw 3 % 9 Lag Lag 0.5 % 10 Uniformity between video signal channels Max. 0.002 0.007 Remarks Ta = 60°C Zone Definition of Video Signal Shading 510 (H) 10 8 9 V 10 H 8 H 8 Zone 0, I Zone II, II' V 10 492 (V) 10 Ignored region Effective pixel region Measurement System [Y] [A] CCD signal output Y signal output LPF1 (3dB down 4MHz) CCD C.D.S AMP [C] S/H LPF2 S/H Chroma signal output (3dB down 1MHz) Note) Adjust the amplifier gain so that the gain between [A] and [Y] and between [A] and [C] equal 1. ­9­ ICX054BK ICX054BK Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system. Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals Cy Ye Cy Ye A1 G Mg G Mg Cy Ye Cy Ye Mg G Mg G B A2 As shown in the left figure, fields are read out. The charge is mixed by pairs such as A1 and A2 in the A field. (pairs such as B in the B field) As a result, the sequence of charges output as signals from the horizontal shift register (Hreg) is, for line A1, (G + Cy), (Mg + Ye), (G + Cy), and (Mg + Ye). Hreg Color Coding Diagram These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words, the approximation: Y = {(G + Cy) + (Mg + Ye)} × 1/2 = 1/2 {2B + 3G + 2R} is used for the Y signal, and the approximation: R ­ Y = {(Mg + Ye) ­ (G + Cy)} = {2R ­ G} is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are (Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye). The Y signal is formed from these signals as follows: Y = {(G + Ye) + (Mg + Cy)} × 1/2 = 1/2 {2B + 3G + 2R} This is balanced since it is formed in the same way as for line A1. In a like manner, the chroma (color difference) signal is approximated as follows: ­ (B ­ Y) = {(G + Ye) ­ (Mg + Cy)} = ­ {2B ­ G} In other words, the chroma signal can be retrieved according to the sequence of lines from R ­ Y and ­ (B ­ Y) in alternation. This is also true for the B field. ­ 10 ­ ICX054BK ICX054BK Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following formula. S = Ys × 250 [mV] 60 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the Y signal output, 200mV, measure the minimum value of the Y signal. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula. Sm = 1 YSm 1 × × × 100 [%] (1/10V 1/10V method conversion value) 10 200 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula. SHy = (Ymax ­ Ymin)/200 × 100 [%] 5. Uniformity between video signal channels Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin [mV]) values of the R ­ Y and B ­ Y channels of the chroma signal and substitute the values into the following formula. Sr = | (Crmax ­ Crmin)/200 | × 100 [%] Sb = | (Cbmax ­ Cbmin)/200 | × 100 [%] 6. Dark signal Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. ­ 11 ­ ICX054BK ICX054BK 7. Dark signal shading After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal output and substitute the values into the following formula. Ydt = Ydmax ­ Ydmin [mV] 8. Flicker 1) Fy Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the difference in the signal level between fields (Yf [mV]). Then substitute the value into the following formula. Fy = (Yf/200) × 100 [%] 2) Fcr, Fcb Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between fields of the chroma signal (Cr, Cb) as well as the average value of the chroma signal output (CAr, CAb). Substitute the values into the following formula. Fci = (Ci/CAi) × 100 [%] (i = r, b) 9. Line crawls Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference between Y signal lines for the same field (Ylw, Ylr, Ylg, Ylb [mV]). Substitute the values into the following formula. Lci = (Yli/200) × 100 [%] (i = w, r, g, b) 10. Lag Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following formula. Lag = (Ylag/200) × 100 [%] FLD SG1 Light Strobe light timing Y signal output 200mV Output ­ 12 ­ Ylag (lag) RG H1 H2 XV4 XSG2 XV3 XSG1 XV1 XV2 XSUB 47k 0.1 2SA1175 2SA1175 22/20V 22/20V 10 9 8 7 10k 10/16V 10/16V 100k 11 12 13 14 15 16 5 6 17 4 CXD1267AN CXD1267AN 19 18 0.1 1/35V 1/35V 22/16V 22/16V 0.1 0.01 0.1 1 2 3 4 5 67 8 27k 180k ICX054 ICX054 (BOTTOM VIEW) 16 15 14 13 12 11 10 V4 2 3 V3 H1 H2 0.1 NC 5V VSUB 100k V2 1/6.3V V1 RG 20 GND VL 1 VGG SUB 15V VSS GND 9 3.3/16V 3/16V 0.01 3.9k 1500p 2SK523 2SK523 100 47/6.3V 3.3/20V 3/20V 680 VOUT ­ 13 ­ VDD Drive Circuit 1M CCD OUT [*A] ­8.5V ICX054BK ICX054BK ICX054BK ICX054BK Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 Ye 0.8 Relative Response 0.7 G 0.6 Cy 0.5 0.4 0.3 Mg 0.2 0.1 0.0 400 450 500 550 600 700 650 Wave Length [nm] Sensor Readout Clock Timing Chart HD V1 2.5 V2 Odd Field V3 V4 38.1 1.2 1.5 2.5 2.0 0.3 V1 V2 Even Field V3 V4 Unit: µs ­ 14 ­ ­ 15 ­ CCD OUT V4 V3 V2 V1 SG2 SG1 HD BLK VD FLD 492 491 525 1 2 3 4 5 520 Drive Timing Chart (Vertical sync) 10 2 4 6 1 3 5 15 2 4 6 1 3 5 265 492 491 2 4 6 1 3 5 280 2 4 6 8 1 3 5 7 ICX054BK ICX054BK 275 270 260 20 ­ 16 ­ SUB V4 V3 V2 V1 XSHD XSHP RG H2 H1 BLK HD 10 510 1 2 3 5 505 500 Drive Timing Chart (Horizontal sync) ICX054BK ICX054BK 10 15 16 1 2 1 2 3 5 10 1 2 3 5 25 20 15 ICX054BK ICX054BK Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N 50N 1.2Nm Plastic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. ­ 17 ­ ICX054BK ICX054BK c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. ­ 18 ­ ­ 19 ­ 1.2 2.5 0.69 ~ ~ Plastic GOLD PLATING 42 ALLOY 0.9g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 0.3 M 1.27 9.2 10.3 12.2 ± 0.1 H PACKAGE MATERIAL V 6.1 ~ 2.5 0.46 0.3 A 1.2 2.5 8.4 (For the first pin only) 0.5 PACKAGE STRUCTURE B 5.7 D B' C 1 8 11.6 16 9 2.5 2-R0.5 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom "C" is less than 50µm. The tilt of the effective image area relative to the top "D" of the cover glass is less than 50µm. 6. The height from the bottom "C" to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.94 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (6.1, 5.7) ± 0.15mm. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 1. "A" is the center of the effective image area. 16pin DIP (450mil) 9.5 11.4 ± 0.1 3.1 Unit: mm 3.35 ± 0.15 1.27 3.5 ± 0.3 0° to 9° 0.25 11.43 Package Outline ICX054BK ICX054BK