ICS9FGP202A 9FGP202A VDD33 33MHZ/ GND33 25MHZ GND32K VDD32K VDD96 DOT96SST - Datasheet Archive

 

Integrated Circuit Systems, Inc. Frequency Timing Generator for Peripherals OE_RMIIA RMII3 RMII2 VDDRMII GNDRMII RMII1 RMII0

 

ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Frequency Timing Generator for Peripherals OE_RMIIA RMII3 RMII2 VDDRMII GNDRMII RMII1 RMII0 SMBCLK VttPwr_GD/PD# Output Features: · 1 - 0.7V current-mode differential CPU pair · 8 - 50MHz 3.3V RMII outputs · 1 - DOT 96MHz output · 1 - 33.33MHz output · 1 - 32.768KHz output · 2 - 25MHz REF outputs SMBDAT Pin Configurations Recommended Application: CK-MNG for Intel servers 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 9FGP202A 9FGP202A OE_RMIIB RMII4 RMII5 GNDRMII VDDRMII RMII6 RMII7 VDD33 VDD33 33.33MHZ/ 33MHZ/*SMBADR GND33 GND33 X2_25 X1_25 GNDREF 25MHZ 25MHZ_1 25MHz_0 VDDREF GND32K GND32K Features/Benefits: · Selectable SMBus Address - D0/D1 or C0/C1 · Spread Spectrum compability on CPU and DOT 96MHz clocks · M/N programming on CPU and DOT 96MHz clocks via SMBus · Outputs can be disabled via pins or SMBus 32.768KHz IREF 11 12 13 14 15 16 17 18 19 20 VDD32K VDD32K Key Specifications: · 0ppm synthesis error on CPU, RMII & 33.33MHz clocks · +/- 100ppm frequency accuracy on other clocks GND VDD96 VDD96 DOT96SST DOT96SST DOT96SSC DOT96SSC OE_96 OE_CPU CPUCLKT0 CPUCLKC0 VDDCPU GNDCPU 40-MLF 40-MLF * Internal Pull-Up Resistor * Internal Pull-Dow n Resistor Functionality CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS DOT96SS MHz MHz Byte0 Bit2 Byte0 Bit1 Byte0 Bit0 0 0 0 266.67 96.00 0 0 1 133.33 96.00 0 1 0 200.00 96.00 0 1 1 166.67 96.00 1 0 0 333.33 96.00 1 0 1 100.00 96.00 1 1 0 400.00 96.00 1 1 1 Reserved 96.00 33.33 MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 RMII MHz 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 25 MHz 25.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 32.768 KHz 32.768 32.768 32.768 32.768 32.768 32.768 32.768 32.768 Power up default is highlighted. Power Supply Pins Pin Number Description VDD GND 9 10 CPUCLK output 2 1 DOT96SS DOT96SS output 26,34 27,35 50 MHz RMII outputs 23 21 33.33MHz output 12 14 32.768KHz output 15 18 XTAL, REF outputs Note: All VDD should be connected to a common power rail with proper filtering and decoupling. 1339C-09/14/09 1339C-09/14/09 SMBus Address Selection SMBADR *SMBADR = 0 D0/D1 * Default value SMBADR = 1 C0/C1 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE PWR PWR OUT OUT 1 2 3 4 GND VDD96 VDD96 DOT96SST DOT96SST DOT96SSC DOT96SSC 5 OE_96 IN 6 OE_CPU IN 7 CPUCLKT0 OUT 8 CPUCLKC0 OUT 9 10 VDDCPU GNDCPU PWR PWR 11 IREF OUT 12 13 14 15 16 17 18 19 20 21 22 VDD32K VDD32K 32.768KHz GND32K GND32K VDDREF 25MHz_0 25MHZ 25MHZ_1 GNDREF X1_25 X2_25 GND33 GND33 33.33MHZ/ 33MHZ/*SMBADR PWR OUT PWR PWR OUT OUT PWR IN OUT PWR I/O 23 24 25 26 27 28 29 VDD33 VDD33 RMII7 RMII6 VDDRMII GNDRMII RMII5 RMII4 PWR OUT OUT PWR PWR OUT OUT 30 OE_RMIIB IN 31 OE_RMIIA IN 32 33 34 35 36 37 38 39 RMII3 RMII2 VDDRMII GNDRMII RMII1 RMII0 SMBCLK SMBDAT OUT OUT PWR PWR OUT OUT IN I/O 40 VttPwr_GD/PD# IN DESCRIPTION Ground pin. Power pin for the DOT96 DOT96 clocks, nominal 3.3V True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock. Active high input for enabling 96Hz outputs. 1 = enable output(s), 0 = tri-state output(s) Active high input for enabling CPU DIFF pairs. 1 = enable output(s), 0 = tri-state output(s) True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin for the CPU outputs This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Power pin for the 32.768KHz outputs, nominal 3.3V 32.768KHz clock output Ground pin for the 32.768KHz outputs Ref, XTAL power supply, nominal 3.3V 25MHz clock output, 3.3V 25MHz clock output, 3.3V Ground pin for the REF outputs. Crystal input, Nominally 25.00MHz. Crystal output, Nominally 25.00MHz. Ground pin for the 33.33MHz outputs 33.33MHz clock output / SMBus address select bit. Power pin for the 33.33MHz outputs, nominal 3.3V 3.3V RMII clock output 3.3V RMII clock output 3.3V power pin for the RMII clocks. Ground pin for the 3V50 outputs 3.3V RMII clock output 3.3V RMII clock output Active high input for enabling RMII(7:4) outputs. 1 = enable output(s), 0 = low Active high input for enabling RMII(3:0) outputs. 1 = enable output(s), 0 = low 3.3V RMII clock output 3.3V RMII clock output 3.3V power pin for the RMII clocks. Ground pin for the 3V50 outputs 3.3V RMII clock output 3.3V RMII clock output Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. 1339C-09/14/09 1339C-09/14/09 2 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. General Description The ICS9FGP202A ICS9FGP202A is a peripheral clock for Intel Servers. An SMBus interface allows full control of the device. Block Diagram 25MHz(1:0) X1_25 X2_25 XTAL CPU PLL (SPREAD CAPABLE) DOT PLL (SPREAD CAPABLE) VttPwr_GD/PD# CPUCLK DOT96SS DOT96SS OE_CPU OE_96 OE_RMIIA OE_RMIIB CONTROL LOGIC 33.33MHz FIXED PLL DIVIDERS 8 RMII(7:0) SMBADR SMBDAT SMBCLK DIVIDERS 1339C-09/14/09 1339C-09/14/09 3 32.768KHz ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. ICS9FGP202A ICS9FGP202A Zo Rs CL=5pF Test Load SEPP Output Buffer (Single Ended Push Pull) L1 Zo Rs CL=5pF L2 Zo Rs SEPP Output Buffer (Single Ended Push Pull) NOTE: L1 must equal L2 +/- 25 mils The singled-ended outputs of the ICS9FGP202A ICS9FGP202A default to either a drive strength of 2 loads or a drive strength of 1 load. Alternate drive strengths can be selected via the SMBus. Using the correct resistor value can properly terminate the output to the transmission line without having to change the default drive strengths via the SMBus. The default drive strengths for the single ended outputs are show below, as are the suggested termination resistors for the above topologies. All values assume Zo = 50 ohms: Default Drive Strength Table Default Drive RMII 1 Load 33.33MHz 2 Loads 25Mhz 2 Loads 32.768KHz 2 Loads Optional Drive 2 Loads 1 Load 1 Load 1 Load Series Termination Resistor Values Series Resistor Series Resistor Output Drive (Rs) for driving 1 (Rs) for driving 2 Strength Load Loads 1 Load 22 ohms N/A 2 Loads 33 ohms 7.5 ohms 1339C-09/14/09 1339C-09/14/09 4 CL=5pF ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Truth Table 1: VttPwr_GD/PD# and OE_96 VttPwr_GD/PD# OE_96 Clocks Pin 40 Pin 5 0 0 All clocks are powered down 0 1 All clocks are powered down 1 0 All clocks are enabled except DOT96SS DOT96SS 1 1 *All clocks are enabled including DOT96SS DOT96SS *Assuming DOT96 DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default) Truth Table 2: VttPwr_GD/PD# and OE_CPU VttPwr_GD/PD# OE_CPU Clocks Pin 40 Pin 6 0 0 All clocks are powered down 0 1 All clocks are powered down 1 0 All clocks are enabled except CPUCLK 1 1 *All clocks are enabled including CPUCLK *Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default) Table 1: CPU Spread and Frequency Selection CPU SS_EN Byte 0 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPU FS2 Byte 0 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CPU FS1 Byte 0 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CPU FS0 Byte 0 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz Down Spread % 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00 0% 0% 0% 0% 0% 0% 0% 0% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 1339C-09/14/09 1339C-09/14/09 5 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Table2: DOT96 DOT96 Spread and Frequency Selection Table DOT96 DOT96 SS_EN Byte 0 bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 FS2 FS1 FS0 Byte 3 bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Byte 3 bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Byte 3 bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Byte 3 bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DOT96SS DOT96SS MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 1339C-09/14/09 1339C-09/14/09 6 Spread % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +/-0.25 +/-0.5 +/-0.75 +/-1.0 -0.25 -0.50 -0.75 -1.0 -1.25 -1.50 -1.75 -2.0 -2.25 -2.5 -2.75 -3.00 Center Center Center Center Down Down Down Down Down Down Down Down Down Down Down Down ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes 3.3V Supply Voltage Maximum difference across all VDD pins Storage Temperature VDDxxx - GND - 0.5 3.3V GND + 4.5 V 1 VDDdelta - 0.5 V 1 ° C 1 1 Ambient Operating Temp Ts - -65 150 Tambient - 0 70 °C 125 °C 1 V 1 Junction Temperature 1 Tj - Input ESD protection HBM ESD prot - 2000 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors TYP Notes VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 IDD3.3OP IDD3.3PD all outputs driven 200 mA 1 all diff pairs driven 30 mA 1 all differential pairs tri-stated 8 mA 1 Input Frequency Fi Pin Inductance Lpin CIN Logic Inputs 4 pF 1 Input Capacitance COUT Output pin capacitance 5 pF 1 CINX X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of 5 pF 1 2.5 ms 1 33 kHz 1 300 us 1 5 ns 1 Clk Stabilization TSTAB Modulation Frequency Tdrive_PD Tfall_PD Trise_PD SMBus Voltage VDD = 3.3 V 25.00000 MHz 7 30 PD rise time of @ IPULLUP Low-level Output Voltage VOL Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 5 ns 1 5.5 V 1 0.4 2.7 VDD 2 nH V 1 mA 1 1000 ns 1 300 ns 1 4 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs. 1339C-09/14/09 1339C-09/14/09 7 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High SYMBOL CONDITIONS* MIN Zo VO = Vx 3000 VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Measurement on single ended signal using absolute value. 1150 mV 1 -300 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm TYP MAX UNITS NOTES 1 mV 1 550 mV 1 140 250 mV 1 1,2 0 100 ppm 2.4998 2.5000 2.5003 ns 2 400MHz spread 2.4998 2.5128 ns 2 333.33MHz nominal 2.9997 3.0003 ns 2 333.33MHz spread 2.9997 3.0154 ns 2 266.66MHz nominal 3.7496 3.7500 3.7504 ns 2 266.66MHz spread Tperiod -100 400MHz nominal Average period Variation of crossing over all edges see Tperiod min-max values 3.7496 3.7692 ns 2 200MHz nominal 4.9995 5.0000 5.0005 ns 2 5.0256 ns 2 6.0000 6.0006 ns 2 6.0307 ns 2 7.5000 7.5008 ns 2 7.5385 ns 2 10.0000 10.0010 ns 2 200MHz spread 4.9995 166.66MHz nominal 5.9994 3.0000 166.66MHz spread 5.9994 133.33MHz nominal 7.4993 133.33MHz spread 7.4993 100.00MHz nominal 9.9990 100.00MHz spread ns 2 2.5978 ns 1,2 2.9147 3.1004 ns 1,2 266.66MHz nominal/spread 3.6646 3.8542 ns 1,2 200MHz nominal/spread 4.9145 5.1106 ns 1,2 166.66MHz nominal/spread 5.9144 6.1157 ns 1,2 133.33MHz nominal/spread Tabsmin/max 10.0513 2.4148 333.33MHz nominal/spread Absolute min/max period 9.9990 400MHz nominal/spread 7.4143 7.6235 ns 1,2 9.9140 10.1363 ns 1,2 175 700 ps 1 175 700 ps 1 Rise Time tr 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V Fall Time tf VOH = 0.525V VOL = 0.175V Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 3 1339C-09/14/09 1339C-09/14/09 8 ps 1 125 d-tf VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom, CPUCLK *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 Fall Time Variation ps 1 55 % 1 85 ps 1 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Electrical Characteristics - DOT96SS DOT96SS 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh VLow Statistical measurement on single ended signal 660 Voltage Low -150 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds mV 1 Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Measurement on single ended signal using absolute value. TYP MAX UNITS Notes 1 850 mV 1,3 150 mV 1,3 -300 250 96.00MHz nominal 96.00MHz spread 550 mV 1 140 mV 1 -300 300 ppm 1,2 10.4135 10.4198 ns 2 10.4135 Variation of crossing over all edges see Tperiod min-max values 10.4722 ns 2 1,2 Average period Tperiod Absolute min period Tabsmin 96.00MHz nominal/spread 10.1635 10.7222 ns Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 1 ps 1 55 % 1 250 45 ps 125 d-tf VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 Fall Time Variation ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.00MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. Electrical Characteristics - RMII - 50MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MAX Long Accuracy ppm see Tperiod min-max values Tperiod 50.00MHz output nominal -50 19.990 0 Clock period 20.000 50 20.010 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH V OH @MIN = 1.0 V VOL @ MIN = 1.95 V -33 1 1 V 1 mA -33 ns V 0.4 VOH@MAX = 3.135 V UNITS NOTES 1,2 ppm 1 mA 1 mA 1 38 mA 1 1 30 Output Low Current IOL Rise Time tr VOL = 0.4 V, VOH = 2.4 V 1 3 ns Fall Time tf VOH = 2.4 V, VOL = 0.4 V 1 3 ns 1 Duty Cycle dt1 VT = 1.5 V 35 65 % 1 VT = 1.5 V, for each group of 4 outputs 200 ps 1 tskew_3V50(3:0) Group Skew tskew_3V50(7:4) VOL @ MAX = 0.4 V Jitter, Long Term tjabs VT = 1.5 V, 10 sec interval 500 ps 1 Jitter, Peak tjpeak VT = 1.5 V 100 ps 1,3 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.00MHz 1339C-09/14/09 1339C-09/14/09 9 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Electrical Characteristics - 33.33MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MAX Long Accuracy ppm see Tperiod min-max values 0 30.000 100 30.030 30.000 30.280 Clock period Tperiod 33.33MHz output non-spread -100 29.970 Absolute min/max period Tabs 33.33MHz output non-spread 29.720 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL 0.4 -33 Output High Current IOH Output Low Current IOL Rise Time tr VOL = 0.4 V, VOH = 2.4 V 1 ns 1 1 V 1 mA 0.5 -33 30 VOL @ MAX = 0.4 V 1 mA 1 mA VOH@MAX = 3.135 V VOL @ MIN = 1.95 V ns V IOL = 1 mA V OH @MIN = 1.0 V UNITS NOTES 1 ppm 1 38 mA 1 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 250 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Electrical Characteristics - 32.768KHz PARAMETER SYMBOL CONDITIONS* MIN Long Accuracy ppm see Tperiod min-max values -100 Clock period Tperiod 32.768KHz output nominal Output High Voltage VOH IOH = -1 mA Output Low Voltage VOL TYP MAX 100 us IOL = 1 mA 0.4 Output High Current IOH Output Low Current IOL Rise Time tr VOL = 0.4 V, VOH = 2.4 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V 1 V 30.518 2.4 V OH @MIN = 1.0 V UNITS NOTES 1 ppm 1 V 1 mA -33 30 1 mA 1 1 mA 1 38 VOL @ MAX = 0.4 V mA 1 4 ns 1 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 1 4 ns Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) 1339C-09/14/09 1339C-09/14/09 10 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Electrical Characteristics - REF - 25MHz PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm see Tperiod min-max values -50 Clock period Tperiod 25.00MHz output nominal 39.980 Output High Voltage VOH IOH = -1 mA VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 UNITS Notes 50 ppm 1,2 40.020 ns 2 V OH @MIN = 1.0 V -29 Jitter tjcyc-cyc VT = 1.5 V 1 mA 1 27 mA 1 2 ns 1 2 ns 1 ps 1 55 % 1 500 VT = 1.5 V 1 mA ps 1 29 VT = 1.5 V dt1 1 mA -23 VOL @ MAX = 0.4 V tsk1 1 V 500 VOL @ MIN = 1.95 V Skew V 0.4 VOH@MAX = 3.135 V Duty Cycle 40.000 MAX 2.4 Output Low Voltage TYP 45 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 1339C-09/14/09 1339C-09/14/09 11 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9FGP202A ICS9FGP202A How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address *D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) · ICS clock will acknowledge each byte one at a time · Controller (host) sends a Stop bit · · · · · · · · · · · · · · · · · · · · · · Index Block Write Operation Controller (Host) starT bit T Slave Address *D0(H) WR WRite Controller (host) will send start bit. Controller (host) sends the write address *D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address *D1 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Controller (Host) T starT bit Slave Address *D0(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address *D1(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P * By default, SMBADR = 0, therefore, SMBus WRITE/READ address is D0/D1. Please see SMBus Address Selection table on page 1. 1339C-09/14/09 1339C-09/14/09 12 Not acknowledge stoP bit ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. SMBus Table: CPU Frequency Select and Spread Spectrum Control Register Pin # Byte 0 Name Control Function Reserved Reserved Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 DOT96 DOT96 SS_EN DOT96 DOT96 Spread Spectrum Enable Bit 4 CPU SS_EN CPU Spread Spectrum Enable Bit 3 CPU FS2 CPU Freq Select Bit 2 Bit 2 CPU FS1 CPU Freq Select Bit 1 Bit 1 CPU FS0 CPU Freq Select Bit 0 Bit 0 SMBus Table: RMII Output Control Register Pin # Name Byte 1 24 RMII_7 Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 25 28 29 32 33 36 37 RMII_6 Enable RMII_5 Enable RMII_4 Enable RMII_3 Enable RMII_2 Enable RMII_1 Enable RMII_0 Enable Control Function RMII_7 Output Control RMII_6 Output Control RMII_5 Output Control RMII_4 Output Control RMII_3 Output Control RMII_2 Output Control RMII_1 Output Control RMII_0 Output Control SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register Name Control Function Pin # Byte 2 7,8 CPUCLK PD Drive Mode Driven in PD Bit 7 Type RW Rev 0.20 RW RW RW RW RW RW 0 1 Reserved Reserved Reserved Disable Enable See Table 1: CPU Frequency Selection Table PWD 0 0 0 0 0 0 1 0 Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type RW 0 Driven 1 Hi-Z PWD 0 Bit 6 3,4 DOT96SS DOT96SS PD Drive Mode Driven in PD RW Driven Hi-Z 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 22 17 16 13 6 5 33.33MHz Enable 25MHz_1 Enable 25MHz_0 Enable 32.768kHz Enable CPUCLK Enable DOT96SS DOT96SS Enable 33.33MHz Output Control 25MHz_1 Output Control 25MHz_0 Output Control 32.768KHz Output Control CPUCLK Output Control DOT96SS DOT96SS Output Control RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 0 1 3 2 1 0 Type RW RW RW RW RW RW RW RW PWD 0 0 0 0 0 0 0 0 Control Function RMII_7 Strength Control RMII_6 Strength Control RMII_5 Strength Control RMII_4 Strength Control RMII_3 Strength Control RMII_2 Strength Control RMII_1 Strength Control RMII_0 Strength Control Type RW RW RW RW RW RW RW RW SMBus Table: DOT96 DOT96 Frequency Select and Spread Spectrum Control Register Name Control Function Pin # Byte 3 Reserved Reserved Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 DOT96SS DOT96SS FS3 DOT96 DOT96 Freq Select Bit Bit 3 DOT96SS DOT96SS FS2 DOT96 DOT96 Freq Select Bit Bit 2 DOT96SS DOT96SS FS1 DOT96 DOT96 Freq Select Bit Bit 1 DOT96SS DOT96SS FS0 DOT96 DOT96 Freq Select Bit Bit 0 SMBus Table: RMII Strength Control Register Name Pin # Byte 4 RMII_7 Str 24 Bit 7 RMII_6 Str 25 Bit 6 RMII_5 Str 28 Bit 5 RMII_4 Str 29 Bit 4 32 RMII_3 Str Bit 3 RMII_2 Str 33 Bit 2 RMII_1 Str 36 Bit 1 RMII_0 Str 37 Bit 0 1339C-09/14/09 1339C-09/14/09 13 Reserved Reserved Reserved Reserved See Table 2: DOT Frequency Selection Table 0 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) 1 2-Loads 2-Loads 2-Loads 2-Loads 2-Loads 2-Loads 2-Loads 2-Loads (2X) (2X) (2X) (2X) (2X) (2X) (2X) (2X) PWD 0 0 0 0 0 0 0 0 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register Byte 5 Name Control Function Pin # Reserved Reserved Bit 7 Reserved Reserved Bit 6 33.33MHz Str 33.33MHz Strength Control 22 Bit 5 25MHz_1 Str 25MHz_1 Strength Control 17 Bit 4 25MHz_0 Str 25MHz_1 Strength Control 16 Bit 3 32.768kHz Str 32.768kHz Strength Control 13 Bit 2 Reserved Reserved Bit 1 Reserved Reserved Bit 0 Type RW RW RW RW RW RW RW RW 0 Reserved Reserved 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) Reserved Reserved SMBus Table: Vendor & Revision ID Register Name Byte 6 Pin # RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R 0 - Type RW RW RW RW RW RW RW RW 0 Type RW RW RW RW RW RW RW RW Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function PLLs M/N Programming Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMBus Table: Device ID Byte 7 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 (LSB) SMBus Table: Byte Count Register Byte 8 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Byte 9 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Name SMBus Table: PLLs M/N Programming Enable Register Name Byte 10 Pin # M/N_EN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function REVISION ID VENDOR ID Control Function Device ID Control Function Writing to this register configures how many bytes will be read back. 1339C-09/14/09 1339C-09/14/09 14 1 2-Loads 2-Loads 2-Loads 2-Loads (2X) (2X) (2X) (2X) PWD 0 0 1 1 1 1 0 0 1 - PWD X X X X 0 0 0 1 1 PWD 0 0 1 0 0 0 1 0 0 - 1 - PWD 0 0 0 0 1 0 0 1 Type 0 1 PWD 0 0 0 0 0 0 0 0 Type RW 0 Disable 1 Enable PWD 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. SMBus Table: CPU PLL VCO Frequency Control Register Byte 11 Name Pin # N Div8 Bit 7 N Div 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bits Type RW RW RW RW RW RW RW RW SMBus Table: CPU PLL VCO Frequency Control Register Name Control Function Byte 12 Pin # N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: CPU PLL Spread Spectrum Control Register Name Control Function Byte 13 Pin # SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum Programming SSP4 Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: CPU PLL Spread Spectrum Control Register Name Control Function Byte 14 Pin # Reserved Bit 7 SSP14 SSP14 Bit 6 SSP13 SSP13 Bit 5 SSP12 SSP12 Bit 4 Spread Spectrum Programming SSP11 SSP11 Bit 3 b(14:8) SSP10 SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: DOT PLL VCO Frequency Control Register Name Byte 15 Pin # N Div8 Bit 7 N Div9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bits SMBus Table: DOT PLL VCO Frequency Control Register Name Control Function Byte 16 Pin # N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 1339C-09/14/09 1339C-09/14/09 15 Type RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X PWD X X X X X X X X PWD X X X X X X X X PWD 0 X X X X X X X PWD X X X X X X X X PWD X X X X X X X X ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. SMBus Table: DOT PLL Spread Spectrum Control Register Byte 17 Name Control Function Pin # SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum Programming SSP4 Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: DOT PLL Spread Spectrum Control Register Name Control Function Byte 18 Pin # Reserved Bit 7 SSP14 SSP14 Bit 6 SSP13 SSP13 Bit 5 SSP12 SSP12 Bit 4 Spread Spectrum Programming SSP11 SSP11 Bit 3 b(14:8) SSP10 SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: Reserved Byte 19 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Pin # Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Pin # Byte 21 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X PWD 0 X X X X X X X Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0 Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0 Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0 1339C-09/14/09 1339C-09/14/09 16 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. (Ref.) Seating Plane (N D -1)x e (Ref.) A1 Index Area ND & NE Even A3 N L N 1 Anvil Singulation 1 2 (Ref.) b (Ref.) A D (NE -1)x e E2 2 Sawn Singulation Top View are Even 2 E2 or E (Typ.) e 2 If N & N D E e Thermal Base D2 2 ND & NE Odd D2 0.08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL MIN. 0.8 1.0 A1 0 0.05 VJJD-2 / -5 TOLERANCE MAX. A (IDT package) SYMBOL DIMENSIONS (JEDEC reference only) A3 b e 40L N 0.1 8 0.50 BASIC 40 10 10 NE 0.3 40 ND 0.25 Reference 10 10 6.00 x 6.00 D x E BASIC 6.00 x 6.00 D2 MIN. / MAX. 1.75 / 4.80 2.75 / 3.0 E2 MIN. / MAX. 1.75 / 4.80 2.75 / 3.0 L MIN. / MAX. 0.30 / 0.50 0.3 / 0.5 Ordering Information Part / Order Number Shipping Packaging 9FPG202AKLF 9FPG202AKLF Tubes 9FPG202AKLFT 9FPG202AKLFT Tape and Reel Package 40-pin MLF 40-pin MLF Temperature 0 to +70°C 0 to +70°C "LF" suffix to the part number are the Pb-Free configuration and RoHS compliant. 1339C-09/14/09 1339C-09/14/09 17 ICS9FGP202A ICS9FGP202A Integrated Circuit Systems, Inc. Revision History Rev. 0.1 0.2 A B Issue Date Description 07/31/06 Initial Release 12/20/06 Changed power up stabilization time from 1.8 to 2.5 ms. Updated IDD specs. 1. IDD3.3OP 150mA to 200mA 2. IDD3.3PD driven from 50mA to 30mA 01/03/07 3. IDD3.3PD Hi-z from 12mA to 8 mA 4. Tightened all +/-300PPM /-300PPM tolerances to +/-100ppm 5. Final Release. 05/15/07 Updated Single-ended outputs to 50 ohms. 1339C-09/14/09 1339C-09/14/09 18 Page # 7 7 4