ICS90C61A 8514/A ICS90C61AN ICS90C61AM ICS90C61A-PR2 WD90C61 ICS90C61A-XXXN - Datasheet Archive

 

Integrated Circuit Systems, Inc. Dual Video/Memory Clock Generator Introduction Features The Integrated Circuit Systems ICS90C61A

 

ICS90C61A ICS90C61A Integrated Circuit Systems, Inc. Dual Video/Memory Clock Generator Introduction Features The Integrated Circuit Systems ICS90C61A ICS90C61A is a dual clock generator for VGA applications. It simultaneously generates two clocks. One clock is for the video memory, and the other is the video dot clock. · This data sheet supplies sales order information, a functional overview, signal pin details, a block diagram, AC/DC characteristics, timing diagrams, and package mechanical information. Description The Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C61A ICS90C61A) is capable of producing different output frequencies under firmware control. The video output frequency is derived from a 14.318 MHz system clock available in IBM PC/XT/AT and Personal System/2 computers. It is designed to work with Western Digital Imaging Video Graphics Array and 8514/A 8514/A devices to optimize video subsystem performance. · · · · · · · Dual Clock generator for the IBM-compatible Western Digital Imaging Video Graphics Array (VGA) LSI devices, and 8514/A 8514/A chip sets Integral loop filter components Generates seven video clock frequencies derived from a 14.318 MHz system clock reference frequency Video clock which is selectable among the seven internally generated clocks and two external clocks On-chip generation of four memory clock frequencies CMOS technology Available in 20-pin PLCC, SOIC, and DIP packages Extended frequency capabilities to 80 MHz in custom frequency patterns Pin Configuration The video dot clock output may be one of seven internallygenerated frequencies or two external inputs. The selection of the video dot clock frequency is done through four inputs. · · · · SEL0 SEL1 VGATTL FCLKSEL SEL0 and SEL1 are latched by the SELEN signal. VGATTL and FCLKSEL are used as direct inputs to the VCLK selection. Table 1-1 is the truth table for VCLK selection. The input and truth table have been designed to allow a direct connection to one of the many Western Digital Imaging VGA controllers or 8514/A 8514/A chip sets. The MCLK output is one of four internally-generated frequencies as shown in Table 1-2. The various VCLK and MCLK frequencies are derived from the 14.318 MHz input frequency. The VCLKE and MCLKE input can tristate the VCLK and MCLK outputs to facilitate board level testing. 20-Pin PLCC, DIP or SOIC J-4, J-7, J-10 The ICS90C61A ICS90C61A is capable of extended frequency output up to 80 MHz in custom applications. See page 5 for details. Note: ICS90C61AN ICS90C61AN (DIP) pin-out is identical to ICS90C61AM ICS90C61AM (SOIC) pin-out. 90C61ARevA111095 B-53 ICS90C61A ICS90C61A ICS90C61A ICS90C61A VGA Interface The ICS90C61A ICS90C61A has two system interfaces: System Bus and VGA Controller, and six user-programmable inputs. Figure 2-1 shows how the Integrated Circuit Systems VGA Clock ICS90C61A ICS90C61A is connected to a VGA controller. Western Digital Imaging VGA controllers normally have a status bit that indicates to the VGA controller that it is working with a clock chip. When working with a clock chip the VGA controller changes two of its clock inputs, VCLK1 and VCLK2, to outputs. These outputs are used to select the required video frequency. Figure 2-1 ICS90C61A ICS90C61A Interface Note: C2 should be placed as close as possible to the ICS90C61A ICS90C61A AVCC pin. B-54 ICS90C61A ICS90C61A System Bus Inputs Analog Filters The system bus inputs are: The analog filters are integral to the ICS90C61A ICS90C61A device. No external components are required. This feature reduces PC board space requirements and component costs. Phase jitter is reduced as externally-generated noise cannot easily influence the phase-locked loop filter. · · · REFCLK SEL0 SEL1 The ICS90C61A ICS90C61A uses the system bus 14.318 MHz clock as a reference to generate all its frequencies for both video and memory clocks. Data lines D2 and D3 are commonly used as inputs to VSEL0 and VSEL1 for video frequency selection. User-Definable Inputs The user-definable inputs are: · · · · · Inputs from VGA Controller The VGA controller input to the ICS90C61A ICS90C61A is: · SELEN The ICS90C61A ICS90C61A is programmed to generate different video clock frequencies using the inputs of SEL0, SEL1, VGATTL, and FCLKSEL. The signals VGATTL and FCLKSEL may be supplied by the VGA controller as is the case in Western Digital Imaging VGA controllers. The inputs SEL0-1 are latched with the signal SELEN. The SELEN input should be an active low pulse. This active low pulse is generated in Western Digital Imaging VGA controllers during I/O writes to internal register 3C2h. Note: Only SEL0 and SEL1 are latched with signal SELEN. EXTCLK and FCLKIN are additional inputs that may be internally routed to the VCLK output. The additional inputs are useful for supporting modes that require frequencies not provided by the ICS90C61A ICS90C61A. VCLKE and MCLKE are the output enable signals for VCLK and MCLK.When low, the respective output is tristated. MSEL0-1 are the memory clock (MCLK) select lines. Table 1-2 shows how MCLK frequencies are selected. All signals in this group have internal pull-up resistors. VGATTL and FCLKSEL are video clock (VCLK) select lines that can select additional VCLK frequencies. See Table 1-1. Outputs to VGA Controller The outputs from the ICS90C61A ICS90C61A to the VGA controller are: · · EXTCLK FCLKIN VLCKE, MCLKE MSELO-1 VGATTL, FCLKSEL MCLK VCLK MCLK and VCLK are the two clock outputs to the VGA controller. B-55 ICS90C61A ICS90C61A Power Considerations The ICS90C61A ICS90C61A product requires an AVCC supply free of fast rise time transients. This requirement may be met in several ways and is highly dependent on the characteristics of the host system. A VGA adapter card is unique in that it must function in an unknown environment. +5 volt power quality is dependent not only on the quality of the power supply resident in the host system, but also on the other cards plugged into the host's backplane. Power supply noise ranges from fair to terrible. As the VGA adapter manufacturer has no control over this, he must assume the worst. The best solution is to create a clean +5 volts by deriving it from the +12 volt supply by using a zener diode and dropping resister. A 470 Ohm resistor and 4.7 volt Zener diode are the least costly way to accomplish this. A .047 to .1 microfarad bypass capacitor tied from AVCC to AGND insures good high-frequency decoupling of this point. Laptop and notebook computers have entirely different problems with power. Typically they have no +12 volt supply; however, they are much quieter electrically. Because the designer has complete control of the system architecture, he can place sensitive components and systems such as the RAMDAC and Dual Video/Memory Clock away from DRAM and other noise-generating components. Most systems provide power that is clean enough to allow for jitter-free Dual Video/Memory Clock performance if the +5 volt supply is decoupled with a resistor and 22 microfarad Tantalum capacitor. Digital inputs that are desired to be held at static logical high level should not be tied to +5 volts as this will result in excessive current drain through the ESD protection diode. The internal pull-up resistors will adequately keep these inputs high. B-56 ICS90C61A ICS90C61A Table 1-1 VCLK SELECTION FCLKSEL 1 1 1 1 1 1 1 1 0 VGATTL 0 0 0 0 1 1 1 1 X SEL0 0 0 1 1 0 0 1 1 X SEL1 0 1 0 1 0 1 0 1 X VCLK FREQUENCY (MHz) ICS90C61A-PR2 ICS90C61A-PR2* REFCLK 16.108 32.216 44.744 25.057 28.089 EXTCLK* 36.242 FCLKIN* Table 1-2 MCLK SELECTION MSEL1 0 0 1 1 MCLK FREQUENCIES (MHz) ICS90C61A-PR2 ICS90C61A-PR2* 41.612 37.585 36.242 44.744 MSEL0 0 1 0 1 *Note: FCLKIN and EXTCLK may be programmed to output custom frequencies up to 80 MHz in applications which require this capability. Custom frequencies in these addresses require a significant volume committment and/or one-time mask charge. Contact ICS Sales for details. *Note: If no "dash number" is specified, then the "-PR2" will be supplied since this version is completely compatible with the original WD90C61 WD90C61 frequency set. B-57 ICS90C61A ICS90C61A Figure 2-2 ICS90C61A ICS90C61A Functional Block Diagram B-58 ICS90C61A ICS90C61A Pin Descriptions The following table provides the pin descriptions for the 20-pin ICS90C61A ICS90C61A packages: PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN SYMBOL REFCLK FCLKIN EXTCLK SEL0 SEL1 SELEN VGATTL FCLKSEL MSEL0 DGND MSEL1 MCLK NC MCLKE AVCC AGND NC VCLKE VCLK DVCC TYPE IN IN IN IN IN IN IN IN IN IN OUT IN IN OUT - DESCRIPTION Reference input clock from system. Feature clock input pin. External clock input for an additional frequency. Control input for VCLK selection. Control input for VCLK selection. Strobe for latching VSEL(0,1) (low enable). Control input for VCLK selection. Control input for FCLK selection. Select input for MCLK selection. Ground for Digital Circuit. Select input for MCLK selection. Memory Clock Output. No Connection. Enable input for MCLK output (high enables output). Power supply for analog circuit. Ground for analog circuit. No Connection. Enable input for VCLK output (high enables output). Video Clock Output. Power supply for Digital Circuit. Note: CLK1, EXTCLK, FCLKIN, SEL0, SEL1,VGATTL, FCLKSEL, SELEN, MSEL0, MSEL1, VCLKE, and MCLKE - input pins have internal pull-up resistors. B-59 ICS90C61A ICS90C61A Absolute Maximum Ratings Ambient temperature under bias Storage temperature Voltage on all inputs and outputs with respect to VSS Standard Test Conditions The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to VSS (OV Ground). Positive current flows into the referenced pin. 0°C to 70°C -40°C to 125°C 0.5 to 7 volts Note: Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating temperature range Power supply voltage 0°C to 70°C 4.75 to 5.25 volts DC Characteristics SYMBOL PARAMETER MIN MAX UNITS CONDITIONS VIL Input Low Voltage VSS 0.8 V VCC = 5V VIH Input High Voltage 2.0 VCC V VCC = 5V VIL VIH IIH VOL VOH ICCD ICCA RUP Cin Cout Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Digital Supply Current Analog Supply Current Internal Pull-up Resistors Input Pin Capacitance Output Pin Capacitance Vss VCC -1.5 2.4 25 - 1.5 VCC 20 0.4 35 10 8 12 V V µA V V mA mA K ohms pF pF B-60 VCC = 5V VCC = 5V Vin = VCC IOL = 6.0 mA IOH = 4.0 mA VCC = 5V, CL = 15pF VCC = 5V VCC = 5V FC = 1 MHz FC = 1 MHz PINS SEL0-1, SELEN, VGATTL, MSEL0-1, FCLKSEL, VCLKE, MCLKE, EXTCLK SEL0-1, SELEN, VGATTL, MSEL0-1, FCLKSEL, VCLKE, MCLKE, EXTCLK FCLKIN FCLKIN ICS90C61A ICS90C61A AC Timing Characteristics The following notes apply to all of the parameters presented in this section. 1. 2. 3. 4. 5. 6. 7. REFCLK = 14.318 MHz TC = 1/FC All units are in nanoseconds (ns). Maximum jitter is within a range of 30 µ s after triggering on a 400 MHz scope. Rise and fall time between 0.8 and 2.0 VDC. Output pin loading = 15pF Duty cycle is measured at 1.4V SYMBOL PARAMETER MIN MAX NOTES SELEN TIMING Tpwen Tsuen Thden Enable Pulse Width Setup Time Data to Enable Hold Time Data to Enable Tr Tf Rise Time Fall Time 20 20 10 REFERENCE INPUT CLOCK - - 3 3 1.0 80 20 Phase-Jitter 3 ns max. Duty Cycle 40%min. to 60% max. % MHz ns 15 B-61 Phase-Jitter 1 ns max. Duty Cycle 42.5% min. to 57.5% max. - Frequency Error Maximum Frequency Propagation Delay for Pass Through Frequency Output Enable to Tristate (into and out of) time 10 10 - MCLK and VCLK TIMINGS Rise Time Tr Fall Time Tf - - ns ICS90C61A ICS90C61A Ordering Information ICS90C61A-XXXN ICS90C61A-XXXN or ICS90C61A-XXXM ICS90C61A-XXXM or ICS90C61A-XXXV ICS90C61A-XXXV Example: ICS XXXX-XXX N Package Type N=DIP (Plastic) M=SOIC V=PLCC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Note: Unless a specific pattern is ordered, PR2 will be shipped. Device Type (consists of 3-6 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device B-62