ICS8535I-01 8535AGI-01 ICS8535-01 20-PIN MO-153 ICS8535AI-01 8535AGI-01T - Datasheet Archive

 

LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535I-01 is a low skew, high

 

ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535I-01 ICS8535I-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS8535I-01 ICS8535I-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. · Four differential 3.3V LVPECL outputs · Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications · CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL · Maximum output frequency: 266MHz · Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels Guaranteed output and part-to-part skew characteristics make the ICS8535I-01 ICS8535I-01 ideal for those applications demanding well defined performance and repeatability. · Output skew: 30ps (maximum) · Part-to-part skew: 250ps (maximum) · Propagation delay: 1.9ns (maximum) · Jitter, RMS: < 0.09ps (typical) · 3.3V operating supply · -40°C to 85°C ambient operating temperature · Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VEE CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VCC D CLK_EN Q LE CLK0 0 CLK1 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8535I-01 ICS8535I-01 Q3 nQ3 8535AGI-01 8535AGI-01 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 4.4mm x 6.5mm x 0.92mm body package G Package Top View www.idt.com 1 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VEE Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK0 Input 6 5, 7, 8, 9 CLK1 nc Input Unused VCC Power 10, 13, 18 11, 12 14, 15 16, 17 19, 20 NOTE: Pullup Type Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. Pulldown LVCMOS / LVTTL clock input. No connect. Positive supply pins. nQ3, Q3 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. nQ2, Q2 Output nQ1, Q1 Output Differential output pair. LVPECL interface levels. nQ0, Q0 Output Differential output pair. LVPECL interface levels. and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k 8535AGI-01 8535AGI-01 Test Conditions www.idt.com 2 Minimum Typical Maximum Units REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN 0 CLK_SEL 0 Selected Source CLK0 Q0:Q3 Disabled; LOW nQ0:nQ3 Disabled; HIGH 0 1 CLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0 Enabled Enabled 1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B. Enabled Disabled CLK0, CLK1 CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK0 or CLK1 0 1 8535AGI-01 8535AGI-01 Outputs Q0:Q3 LOW HIGH nQ0:nQ3 HIGH LOW www.idt.com 3 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Minimum Typical Maximum Units 3.135 3.3 3.465 V Power Supply Current 55 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Maximum Units CLK0, CLK1 Test Conditions Minimum 2 Typical VCC + 0.3 V CLK_EN, CLK_SEL 2 VCC + 0.3 V CLK0, CLK1 -0.3 1.3 V CLK_EN, CLK_SEL -0.3 0.8 V 150 µA 5 µA CLK0, CLK1, CLK_SEL CLK_EN VIN = VCC = 3.465V VIN = VCC = 3.465V CLK0, CLK1, CLK_SEL VIN = 0V, VCC = 3.465V -5 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Test Conditions Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC - 1.4 0.9 V VCC - 2.0 VCC - 1.7 V 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCC - 2V. 8535AGI-01 8535AGI-01 www.idt.com 4 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Test Conditions Output Frequency Typical Units MHz tPD Propagation Delay; NOTE 1 1.9 ns t sk(o) Output Skew; NOTE 2, 4 30 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 250 ps tjit tR / tF 1.0 Maximum 266 266MHz Minimum 0.09 20% to 80% @ 50MHz 300 ps 700 odc Output Duty Cycle 48 50 52 All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8535AGI-01 8535AGI-01 www.idt.com 5 ps % REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power 0 -10 Additive Phase Jitter at 156.25MHz = 0.09ps (typical) -20 -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The 8535AGI-01 8535AGI-01 www.idt.com 6 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx SCOPE PART 1 nQx Qx LVPECL PART 2 nQy nQx VEE Qy tsk(pp) -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW nQx 80% 80% Qx VSW I N G Clock Outputs nQy 20% 20% tF tR Qy tsk(o) OUTPUT RISE/FALL TIME OUTPUT SKEW nQ0:nQ3 CLK0, CLK1 Q0:Q3 t PW t nQ0:nQ3 Q0:Q3 odc = tPD PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/ PULSE WIDTH/PERIOD PROPAGATION DELAY 8535AGI-01 8535AGI-01 www.idt.com 7 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVPECL OUTPUT: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. TERMINATION FOR LVPECL OUTPUTS drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50 125 FOUT 125 FIN Zo = 50 Zo = 50 FOUT 50 RTT = 1 Z (VOH + VOL) / (VCC ­ 2) ­ 2 o Zo = 50 VCC - 2V RTT 84 FIGURE 2A. LVPECL OUTPUT TERMINATION 8535AGI-01 8535AGI-01 FIN 50 84 FIGURE 2B. LVPECL OUTPUT TERMINATION www.idt.com 8 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER SCHEMATIC EXAMPLE Figure 3 shows a schematic example of the ICS8535I-01 ICS8535I-01. In this example, the CLK0 input is selected. The decoupling ca- pacitors should be physically located near the power pin. For ICS8535I-01 ICS8535I-01, the unused clock outputs can be left floating. Zo = 50 + Zo = 50 - 3.3V R2 50 R12 1K R1 50 3.3V U1 Q1 Ro ~ 7 Ohm R13 LVCMOS Zo = 50 Ohm 43 R11 1K 3.3V 1 2 3 4 5 6 7 8 9 10 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 VEE CLK_EN CLK_SEL CLK0 NC CLK1 NC NC NC VCC 20 19 18 17 16 15 14 13 12 11 R3 50 3.3V 3.3V C1 0.1u ICS8535-01 ICS8535-01 3.3V Zo = 50 C2 0.1u + C3 0.1u Zo = 50 R8 50 R7 50 R9 50 FIGURE 3. ICS8535I-01 ICS8535I-01 LVPECL BUFFER SCHEMATIC EXAMPLE 8535AGI-01 8535AGI-01 www.idt.com 9 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8535I-01 ICS8535I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535I-01 ICS8535I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. · · Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.6mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 120mW = 310.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.311W * 66.6°C/W = 105.7°C. This is well below the limit of 125°C. This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN 20-PIN TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8535AGI-01 8535AGI-01 www.idt.com 10 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC · For logic high, VOUT = V OH_MAX (V CC_MAX · ­ 0.9V OH_MAX OL_MAX CC_MAX CC_MAX ) = 0.9V -V For logic low, VOUT = V (V =V -V OL_MAX =V CC_MAX ­ 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX ­ (V CC_MAX - 2V)/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX )/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX ­ (V CC_MAX - 2V)/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX )/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8535AGI-01 8535AGI-01 www.idt.com 11 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8535I-01 ICS8535I-01 is: 412 8535AGI-01 8535AGI-01 www.idt.com 12 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A - 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0° 8° aaa - 0.10 0.75 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 MO-153 8535AGI-01 8535AGI-01 www.idt.com 13 REV. F OCTOBER 4, 2010 < ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8535AGI-01 8535AGI-01 ICS8535AI-01 ICS8535AI-01 20 lead TSSOP tube -40°C to 85°C 8535AGI-01T 8535AGI-01T ICS8535AI-01 ICS8535AI-01 20 lead TSSOP 2500 tape & reel -40°C to 85°C 8535AGI-01LF 8535AGI-01LF 8535AI01L 8535AI01L 20 lead "Lead Free" TSSOP tube -40°C to 85°C 8535AGI-01LFT 8535AGI-01LFT 8535AI01L 8535AI01L 20 lead "Lead Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8535AGI-01 8535AGI-01 www.idt.com 14 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER REVISION HISTORY SHEET Rev 8 4 1 Description of Change Added Termination for LVPECL Output section. Revised Marking on Ordering Information Table. Output Load Test Circuit - corrected VEE equation to read "VEE = -0.5V ± 0.165V" from "VEE = -0.5V ± 0.135V". AC Characteristics table - changed tsk(pp) from 200ps max. to 250ps. max. Update format. Added Schematic Example in the Application Section. LVPECL Table - changed VSWING 0.85V Max. to 1.0V Max. Added RMS Jitter to Features section. T2 A Table 2 4 Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Revised Absolute Maximum Ratings Output. T5 5 6 AC Characteritsics Table - added RMS Jitter. Added Additive Phase Jitter Section. Revised LVPECL Output Termination diagrams. Added "Lead Free" Par t/Order Number rows. Corrected Ambient Operating Temperature range from 0° - 70°C to -40°C - 85°C. Power Supply Current, changed IEE back to 55mA max. from 50mA max. Ordering Information Table - corrected temperature range. T9 A B 6 T5 C D Page 9 14 5 8 14 E E E 4 14 T9 14 T9 8 14 T4C E T4A T9 4 F F 8535AGI-01 8535AGI-01 10 - 11 T9 14 16 Date 5/29/02 10/4/02 12/16/02 1/20/03 12/4/03 1/14/04 6/24/04 Ordering Information Table - Lead-Free Marking from 8535AGI01L 8535AGI01L to 8535AI01L 8535AI01L. Added Recommendations for Unused Input and Output Pins Ordering Information Table - corrected marking from ICS8535AGI01 ICS8535AGI01 to ICS8535AI-01 ICS8535AI-01. LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCC - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4C. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Par t/Order Number column. Added Contact Page. www.idt.com 15 9/10/04 4/21/06 4/12/07 10/4/10 REV. F OCTOBER 4, 2010 ICS8535I-01 ICS8535I-01 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER We've Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8535AGI-01 8535AGI-01 www.idt.com 16 REV. F OCTOBER 4, 2010