ICS851021 ICS851021AY 1-TO-21 64-PIN MS-026 851021AY 851021AYT 851021AYLF - Datasheet Archive

 

0.7V HCSL Fanout Buffer ICS851021 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS851021 is a 1-to-21 Differential Current IC S

 

1-to-21, Differential Current Mode 0.7V HCSL Fanout Buffer ICS851021 ICS851021 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS851021 ICS851021 is a 1-to-21 Differential Current IC S Mode 0.7V HCSL Fanout Buffer. The ICS851021 ICS851021 is HiPerClockSTM designed to translate any differential input signal levels to 0.7V differential current mode HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resistor value is chosen to equal the value of the characteristic line impedance of 50. The ICS851021 ICS851021 is characterized at an operating supply voltage of 3.3V. · Twenty-one 0.7V differential HCSL clock outputs The 0.7V differential outputs, accurate crossover voltage and duty cycle makes the ICS851021 ICS851021 ideal for interfacing to PCI Express and FBDIMN applications. · Part-to-part skew: 335ps (maximum) · Translates any differential input signal (LVPECL, LVHSTL, LVDS, 0.7V DIFF) to differential current mode HCSL levels without external bias networks · Maximum output frequency: 250MHz · Single or dual output drive · Output skew: 395ps (maximum) · Additive phase jitter, RMS: 0.20ps (typical) · Output drift: 140ps (maximum) · VOH: 850mV (maximum) · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Q0 nQ0 Q20 nQ20 Q1 nQ1 Q19 nQ19 GND CLK nCLK VDD Q19 nQ19 Q20 nQ20 VDD Q0 nQ0 Q1 nQ1 nQ2 CLK nCLK VDD PIN ASSIGNMENT Q2 BLOCK DIAGRAM Q3 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 nQ3 2 47 Q18 3 46 VDD nQ18 Q2 nQ2 Q18 nQ18 VDD Q4 4 45 nQ17 Q3 nQ3 Q17 nQ17 nQ4 5 44 Q17 GND 6 43 GND Q5 7 42 nQ16 nQ5 8 41 Q16 40 VDD ICS851021 ICS851021 64-Lead TQFP, E-Pad 10mm x 10mm x 1.0mm package body Y package Top View Q4 nQ4 Q16 nQ16 Q5 nQ5 Q15 nQ15 VDD 9 Q6 10 39 nQ15 Q6 nQ6 Q14 nQ14 nQ6 11 38 Q15 Q7 12 37 nQ14 Q7 nQ7 Q13 nQ13 nQ7 13 36 Q14 VDD 14 35 VDD Q8 nQ8 Q12 nQ12 Q8 15 34 nQ13 Q9 nQ9 Q11 nQ11 Q13 GND nQ12 Q12 VDD nQ11 Q11 nc VDD VDD nQ10 Q10 VDD nQ9 Q10 nQ10 Q9 GND 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RREF nQ8 IREF ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 1 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 9, 14, 21, 24, 25, 29, 35, 40, 46, 52, 57, 62 4, 5 Name Q3, nQ3 Type Output Description Differential output pair. HCSL interface levels. VDD Power Core supply pins. Q4, nQ4 Output Differential output pair. HCSL interface levels. 6, 17, 32, 43, 49 GND Power Power supply ground. 7, 8 Q5, nQ5 Output Differential output pair. HCSL interface levels. 10, 11 Q6, nQ6 Output Differential output pair. HCSL interface levels. 1 2, 13 Q7, nQ7 Output Differential output pair. HCSL interface levels. 15, 16 Q8, nQ8 Output 18 IREF Input 19, 20 Q9, nQ9 Output Differential output pair. HCSL interface levels. External fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode Qx/nQx clock outputs. Differential output pair. HCSL interface levels. 22, 23 Q10, nQ10 Output Differential output pair. HCSL interface levels. 26 nc Unused No connect. 2 7, 28 30, 31 Q11, nQ11 Q12, nQ12 Output Output Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. 3 3, 34 36, 37 38, 39 41, 42 44, 45 47, 48 50 51 53, 54 5 5, 56 5 8, 59 60, 61 64, 63 Q13, nQ13 Q14, nQ14 Q15, nQ15 Q16, nQ16 Q17, nQ17 Q18, nQ18 CLK nCLK Q19, nQ19 Q20, nQ20 Q0, nQ0 Q1, nQ1 Q2, nQ2 Output Output Output Output Output Output Input Input Output Output Output Output Output Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Non inver ting differential clock input. Inver ting differential clock input. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. OUTPUT DRIVER CURRENT The ICS851021 ICS851021 outputs are HCSL differential current drive with the current being set with a resistor from IREF to ground. For a single load and a 50 p.c. board trace, the drive current would typically be set with a RREF of 950 which produces an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 1 for current mirror and output drive details. IREF RREF RL FIGURE 1. HCSL CURRENT MIRROR ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 2 RL AND OUTPUT DRIVE ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. -0.5V to VDD + 0.5V Package Thermal Impedance, JA 31.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Minimum Typical Maximum Units 3.135 3. 3 3.465 V Power Supply Current 105 mA Maximum Units TABLE 2B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions IIH Input High Current CLK, nCLK VDD = VIN = 3.465V 5 µA IIL Input Low Current CLK, nCLK VDD = 3.465V, VIN = 0V 5 µA 0.15 1.3 V GND + 0.5 VDD ­ 0.85 V VPP Peak-to-Peak Input Voltage Common Mode Input Voltage; VCMR NOTE 1 NOTE 1: Common mode voltage is defined as VIH. ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 3 Minimum Typical ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER TABLE 3. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency t PD tsk(o) Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section Output Skew; NOTE 2, 3 395 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 335 ps tsk(drift) Output Drift; NOTE 5 140 ps tjit Test Conditions Typical Units MHz 2.75 1.5 Maximum 250 Measured on at VOX CLK = 200MHz, (Integration Range: 12kHz ­ 30MHz) Measured on at VOX Minimum ns 0.20 ps VMAX Voltage High; NOTE 6 150MHz 500 850 mV VMIN Voltage Low; NOTE 6 150MHz -150 150 mV 250 550 mV 140 mV 4. 0 V/ns 20 % VCROSS Absolute Crossing Voltage VCROSS Total Variation of VCROSS over all edges Rise/Fall Edge Rate: NOTE 7, 8 tR /tF 0.6 Rise/Fall Time Matching; NOTE 9 odc Output Duty Cycle; NOTE 10 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Current adjust set for VOH = 0.7V. Measurements refer to PCIEX outputs only. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Output Drift is measured as the change in the time placement of the differential crosspoint for each output on a given device due to a change in temperature and supply voltage. Measured at the differential cross points. NOTE 6: Measurement using RREF = to 950, RLOAD = to 50. NOTE 7: Measurement taken from differential waveform. NOTE 8: Measured from -150mV to +150mV on the differential waveform (derived from CLK minus nCLK). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 9: Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a ±75mV window centered on the median cross point where Qx rising meets nQx falling. NOTE 10: Assuming 50% input duty cycle. Data taken at 200MHz, unless otherwise specified. ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 4 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz SSB PHASE NOISE dBc/HZ Input/Output Additive Phase Jitter at 200MHz (12kHz - 30MHz) = 0.20ps (typical) OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 5 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V VDD VDD 50 33 Measurement Point nCLK 49.9 2pF HCSL V Cross Points PP 50 33 GND Measurement Point 49.9 V CMR CLK GND 2pF 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 nQx Qx Qx nQy PART 2 nQy Qy Qy tsk(pp) tsk(o) OUTPUT SKEW Rise Edge Rate PART-TO-PART SKEW TSTABLE Fall Edge Rate VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV +150mV 0.0V -150mV Q - nQ Q - nQ VRB TSTABLE DIFFERENTIAL MESUREMENT POINTS FOR RINGBACK DIFFERENTIAL MESUREMENT POINTS FOR RISE/FALL TIME ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 6 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION, CONTINUED nQ nQ tFALL tRISE VCROSS_MEDIAN +75mV VCROSS_MEDIAN VCROSS_MEDIAN VCROSS_MEDIAN -75mV Q Q SE MESUREMENT POINTS FOR RISE/FALL TIME MATCHING VMAX = 1.15V nQ nQ VCROSS_MAX = 550mV VCROSS_DELTA = 140mV VCROSS_MIN = 250mV Q Q VMIN = -0.30V SE MESUREMENT POINTS FOR DELTA CROSS POINT SE MESUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.0V Q - nQ DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 7 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the singleended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: DIFFERENTIAL OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 8 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK CLK Zo = 50 nCLK Zo = 50 nCLK Differential Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver Differential Input LVPECL R2 50 R1 50 R2 50 R2 50 FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER LVHSTL DRIVER FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 Zo = 50 Zo = 50 CLK CLK R1 100 Zo = 50 nCLK R1 84 Zo = 50 Differential Input LVPECL R2 84 FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER nCLK Receiver LVDS FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V *R3 33 Zo = 50 CLK Zo = 50 nCLK HCSL *R4 33 R1 50 R2 50 Differential Input *Optional ­ R3 and R4 can be 0 FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 9 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD FIGURE 4. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH ­SIDE VIEW (DRAWING NOT TO SCALE) ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 10 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER RECOMMENDED TERMINATION Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance. 0.7V Differential HCSL Add-In Card 0.7V Differential HCSL Clock Driver FIGURE 5A. RECOMMENDED TERMINATION Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50 impedance. 0.7V Differential HCSL Clock Driver FIGURE 5B. RECOMMENDED TERMINATION ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 11 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS851021 ICS851021. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS851021 ICS851021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. · · Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 105mA = 363.83mW Power (outputs)MAX = 47.3mW/Loaded Output pair If all outputs are loaded, the total power is 21 * 47.3mW = 993.3mW Total Power_MAX (3.465V, with all outputs switching) = 363.83mW + 993.3mW = 1357.13mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 31.8°C/W per Table 4 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.357W * 31.8°C/W = 113.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 4. THERMAL RESISTANCE JA FOR 64-PIN 64-PIN TQFP, FORCED CONVECTION JA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 1 2.5 31.8°C/W 25.8°C/W 24.2°C/W 12 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. VDD IOUT = 17mA VOUT RREF = 475 ± 1% RL 50 IC FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD is HIGH. Power = (VDD_HIGH ­ VOUT ) * IOUT, since VOUT = IOUT * RL = (VDD_HIGH ­ IOUT * RL) * IOUT = (3.63V ­ 17mA * 50) * 17mA Total Power Dissipation per output pair = 47.3mW ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 13 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD JA by Velocity (Meters Per Second) 0 2.5 31.8°C/W Multi-Layer PCB, JEDEC Standard Test Boards 1 25.8°C/W 24.2°C/W TRANSISTOR COUNT The transistor count for ICS851021 ICS851021 is: 843 ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 14 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, E-PAD -HD VERSION EXPOSED PAD DOWN TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL ACD-HD MINIMUM NOMINAL MAXIMUM 64 N A - - 1.20 A1 0.05 0.10 0.15 A2 0.95 1.0 1.05 b 0.17 0.22 0.27 c 0.09 - 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.50 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 0° - 7° ccc - - 0.08 D3 & E3 4.5 - 5.5 Reference Document: JEDEC Publication 95, MS-026 MS-026 ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 15 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 851021AY 851021AY ICS851021AY ICS851021AY 64 lead TQFP, E-Pad tray 0°C to 70°C 851021AYT 851021AYT ICS851021AY ICS851021AY 64 lead TQFP, E-Pad 500 tape & reel 0°C to 70°C 851021AYLF 851021AYLF ICS851021AYLF ICS851021AYLF 64 Lead "Lead-Free" TQFP, E-Pad tray 0°C to 70°C 851021AYLFT 851021AYLFT ICS851021AYLF ICS851021AYLF 64 Lead "Lead-Free" TQFP, E-Pad 500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 16 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER REVISION HISTORY SHEET Rev Table B T1 T3 B T6 Page 1 2 12 4 8 9 15 Description of Change Pin Assignment, corrected pin 25 from VDDA to VDD. Pin Description Table - deleted VDDA (pin #25) row, and added pin #25 to VDD row. Power Considerations - corrected total power calculation and Tj calculation. AC Characteristics Table - added Thermal note. Updated Wiring the Differential Input to Accept Single Ended Levels. Updated Differential Clock Input Interface. Package Dimensions - corrected D3 & E3 dimensions. Updated datasheet's Head/Footer. ICS851021AY ICS851021AY REVISION B MARCH 3, 2010 17 Date 5/25/08 3/3/10 ©2010 Integrated Device Technology, Inc. ICS851021 ICS851021 Data Sheet 1-TO-21 1-TO-21, DIFFERENTIAL CURRENT MODE 0.7V HCSL FANOUT BUFFER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.