ICS527-03 ICS527-04 - Datasheet Archive

 

Integrated Circuit Systems, Inc. USER CONFIGURABLE PECL OUTPUT ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS527-03 is

 

ICS527-03 ICS527-03 Integrated Circuit Systems, Inc. USER CONFIGURABLE PECL OUTPUT ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS527-03 ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-03 ICS527-03 aligns rising edges on ICLK with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the ICS527-04 ICS527-04. · · · · · · · · · · · · · PIN ASSIGNMENT R5 1 28 R4 R6 2 27 R3 D IV 2 3 26 R2 S0 4 25 R1 S1 5 24 Packaged as 28 pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5MHz-200MHz Output clock frequencies from 2.5MHz to 160MHz Very low jitter Duty cycle of 45/55 Operating voltage of 3.3V Advanced, low power CMOS process R0 VDD VDD 6 23 FBPECL 7 22 PECL FBPECL 8 21 OUTPUT FREQUENCY AND OUTPUT DIVIDER TABLE PECL S1 S0 Output Divider Output Frequency (MHz) 0 2 10 - 80 9 20 GND 0 C L K IN 10 19 RES 0 1 4 5 - 40 PDTS 11 18 F6 1 0 8 2.5 - 20 F0 12 17 F5 F1 13 16 F4 1 1 1 20 -160 F2 14 15 F3 GND BLOCK DIAGRAM R6:R0 VDD R 7 ICLK Divide by 2 1 0 VDD FBPECL RES Reference Divider R FBPECL Phase Comparator, Charge Pump, and Loop Filter Divide by 2 VDD 2 PECL VCO Output Divider PECL 1 0 Feedback Divider DIV2 7 F6:F0 2 GND PDTS 2 S1:S0