ICS1893AF ICS1893Y-10 100M/MII 10TCSR 100TCSR ICS1893AFLF ICS1893AFILF ICS1890 - Datasheet Archive

 

Document Type: ICS1893AF Data Sheet Document Stage: Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiverTM General The

 

Integrated Circuit Systems, Inc. Document Type: ICS1893AF ICS1893AF Data Sheet Document Stage: Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiverTM General The ICS1893AF ICS1893AF is a lower cost, re-packaged version of the ICS1893Y-10 ICS1893Y-10. The ICS1893AF ICS1893AF is a fully integrated, Physical Layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The ICS1893AF ICS1893AF uses the same proven silicon as the ICS1893Y-10 ICS1893Y-10 but offers a lower cost solution by using a lower cost 300 mil. 48-lead SSOP package. The ICS1893AF ICS1893AF uses the same twisted-pair transmit and receive circuits as the ICS1893Y-10 ICS1893Y-10, and the same recommended board layout techniques apply to the ICS1893AF ICS1893AF. The ICS1893AF ICS1893AF is intended for Node applications using the standard MII interface to the MAC. All differences in the ICS1893AF ICS1893AF / ICS1893Y-10 ICS1893Y-10 Feature Set are listed in the Comparison Table on page 14. Features · Single 3.3V power supply · Supports category 5 cables with attenuation in excess of · · · · · · · · · · · · 24dB at 100 MHz. DSP-based baseline wander correction to virtually eliminate killer packets Low-power, 0.35-micron CMOS (typically 400 mW) Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard 10Base-T and 100Base-TX IEEE 802.3 compliant Clock or crystal supported Media Independent Interface (MII) supported Managed or Unmanaged Applications 10M or 100M Half and Full Duplex Modes Auto-Negotiation with Parallel detection for Legacy products Fully integrated, DSP-based PMD includes: ­ Adaptive equalization and baseline wander correction ­ Transmit wave shaping and stream cipher scrambler ­ MLT-3 encoder and NRZ/NRZI encoder Loopback mode for Diagnostic Functions Small footprint 48-pin 300 mil SSOP package. Available in Industrial Temperature and Lead Free packaging. ICS1893AF ICS1893AF Block Diagram 100Base-T 10/100 MII MAC Interface Interface MUX PCS · Framer · CRS/COL Detection · Parallel to Serial · 4B/5B PMA · Clock Recovery · Link Monitor · Signal Detection · Error Detection TP_PMD · MLT-3 · Stream Cipher · Adaptive Equalizer · Baseline Wander Correction Integrated Switch Configuration and Status AutoNegotiation 10Base-T MII Serial Management Interface MII Extended Register Set Low-Jitter Clock Synthesizer Clock ICS1893AF ICS1893AF, Rev. F 05/13/10 Power TwistedPair Interface to Magnetics Modules and RJ45 Connector LEDs and PHY Address ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Octobe ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Title Page Revision History . 9 Chapter 1 Abbreviations and Acronyms . 10 Chapter 2 Conventions and Nomenclature. 12 Chapter 3 Typical ICS1893AF ICS1893AF Applications. 14 3.1 ICS1893AF ICS1893AF / ICS1893Y-10 ICS1893Y-10 Pin Differences .14 3.2 ICS1893AF ICS1893AF / ICS1893Y-10 ICS1893Y-10 Shared Features .15 Chapter 4 4.1 4.2 Overview of the ICS1893AF ICS1893AF. 16 100Base-TX Operation .17 10Base-T Operation .17 Chapter 5 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 5.6 5.7 Operating Modes Overview. 18 Reset Operations .19 General Reset Operations .19 Specific Reset Operations .20 Power-Down Operations .21 Automatic Power-Saving Operations .22 Auto-Negotiation Operations .22 100Base-TX Operations .23 10Base-T Operations .23 Half-Duplex and Full-Duplex Operations .23 Chapter 6 6.1 6.2 6.3 6.3.1 6.3.2 6.4 6.5 Interface Overviews. 24 MII Data Interface .25 Serial Management Interface .26 Twisted-Pair Interface .26 Twisted-Pair Transmitter Interface .27 Twisted-Pair Receiver Interface .28 Clock Reference Interface .29 Status Interface .31 Chapter 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Functional Blocks. 33 Functional Block: Media Independent Interface .34 Functional Block: Auto-Negotiation .35 Auto-Negotiation General Process .36 Auto-Negotiation: Parallel Detection .37 Auto-Negotiation: Remote Fault Signaling .37 Auto-Negotiation: Reset and Restart .38 Auto-Negotiation: Progress Monitor .38 ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 2 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 7.6 7.6.1 7.6.2 Title Page Functional Block: 100Base-X PCS and PMA Sublayers .40 PCS Sublayer .40 PMA Sublayer .40 PCS/PMA Transmit Modules .41 PCS/PMA Receive Modules .42 PCS Control Signal Generation .43 4B/5B Encoding/Decoding .43 Functional Block: 100Base-TX TP-PMD Operations .44 100Base-TX Operation: Stream Cipher Scrambler/Descrambler .44 100Base-TX Operation: MLT-3 Encoder/Decoder .44 100Base-TX Operation: DC Restoration .44 100Base-TX Operation: Adaptive Equalizer .45 100Base-TX Operation: Twisted-Pair Transmitter .45 100Base-TX Operation: Twisted-Pair Receiver .45 100Base-TX Operation: Auto Polarity Correction .46 100Base-TX Operation: Isolation Transformer .46 Functional Block: 10Base-T Operations .47 10Base-T Operation: Manchester Encoder/Decoder .47 10Base-T Operation: Clock Synthesis .47 10Base-T Operation: Clock Recovery .47 10Base-T Operation: Idle .48 10Base-T Operation: Link Monitor .48 10Base-T Operation: Smart Squelch .49 10Base-T Operation: Carrier Detection .49 10Base-T Operation: Collision Detection .49 10Base-T Operation: Jabber .50 10Base-T Operation: SQE Test .50 10Base-T Operation: Twisted-Pair Transmitter .51 10Base-T Operation: Twisted-Pair Receiver .51 10Base-T Operation: Auto Polarity Correction .51 10Base-T Operation: Isolation Transformer .51 Functional Block: Management Interface .52 Management Register Set Summary .52 Management Frame Structure .52 ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 3 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Chapter 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 Title Page Management Register Set . 55 Introduction to Management Register Set .56 Management Register Set Outline .56 Management Register Bit Access .57 Management Register Bit Default Values .57 Management Register Bit Special Functions .58 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 Register 0: Control Register .59 Reset (bit 0.15) .59 Loopback Enable (bit 0.14) .60 Data Rate Select (bit 0.13) .60 Auto-Negotiation Enable (bit 0.12) .60 Low Power Mode (bit 0.11) .61 Isolate (bit 0.10) .61 Restart Auto-Negotiation (bit 0.9) .61 Duplex Mode (bit 0.8) .62 Collision Test (bit 0.7) .62 IEEE Reserved Bits (bits 0.6:0) .62 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 Register 1: Status Register .63 100Base-T4 (bit 1.15) .63 100Base-TX Full Duplex (bit 1.14) .64 100Base-TX Half Duplex (bit 1.13) .64 10Base-T Full Duplex (bit 1.12) .64 10Base-T Half Duplex (bit 1.11) .64 IEEE Reserved Bits (bits 1.10:7) .65 MF Preamble Suppression (bit 1.6) .65 Auto-Negotiation Complete (bit 1.5) .65 Remote Fault (bit 1.4) .66 Auto-Negotiation Ability (bit 1.3) .66 Link Status (bit 1.2) .67 Jabber Detect (bit 1.1) .67 Extended Capability (bit 1.0) .67 8.4 Register 2: PHY Identifier Register .68 ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 4 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Title Page 8.5 8.5.1 8.5.2 8.5.3 Register 3: PHY Identifier Register .70 OUI bits 19-24 (bits 3.15:10) .70 Manufacturer's Model Number (bits 3.9:4) .71 Revision Number (bits 3.3:0) .71 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 Register 4: Auto-Negotiation Register .72 Next Page (bit 4.15) .72 IEEE Reserved Bit (bit 4.14) .72 Remote Fault (bit 4.13) .73 IEEE Reserved Bits (bits 4.12:10) .73 Technology Ability Field (bits 4.9:5) .74 Selector Field (Bits 4.4:0) .75 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 Register 5: Auto-Negotiation Link Partner Ability Register .76 Next Page (bit 5.15) .76 Acknowledge (bit 5.14) .77 Remote Fault (bit 5.13) .77 Technology Ability Field (bits 5.12:5) .77 Selector Field (bits 5.4:0) .77 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 Register 6: Auto-Negotiation Expansion Register .78 IEEE Reserved Bits (bits 6.15:5) .78 Parallel Detection Fault (bit 6.4) .79 Link Partner Next Page Able (bit 6.3) .79 Next Page Able (bit 6.2) .79 Page Received (bit 6.1) .79 Link Partner Auto-Negotiation Able (bit 6.0) .79 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 8.9.6 Register 7: Auto-Negotiation Next Page Transmit Register .80 Next Page (bit 7.15) .81 IEEE Reserved Bit (bit 7.14) .81 Message Page (bit 7.13) .81 Acknowledge 2 (bit 7.12) .81 Toggle (bit 7.11) .81 Message Code Field / Unformatted Code Field (bits 7.10:0) .81 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 Register 8: Auto-Negotiation Next Page Link Partner Ability Register .82 Next Page (bit 8.15) .83 IEEE Reserved Bit (bit 8.14) .83 Message Page (bit 8.13) .83 Acknowledge 2 (bit 8.12) .83 Message Code Field / Unformatted Code Field (bits 8.10:0) .83 ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 5 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Title Page 8.11 8.11.1 8.11.2 8.11.3 8.11.4 8.11.5 8.11.6 8.11.7 8.11.8 8.11.9 Register 16: Extended Control Register .84 Command Override Write Enable (bit 16.15) .85 ICS Reserved (bits 16.14:11) .85 PHY Address (bits 16.10:6) .85 Stream Cipher Scrambler Test Mode (bit 16.5) .85 ICS Reserved (bit 16.4) .85 NRZ/NRZI Encoding (bit 16.3) .85 Invalid Error Code Test (bit 16.2) .86 ICS Reserved (bit 16.1) .86 Stream Cipher Disable (bit 16.0) .86 8.12 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 8.12.8 8.12.9 8.12.10 8.12.11 8.12.12 8.12.13 8.12.14 Register 17: Quick Poll Detailed Status Register .87 Data Rate (bit 17.15) .88 Duplex (bit 17.14) .88 Auto-Negotiation Progress Monitor (bits 17.13:11) .89 100Base-TX Receive Signal Lost (bit 17.10) .89 100Base PLL Lock Error (bit 17.9) .90 False Carrier (bit 17.8) .90 Invalid Symbol (bit 17.7) .90 Halt Symbol (bit 17.6) .91 Premature End (bit 17.5) .91 Auto-Negotiation Complete (bit 17.4) .91 100Base-TX Signal Detect (bit 17.3) .91 Jabber Detect (bit 17.2) .92 Remote Fault (bit 17.1) .92 Link Status (bit 17.0) .92 8.13 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5 8.13.6 8.13.7 8.13.8 8.13.9 Register 18: 10Base-T Operations Register .93 Remote Jabber Detect (bit 18.15) .93 Polarity Reversed (bit 18.14) .94 ICS Reserved (bits 18.13:6) .94 Jabber Inhibit (bit 18.5) .94 ICS Reserved (bit 18.4) .94 Auto Polarity Inhibit (bit 18.3) .94 SQE Test Inhibit (bit 18.2) .94 Link Loss Inhibit (bit 18.1) .95 Squelch Inhibit (bit 18.0) .95 ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 6 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section 8.14 8.14.1 8.14.2 8.14.3 8.14.4 8.14.5 8.14.6 8.14.7 Title Page Register 19: Extended Control Register 2 .96 Node/Repeater Configuration (bit 19.15) .97 Hardware/Software Priority Status (bit 19.14) .97 Remote Fault (bit 19.13) .97 ICS Reserved (bits 19.12:8) .97 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) .97 ICS Reserved (bits 19.6:1) .97 Automatic 100Base-TX Power-Down (bit 19.0) .97 Chapter 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 Pin Diagram, Listings, and Descriptions . 98 ICS1893AF ICS1893AF Pin Diagram .98 ICS1893AF ICS1893AF Pin Descriptions .99 Transformer Interface Pins .100 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .101 Configuration Pins.104 MAC Interface Pins .105 Ground and Power Pins.109 Chapter 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 10.5.8 10.5.9 10.5.10 10.5.11 10.5.12 10.5.13 DC and AC Operating Conditions. 110 Absolute Maximum Ratings .110 Recommended Operating Conditions .110 Recommended Component Values .111 DC Operating Characteristics .112 DC Operating Characteristics for Supply Current .112 DC Operating Characteristics for TTL Inputs and Outputs .112 DC Operating Characteristics for REF_IN .113 DC Operating Characteristics for Media Independent Interface .113 Timing Diagrams .114 Timing for Clock Reference In (REF_IN) Pin .114 Timing for Transmit Clock (TXCLK) Pins .115 Timing for Receive Clock (RXCLK) Pins .116 100M MII: Synchronous Transmit Timing .117 10M MII: Synchronous Transmit Timing .118 100M/MII 100M/MII Media Independent Interface: Synchronous Receive Timing .119 MII Management Interface Timing .120 10M Media Independent Interface: Receive Latency .121 10M Media Independent Interface: Transmit Latency.122 100M/MII 100M/MII Media Independent Interface: Transmit Latency.123 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission).124 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission).125 100M MII Media Independent Interface: Receive Latency.126 ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 7 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Title 10.5.14 10.5.15 10.5.16 10.5.17 10.5.18 10.5.19 10.5.20 Chapter 11 Chapter 12 Page 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion .127 Reset: Power-On Reset .128 Reset: Hardware Reset and Power-Down .129 10Base-T: Heartbeat Timing (SQE) .130 10Base-T: Jabber Timing .131 10Base-T: Normal Link Pulse Timing .132 Auto-Negotiation Fast Link Pulse Timing .133 Physical Dimensions of ICS1893AF ICS1893AF Package . 134 Ordering Information . 135 ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 8 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Revision History Revision History · The initial release of this document was dated 5 April 2002. · This release of this document, Rev B, is dated 6 March 2003. The following list indicates where changes occur. ­ Table of Contents reflect page renumbering. ­ Figure 6-3, "Crystal or Oscillator Operation", corrected 33 pF to 33 Ohm in Oscillator operation. ­ Section 7.5.5. "When the 10Base-T link is:, Invalid / Valid Smart Squelch function". Changed each "logic" number from zero to one, or the reverse. ­ Table 8-10, changed "Decimal" revision number from 0 to 1. ­ Table 8-11, deleted "Note 1" at foot of table. On bits 4.5 through 4.8, replaced "Note 1" notation in "Access" column with R/W. ­ Section 8.14. Deleted two paragraphs made redundant by change made to Table 8-21. ­ Table 8-21, Bit 19.5, changed "Force LEDs On" to "ICS Reserved". ­ Table 9-6, revised P3TD Pin 6 and P4RD Pin 8 Pin Description. ­ Table 10-3, "Note" paragraph deleted. ­ Figure 10-1, deleted capacitors across resistors 10TCSR 10TCSR and 100TCSR 100TCSR. ­ Table 10-4, changed "Supply Current Power-Down" IDD from 40 to 4 (Typ) and from 50 to 5 (Max). In addition, changed "Supply Current Reset" IDD from 50 to 10 (Typ) and from 60 to 11 (Max). ­ Figure 12-1, "Package Type" added AFI = 48 Lead 300 mil. SSOP Industrial Temp. · This release of this document, Rev. C, is dated 4 June 2003. · This release of this document, Rev. D, is dated 25 October 2004. The following list indicates where changes occur. ­ Table 6-1, 25MHz Crystal Specification revised. ­ Table 6-2, 25MHz Oscillator Specification revised. ­ Section 6.5, Status Interface. First sentence in paragraph deleted. Reference deleted to Rev. C in second sentence. ­ Table 8-18, Bit 17.3 signal present / no signal present entries reversed. Corrected. ­ Table 9-8, Pin RXD3 number "29" incorrect. Corrected. ­ Table 10-6, Min and Max column entries incorrect. Corrected. ­ Figure 12-1, "Odering Information" added part number ICS1893AFLF ICS1893AFLF = 48 Lead 300 mil. SSOP Lead Free Commercial Temperature package and part number ICS1893AFILF ICS1893AFILF = 48 Lead 300 mil. SSOP Lead Free Industrial Temperature package. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 9 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym Interpretation 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor CSMA/CD Carrier Sense Multiple Access with Collision Detection CW Command Override Write DSP digital signal processing ESD End-of-Stream Delimiter FDDI Fiber Distributed Data Interface FLL frequency-locked loop FLP Fast Link Pulse IDL A `dead' time on the link following a 10Base-T packet, not to be confused with idle IEC International Electrotechnical Commission IEEE Institute of Electrical and Electronic Engineers ISO International Standards Organization LH Latching High LL Latching Low LMX Latching Maximum MAC Media Access Control Max. maximum Mbps Megabits per second MDI Media Dependent Interface MF Management Frame MII Media Independent Interface Min. minimum MLT-3 Multi-Level Transition Encoding (3 Levels) N/A Not Applicable NLP Normal Link Pulse No. Number NRZ Not Return to Zero NRZI Not Return to Zero, Invert on one ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 10 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym Interpretation OSI Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893AF ICS1893AF is a physical-layer device, also referred to as a `PHY' or `PHYceiver'. (The ICS1890 ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ppm parts per million QFP quad flat pack RO read only R/W read/write R/W0 read/write zero SC self-clearing SF Special Functions SFD Start-of-Frame Delimiter SI Stream Interface, Serial Interface, or Symbol Interface. With reference to the MII/SI pin, the acronym `SI' has multiple meanings. · Generically, SI means 'Stream Interface', and is documented as such in this data sheet. · However, when the MAC/Repeater Interface is configured for: ­ 10M operations, SI is an acronym for 'Serial Interface'. ­ 100M operations, SI is an acronym for 'Symbol Interface'. SQE Signal Quality Error SSD Start-of-Stream Delimiter STA Station Management Entity STP shielded twisted pair TAF Technology Ability Field TP-PMD Twisted-Pair Physical Layer Medium Dependent Typ. typical UTP unshielded twisted pair ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 11 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 2 Conventions and Nomenclature Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Convention / Nomenclature · A bit in a register is identified using the format `register.bit'. For example, bit 0.15 is bit 15 of register 0. · When a colon is used with bits, it indicates the range of bits. For example, bits 1.15:11 are bits 15, 14, 13, 12, and 11 of register 1. · For a range of bits, the order is always from the most-significant bit to the least-significant bit. Code groups Within this table, see the item `Symbols' Colon (:) Within this table, see these items: · `Bits' · `Pin (or signal) names' Numbers · As a default, all numbers use the decimal system (that is, base 10) unless · Pin (or signal) names followed by a lowercase letter. A string of numbers followed by a lowercase letter: ­ A `b' represents a binary (base 2) number ­ An `h' represents a hexadecimal (base 16) number ­ An `o' represents an octal (base 8) number All numerical references to registers use decimal notation (and not hexadecimal). · All pin or signal names are provided in capital letters. · A pin name that includes a forward slash `/' is a multi-function, configuration pin. These pins provide the ability to select between two ICS1893AF ICS1893AF functions. The name provided: ­ Before the `/' indicates the pin name and function when the signal level on the pin is logic zero. ­ After the `/' indicates the pin name and function when the signal level on the pin is logic one. For example, the HW/SW pin selects between Hardware (HW) mode and Software (SW) mode. When the signal level on the HW/SW pin is logic: ­ Zero, the ICS1893AF ICS1893AF Hardware mode is selected. ­ One, the ICS1893AF ICS1893AF Software mode is selected. · An `n' appended to the end of a pin name or signal name (such as RESETn) indicates an active-low operation. · When a colon is used with pin or signal names, it indicates a range. For example, TXD[3:0] represents pins/signals TXD3, TXD2, TXD1, and TXD0. · When pin name abbreviations are spelled out, words in parentheses indicate additional description that is not part of the pin name abbreviation. Registers · A bit in a register is identified using the format `register.bit'. For example, bit 0.15 is bit 15 of register 0. · All numerical references to registers use decimal notation (and not hexadecimal). · When register name abbreviations are spelled out, words in parentheses indicate additional description that is not part of the register name abbreviation. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 12 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 2 Conventions and Nomenclature Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Convention / Nomenclature · When referring to signals, the terms: · Symbols ­ `FALSE', `low', or `zero' represent signals that are logic zero. ­ `TRUE', `high', or `one' represent signals that are logic one. Chapter 10, "DC and AC Operating Conditions" defines the electrical specifications for `logic zero' and `logic one' signals. · In this data sheet, code group names are referred to as `symbols' and they · are shown between '/' (slashes). For example, the symbol /J/ represents the first half of the Start-of-Stream Delimiter (SSD1). Symbol sequences are shown in succession. For example, /I/J/K/ represents an IDLE followed by the SSD. Terms: `set', `active', `asserted', The terms `set', `active', and `asserted' are synonymous. They do not necessarily infer logic one. (For example, an active-low signal can be set to logic zero.) Terms: `cleared', `de-asserted', `inactive' The terms `cleared', `inactive', and `de-asserted' are synonymous. They do not necessarily infer logic zero. Terms: `twisted-pair receiver' In reference to the ICS1893AF ICS1893AF, the term `Twisted-Pair Receiver' refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). Terms: `twisted-pair transmitter' In reference to the ICS1893AF ICS1893AF, the term `Twisted-Pair Transmitter' refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 13 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 3 Typical ICS1893AF ICS1893AF Applications Chapter 3 Typical ICS1893AF ICS1893AF Applications The ICS1893AF ICS1893AF is configured for the majority of single Phy Ethernet applications. These applications include Network Interface Cards, PC Motherboards, Printers, ACR Riser cards, Set top Boxes, and Game machines. Virtually any single Phy application utilizing the standard IEEE MII interface can use the ICS1893AF ICS1893AF. The ICS1893AF ICS1893AF offers the same high performance at a lower cost. Table 3-1. ICS1893AF ICS1893AF / ICS1893Y-10 ICS1893Y-10 Feature Set Comparison Table Feature ICS1893AF ICS1893AF ICS1893Y-10 ICS1893Y-10 Comment Package Type SSOP 300mil TQFP 10x10x1.0 Pin Count 48 64 NOD/REP NOD/REP NOD/REP pin removed tied internally to VSS ICS1893AF ICS1893AF configured in NODE mode only. HW/SW MII/SI pin removed tied internally to VDD MII/SI ICS1893AF ICS1893AF configured in software mode only. MII/SI SI/MII pin removed tied internally to VSS SI/MII ICS1893AF ICS1893AF supports only MII interface to MAC. 10/100 10/100 pin is output only 10/100 The 10/100 pin in software mode is an output indicating 100M operation when high. DPXSEL DPXSEL pin removed DPXSEL FD/HD information is available in the Quick Poll Status Register Reg 17. ANSEL DPXSEL pin removed ANSEL ANSEL in software mode is an output. This information is available in control Reg 0, Default setting is A-N enabled. LSTA LSTA pin removed LSTA Link status available on P2LI led LOCK LOCK pin removed LOCK Link status available on P2LI led TXER TXER pin removed tied internally to VSS TXER TXER function is still available by using control Reg 3.1 The following bullet items describe ICS1893AF ICS1893AF pin differences and how they affect the application: · The ICS1893AF ICS1893AF is hardwired for the predominate board application used in the vast majority of single Phy applications: ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 14 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 3 Typical ICS1893AF ICS1893AF Applications ­ Hardwired for Node configuration (NOD/REP pin removed, tied internally to VSS). Node configuration enables the 10M SQE test default setting and causes CRS to be asserted for either transmit or receive activity in half duplex, or for just receive activity when in full duplex. ­ Hardwired for Software mode (HW/SW pin removed, tied internally to VDD). ­ Hardwired for MII interface only. (MII/SI pin removed, tied internally to VSS). In this configuration the 10baseT serial and 100baseTX 5 bit symbol interfaces are NOT supported. Applications requiring these interfaces should use ICS1893Y-10 ICS1893Y-10. · In the software control configuration the 10/100, DPXSEL and ANSEL pins are outputs. ­ DPXEL pin is not brought out. ­ ANSEL pin is not brought out. ­ 10/100 pin is brought out to indicate 100M operation. Some applications use this output to drive an LED indicating 100M operation. · Pins LSTA (link status) and LOCK (rec. PLL locked) are not brought out. ­ LSTA and LOCK provided redundant information already available with the P2LI pin. P2LI indicates the Link is valid. · Input pin TXER is removed and tied low inside the package. The TXER function is still available by using the Extended Control Register Reg 16 Bit 2. Most applications tied the TXER pin to VSS. 3.2 ISC1893AF ISC1893AF Shared Features · The same silicon die is used in the ICS1893AF ICS1893AF and ICS1893Y-10 ICS1893Y-10 ­ Only the package type is different. · The ICS1893AF ICS1893AF offers the same.35µ 3.3V low power operation. · Parametric specifications and timing diagrams are the same as ICS1893Y-10 ICS1893Y-10. · Both the ICS1893Y-10 ICS1893Y-10 and the ICS1893AF ICS1893AF incorporate Digital Signal Processing in their PMD Sub layer, thereby allowing them to transmit and receive data with Unshielded Twisted Pair (UTP) Category 5 cables up to 150 meters in length. In addition, this ICS-patented technology enables the ICS1893Y-10 ICS1893Y-10 ICS1893AF ICS1893AF to address the effects of Baseline Wander correction. · Both ICS1893AF ICS1893AF and ICS1893Y-10 ICS1893Y-10 have improved 10Base-T Squelch operation. · The ICS1893AF ICS1893AF uses the same twisted pair transmitter and receive circuits and therefore the same recommended board layout techniques apply. · Both share improved transmit circuits resulting in a decrease in the magnitude of the 10Base-T harmonic content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3). · Both use digital PLL technology resulting in lower jitter and improved stability. · The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are preserved in the ICS1893AF ICS1893AF. This enables software configuring for FD/HD, 10Base-T, 100Base-TX and Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is Auto-Negotiation Enable. All register settings are the same as in the ICS1893AF ICS1893AF datasheet. · The ICS1893AF ICS1893AF preserves the dual-purpose LED/Phy Address control pins as in the ICS1893Y-10 ICS1893Y-10. The captured address seeds the scrambler for lower EMI in for multiple Phy applications. · All Auto-Negotiation features are preserved in the ICS1893AF ICS1893AF. The reset default mode is A_N enabled. The A_N parallel detect feature is preserved for legacy interoperability. · Both support Management Frame (MF) Preamble Suppression. · Both support backward compatibility with the ICS1890 ICS1890 Management Registers. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 15 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 4 Overview of the ICS1893AF ICS1893AF Chapter 4 Overview of the ICS1893AF ICS1893AF The ICS1893AF ICS1893AF is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control) converts them into a serial bit stream, encodes them, and transmits them over the medium through an external isolation transformer. When receiving data, the ICS1893AF ICS1893AF converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC Interface. The ICS1893AF ICS1893AF implements the OSI model's physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: · · · · Physical Coding sublayer (PCS) Physical Medium Attachment sublayer (PMA) Physical Medium Dependent sublayer (PMD) Auto-Negotiation sublayer The ICS1893AF ICS1893AF is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893AF ICS1893AF can interface directly to the MAC. The ICS1893AF ICS1893AF transmits framed packets acquired from its MAC Interface and receives encapsulated packets from another PHY, which it translates and presents to its MAC Interface. Note: As per the ISO/IEC standard, the ICS1893AF ICS1893AF does not affect, nor is it affected by, the underlying structure of the MAC/repeater frame it is conveying. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 16 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 4.1 Chapter 4 Overview of the ICS1893AF ICS1893AF 100Base-TX Operation During 100Base-TX data transmission, the ICS1893AF ICS1893AF accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893AF ICS1893AF encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1893AF ICS1893AF replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC/repeater frame. When receiving data from the medium, the ICS1893AF ICS1893AF removes each SSD and replaces it with the pre-defined preamble pattern before presenting the nibbles to its MAC Interface. When the ICS1893AF ICS1893AF encounters an ESD in the received data stream, signifying the end of the frame, it ends the presentation of nibbles to its MAC Interface. Therefore, the local MAC receives an unaltered copy of the transmitted frame sent by the remote MAC/repeater. During periods when MAC frames are being neither transmitted nor received, the ICS1893AF ICS1893AF signals and detects the IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1893AF ICS1893AF transmit channel sends a continuous stream of scrambled ones to signify the IDLE condition. Similarly, the ICS1893AF ICS1893AF receive channel continually monitors its data stream and looks for a pattern of scrambled ones. The results of this signaling and monitoring provide the ICS1893AF ICS1893AF with the means to establish the integrity of the Link Segment between itself and its remote link partner and inform its Station Management Entity (STA) of the link status. For 100M data transmission, the ICS1893AF ICS1893AF MAC Interface is configured to provide a 100M Media Independent Interface (MII). 4.2 10Base-T Operation During 10Base-T data transmission, the ICS1893AF ICS1893AF inserts only the IDL delimiter into the data stream. The ICS1893AF ICS1893AF appends the IDL delimiter to the end of each MAC frame. However, since the 10Base-T preamble already has a Start-of-Frame delimiter (SFD), it is not required that the ICS1893AF ICS1893AF insert an SSD-like delimiter. When receiving data from the medium (such as a twisted-pair cable), the ICS1893AF ICS1893AF uses the preamble to synchronize its receive clock. When the ICS1893AF ICS1893AF receive clock establishes lock, it presents the preamble nibbles to its MAC Interface. The 10M MAC Interface can be configured as either a 10M MII Interface. In 10M operations, during periods when MAC frames are being neither transmitted nor received, the ICS1893AF ICS1893AF signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with the remote link partner to be established and then reported to the ICS1893AF ICS1893AF's STA. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 17 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 5 Operating Modes Overview Chapter 5 Operating Modes Overview The ICS1893AF ICS1893AF operating modes are typically controlled from software. The ICS1893AF ICS1893AF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893AF ICS1893AF is configured to support the MAC Interface as a 10M MII or a 100M MII. The protocol on the Medium Dependent Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or full-duplex modes. The ICS1893AF ICS1893AF is fully compliant with the ISO/IEC 8802-3 standard, as it pertains to both 10Base-T and 100Base-TX operations. The feature-rich ICS1893AF ICS1893AF allows easy migration from 10-Mbps to 100-Mbps operations as well as from systems that require support of both 10M and 100M links. This chapter is an overview of the following ICS1893AF ICS1893AF modes of operation: · · · · · · · Section 5.1, "Reset Operations" Section 5.2, "Power-Down Operations" Section 5.3, "Automatic Power-Saving Operations" Section 5.4, "Auto-Negotiation Operations" Section 5.5, "100Base-TX Operations" Section 5.6, "10Base-T Operations" Section 5.7, "Half-Duplex and Full-Duplex Operations" ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 18 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 5.1 Chapter 5 Operating Modes Overview Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893AF ICS1893AF can be configured for various reset options. 5.1.1 General Reset Operations The following reset operations apply to all the specific ways in which the ICS1893AF ICS1893AF can be reset, which are discussed in Section 5.1.2, "Specific Reset Operations". 5.1.1.1 Entering Reset When the ICS1893AF ICS1893AF enters a reset condition (either through hardware, power-on reset, or software), it does the following: 1. Isolates the MAC/Repeater Interface input pins 2. Drives all MAC/Repeater Interface output pins low 3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN) 4. Initializes all its internal modules and state machines to their default states 5. Enters the power-down state 6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management Register bits to their default values 5.1.1.2 Exiting Reset When the ICS1893AF ICS1893AF exits a reset condition, it does the following: 1. Exits the power-down state 2. Latches the Serial Management Port Address of the ICS1893AF ICS1893AF into the Extended Control Register, bits 16.10:6. [See Section 8.11.3, "PHY Address (bits 16.10:6)".] 3. Enables all its internal modules and state machines 4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their associated ICS1893AF ICS1893AF input pins, as determined by the HW/SW pin 5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) 6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock (TXCLK) and receive clock (RXCLK) 7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed 5.1.1.3 Hot Insertion As with the ICS189X ICS189X products, the ICS1893AF ICS1893AF reset design supports `hot insertion' of its MII. (That is, the ICS1893AF ICS1893AF can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.) ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 19 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 5.1.2 Chapter 5 Operating Modes Overview Specific Reset Operations This section discusses the following specific ways that the ICS1893AF ICS1893AF can be reset: · Hardware reset (using the RESETn pin) · Power-on reset (applying power to the ICS1893AF ICS1893AF) · Software reset (using Control Register bit 0.15) Note: 5.1.2.1 At the completion of a reset (either hardware, power-on, or software), the ICS1893AF ICS1893AF sets all registers to their default values. Hardware Reset Entering Hardware Reset Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware reset (that is, the ICS1893AF ICS1893AF enters the reset state). During reset, the ICS1893AF ICS1893AF executes the steps listed in Section 5.1.1.1, "Entering Reset". Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893AF ICS1893AF completes in 640 ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 5.1.1.2, "Exiting Reset". After the first five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details on this transition, see Section 10.5.16, "Reset: Hardware Reset and Power-Down".] Note: 1. The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid. 2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit that is used to initiate a software reset. 5.1.2.2 Power-On Reset Entering Power-On Reset When power is applied to the ICS1893AF ICS1893AF, it waits until the potential between VDD and VSS achieves a minimum voltage before entering reset and executing the steps listed in Section 5.1.1.1, "Entering Reset". After entering reset from a power-on condition, the ICS1893AF ICS1893AF remains in reset for approximately 20 µs. (For details on this transition, see Section 10.5.15, "Reset: Power-On Reset".) Exiting Power-On Reset The ICS1893AF ICS1893AF automatically exits reset and performs the same steps as for a hardware reset. (See Section 5.1.1.2, "Exiting Reset".) Note: The only difference between a hardware reset and a power-on reset is that during a power-on reset, the ICS1893AF ICS1893AF isolates its RESETn input pin. All other functionality is the same. As with a hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 20 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 5.1.2.3 Chapter 5 Operating Modes Overview Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893AF ICS1893AF enters the reset state for two REF_IN clock cycles. Note: Entering a software reset is nearly identical to entering a hardware reset or a power-on reset, except that during a software-initiated reset, the ICS1893AF ICS1893AF does not enter the power-down state. Exiting Software Reset At the completion of a reset (either hardware, power-on, or software), the ICS1893AF ICS1893AF sets all registers to their default values. This action automatically clears (that is, sets equal to logic zero) Control Register bit 0.15, the software reset bit. Therefore, for a software reset (only), bit 0.15 is a self-clearing bit that indicates the completion of the reset process. Note: 1. The RESETn pin is active low but Control Register bit 0.15 is active high. 2. Exiting a software reset is nearly identical to exiting a hardware reset or a power-on reset, except that upon exiting a software-initiated reset, the ICS1893AF ICS1893AF does not re-latch its Serial Management Port Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 8.11.3, "PHY Address (bits 16.10:6)".] 3. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one. As a result, this bit 0.15 cannot be used to indicate the completion of the reset process for hardware or power-on resets. 5.2 Power-Down Operations The ICS1893AF ICS1893AF enters the power-down state whenever either (1) the RESETn pin is low or (2) Control Register bit 0.11 (the Power-Down bit) is logic one. In the power-down state, the ICS1893AF ICS1893AF disables all internal functions and drives all MAC/Repeater Interface output pins to logic zero except for those that support the MII Serial Management Port. In addition, the ICS1893AF ICS1893AF tri-states its Twisted-Pair Transmit pins (TP_TXP and TP_TXN) to achieve an additional reduction in power. There is one significant difference between entering the power-down state by setting Control Register bit 0.11 as opposed to entering the power-down state during a reset. When the ICS1893AF ICS1893AF enters the power-down state: · By setting Control Register bit 0.11, the ICS1893AF ICS1893AF maintains the value of all Management Register bits except for the latching low (LL), latching high (LH), and latching maximum (LMX) status bits. Instead, these LL, LH, and LMX Management Register bits are re-initialized to their default values. · During a reset, the ICS1893AF ICS1893AF sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: · Section 8.14, "Register 19: Extended Control Register 2" · Section 10.4, "DC Operating Characteristics", which has tables that specify the ICS1893AF ICS1893AF power consumption while in the power-down state ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 21 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 5.3 Chapter 5 Operating Modes Overview Automatic Power-Saving Operations The ICS1893AF ICS1893AF has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1893AF ICS1893AF automatic power-saving features for the various modes. Table 5-1. Automatic Power-Saving Features, 10Base-T and 100Base-TX Modes Mode for ICS1893AF ICS1893AF PowerSaving Feature 10Base-T Mode 100Base-TX Mode Disable Inter- In 10Base-T mode, the ICS1893AF ICS1893AF nal Modules disables all its internal 100Base-TX modules. STA Control of Automatic PowerSaving Features 5.4 When an STA sets the state of the ICS1893AF ICS1893AF Extended Control Register 2, bit 19.0 to logic: · Zero, the 100Base-TX modules always remain enabled, even during 10Base-T operations. · One, the ICS1893AF ICS1893AF automatically disables 100Base-TX modules while the ICS1893AF ICS1893AF is operating in 10Base-T mode. In 100Base-TX mode, the ICS1893AF ICS1893AF disables all its internal 10Base-T modules. When an STA sets the state of the ICS1893AF ICS1893AF Extended Control Register 2, bit 19.1 to logic: · Zero, the 10Base-T modules always remain enabled, even during 100Base-TX operations. · One, the ICS1893AF ICS1893AF automatically disables 10Base-T modules while the ICS1893AF ICS1893AF is operating in 100Base-TX mode. Auto-Negotiation Operations The ICS1893AF ICS1893AF has an Auto-Negotiation sublayer and provides a Control Register bit (bit 0.12) to determine whether its Auto-Negotiation sublayer is enabled or disabled. When enabled, the ICS1893AF ICS1893AF Auto-Negotiation sublayer exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode it has in common with its remote link partner. For example, if the ICS1893AF ICS1893AF supports 100Base-TX and 10Base-T modes ­ but its link partner supports 100Base-TX and 100Base-T4 modes ­ the two devices automatically select 100Base-TX as the highest-performance common operating mode. For details regarding initialization and control of the auto-negotiation process, see Section 7.2, "Functional Block: Auto-Negotiation". ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 22 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 5.5 Chapter 5 Operating Modes Overview 100Base-TX Operations The ICS1893AF ICS1893AF 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893AF ICS1893AF is a 100M translator between a MAC and the physical transmission medium. As such, the ICS1893AF ICS1893AF has two interfaces, both of which are fully configurable: one to the MAC/repeater and one to the Link Segment. In 100Base-TX mode, the ICS1893AF ICS1893AF provides the following functions: · · · · Data conversion from both parallel-to-serial and serial-to-parallel formats Data encoding/decoding (4B/5B, NRZ/NRZI, and MLT-3) Data scrambling/descrambling Data transmission/reception over a twisted-pair medium To accurately transmit and receive data, the ICS1893AF ICS1893AF employs DSP-based wave shaping, adaptive equalization, and baseline wander correction. In addition, in 100Base-TX mode, the ICS1893AF ICS1893AF provides a variety of control and status means to assist with Link Segment management. For more information on 100Base-TX, see Section 7.4, "Functional Block: 100Base-TX TP-PMD Operations". 5.6 10Base-T Operations The ICS1893AF ICS1893AF 10Base-T mode provides 10Base-T physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 10Base-T mode, the ICS1893AF ICS1893AF is a 10M translator between a MAC/repeater and the physical transmission medium. In 10Base-T mode, the ICS1893AF ICS1893AF provides the following functions: · Data conversion from both parallel-to-serial and serial-to-parallel formats · Manchester data encoding/decoding · Data transmission/reception over a twisted-pair medium 5.7 Half-Duplex and Full-Duplex Operations The ICS1893AF ICS1893AF supports half-duplex and full-duplex operations for both 10Base-T and 100Base-TX applications. Full-duplex operation allows simultaneous transmission and reception of data, which effectively doubles the Link Segment throughput to either 20 Mbps (for 10Base-T operations) or 200 Mbps (for 100Base-TX operations). As per the ISO/IEC standard, full-duplex operations differ slightly from half-duplex operations. These differences are necessary, as during full-duplex operations a PHY actively uses both its transmit and receive data paths simultaneously. · In 10Base-T full-duplex operations, the ICS1893AF ICS1893AF disables its loopback function (that is, it does not automatically loop back data from its transmitter to its receiver) and disables its SQE Test function. · In both 10Base-T and 100Base-TX full-duplex operations, the ICS1893AF ICS1893AF asserts its CRS signal only in response to receive activity while its COL signal always remains inactive. For more information on half-duplex and full-duplex operations, see the following sections: · · · · Section 8.2, "Register 0: Control Register" Section 8.2.8, "Duplex Mode (bit 0.8)" Section 8.3, "Register 1: Status Register" Section 8.6, "Register 4: Auto-Negotiation Register" ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 23 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 6 Interface Overviews Chapter 6 Interface Overviews The ICS1893AF ICS1893AF MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: · · · · · Section 6.1, "MII Data Interface" Section 6.2, "Serial Management Interface" Section 6.3, "Twisted-Pair Interface" Section 6.4, "Clock Reference Interface" Section 6.5, "Status Interface" ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 24 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.1 Chapter 6 Interface Overviews MII Data Interface The ICS1893AF ICS1893AF's MAC Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893AF ICS1893AF MAC/Repeater Interface is configured for the MII Data Interface mode, data is transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. The ICS1893AF ICS1893AF provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles). · The ICS1893AF ICS1893AF's MII transmit data path includes the following: ­ ­ ­ ­ A data nibble, TXD[3:0] A transmit data clock to synchronize transfers, TXCLK A transmit enable signal, TXEN A transmit error signal, TXER · The ICS1893AF ICS1893AF's MII receive data path includes the following: ­ ­ ­ ­ A separate data nibble, RXD[3:0] A receive data clock to synchronize transfers, RXCLK A receive data valid signal, RXDV A receive error signal, RXER Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by the ICS1893AF ICS1893AF (that is, the ICS1893AF ICS1893AF sources the TXCLK and RXCLK signals to the MAC/repeater). Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The ICS1893AF ICS1893AF is fully compliant with these definitions and sources both of these signals to the MAC/repeater. When operating in: · Half-duplex mode, the ICS1893AF ICS1893AF asserts the Carrier Sense signal when data is being either transmitted or received. While operating in half-duplex mode, the ICS1893AF ICS1893AF also asserts its Collision Detect signal to indicate that data is being received while a transmission is in progress. · Full-duplex mode, the ICS1893AF ICS1893AF asserts the Carrier Sense signal only when receiving data and forces the Collision Detect signal to remain inactive. As mentioned in Section 5.1.1.3, "Hot Insertion", the ICS1893AF ICS1893AF design allows hot insertion of its MII. That is, it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this functionality, the ICS1893AF ICS1893AF isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1893AF ICS1893AF enables its MII and enables its Twisted-Pair Transmit signals. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 25 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.2 Chapter 6 Interface Overviews Serial Management Interface The ICS1893AF ICS1893AF provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC/Repeater Interface. This Serial Management Interface is used to exchange control, status, and configuration information between a Station Management entity (STA) and the physical layer device (PHY), that is, the ICS1893AF ICS1893AF. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893AF ICS1893AF. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC). The clock is used to synchronize all data transfers between the ICS1893AF ICS1893AF and the STA. In addition to the ISO/IEC defined registers, the ICS1893AF ICS1893AF provides several extended status and control registers to provide more refined control of the MII and MDI interfaces. For example, the QuickPoll Detailed Status Register provides the ability to acquire the most-important status functions with a single MDIO read. Note: 6.3 In the ICS1893AF ICS1893AF, the MDIO and MDC pins remain active for all the MAC/Repeater Interface modes (that is, 10M MII, 100M MII, 100M Symbol, and 10M Serial). Twisted-Pair Interface For the twisted-pair interface, the ICS1893AF ICS1893AF uses 1:1 ratio transformers for both transmit and receive. Better operation results from using a split ground plane through the transformer. In this case: · The RJ-45 RJ-45 transformer windings must be on the chassis ground plane along with the Bob Smith termination. · The ICS1893AF ICS1893AF system ground plane must include the ICS1893AF-side transformer windings along with the 61.9 resistors and the 120-nH inductor. · The transformer provides the isolation with one set of windings on one ground plane and another set of windings on the second ground plane. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 26 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.3.1 Chapter 6 Interface Overviews Twisted-Pair Transmitter Interface The twisted-pair transmitter driver uses an H-bridge configuration. ICS suggests any of the following 1:1 10/100 Magnetics: · Halo TG22S012ND TG22S012ND · Midcom 6120-37 Figure 6-1 shows the design for the ICS1893AF ICS1893AF twisted-pair transmitter interface. · Two 61.9 1% resistors are in series, with a 120-nH 5% inductor between them. These components form a network that connects across both the transformer and the ICS1893AF ICS1893AF TP_TXP and TP_TXN pins. · The ICS1893AF ICS1893AF supplies the power to the transformer. (No VDD connection is required.) · The ICS1893AF ICS1893AF TP_CT pin is connected directly to the transformer transmit center tap connection and is bypassed to ground with a 100-pF capacitor. The transformer center tap must not connect to the resistor/inductor network. Note: 1. If the transmit transformer has a choke, it may be put on the chip side, the RJ-45 RJ-45 side, or both. 2. Keep all TX traces as short as possible. 3. When making board traces, 50-characteristic impedance is desirable. Figure 6-1. ICS1893AF ICS1893AF Transmit Twisted Pair System Ground Plane Chassis Ground Plane Separate Ground Plane 1:1 TP_TXP 12 61.9 1% ICS1893AF ICS1893AF Center Tap 120 nH To RJ-45 RJ-45 61.9 1% TP_TXN 13 TP_CT 10 75 100 pF Ideally, for these traces Zo = 50. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 27 0.1 µF October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.3.2 Chapter 6 Interface Overviews Twisted-Pair Receiver Interface Figure 6-2 shows the design for the ICS1893AF ICS1893AF twisted-pair receiver interface. · Two 56.2 1% resistors are in series, with the center bypassed to ground with a 0.1-µF bypass capacitor. · No bypass capacitor is used with the receive transformer center tap. · A 4.7-pF capacitor must be included across the ICS1893AF ICS1893AF side of the receive transformer. Note: 1. Keep leads as short as possible. 2. Install the resistor network as close to the ICS1893AF ICS1893AF as possible. Figure 6-2. ICS1893AF ICS1893AF Receiver Twisted Pair System Ground Plane Chassis Ground Plane Separate Ground Plane 1:1 TP_RXP 18 56.2 1% ICS1893AF ICS1893AF Center Tap 4.7 pF To RJ-45 RJ-45 0.1 µF 56.2 1% TP_RXN 19 75 0.1 µF 2 kV ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 28 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.4 Chapter 6 Interface Overviews Clock Reference Interface The REF_IN pin provides the ICS1893AF ICS1893AF Clock Reference Interface. The ICS1893AF ICS1893AF requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893AF ICS1893AF supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 6.1. Figure 6-3. Crystal or Oscillator Operation Crystal REF_OUT REF_IN 46 47 25.000MHz 33 pF 33 pF Oscillator REF_OUT REF_IN 46 47 NC CMOS 25.000 MHz 33 Ohm 10 pF ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 29 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 6 Interface Overviews If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893AF ICS1893AF. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the bypass caps serve to adjust the final frequency of the crystal oscillation. Typical applications would use 33pF bypass caps. The exact value will be affected by the board routing capacitance on Ref_in and Ref_out pins. Smaller bypass capacitors raise the frequency of oscillation. Once the exact value of bypass capacitance is established it will be the same for all boards using the same specification crystal. The best way to measure the crystal frequency is to measure the frequency of TXCLK (pin 37) using a frequency counter with a 10 second sample. Using TXCLK prevents affecting the crystal frequency by the measurement. The crystal specification is shown in Table 6.1. Table 6-1. 25MHz Crystal Specification Specifications Symbol Minimum Fundamental Frequency (tolerance is sum of freq., temp., stability and aging.) F0 Freq. Tolerance F/f Input Capacitance CIN Typical Maximum 24.99875 25.00000 Unit 25.00125 MHz ± 50 ppm 3 pF Table 6-2. 25MHz Oscillator Specification Specifications Symbol Minimum Output Frequency F0 Freq. Stability (including aging) F/f Duty cycle CMOS level one-half VDD Tw/T VIH Typical Maximum 24.99875 25.00000 25.00125 MHz ± 50 ppm 65 % 35 2.79 Volts VIL 0.33 Period Jitter Input Capacitance CIN 3 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 30 Volts 500 Tjitter ICS1893AF ICS1893AF, Rev D 10/26/04 Unit pS pF October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 6.5 Chapter 6 Interface Overviews Status Interface The ICS1893AF ICS1893AF provides five multi-function configuration pins that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 9.2.2.) Table 6-3. Pins for Monitoring the Data Link Pin LED Driven by the Pin's Output Signal P0AC AC (Link Activity) LED P1CL CL (Collisions) LED P2LI LI (Link Integrity) LED P3TD TD (Transmit Data) LED P4RD RD (Receive Data) LED Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893AF ICS1893AF exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs. 2. A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of the ICS1893AF ICS1893AF. LEDs may be placed in series with these resistors to provide a designated status indicator as described in Table 6-3. Caution: All pins listed in Table 6-3 must not float. 4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For example, if a multi-function configuration pin is pulled down to ground through an LED and a current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the asserted state, the output is driven high. 5. Adding 10K resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 31 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 6 Interface Overviews Figure 6-4 shows typical biasing and LED connections for the ICS1893AF ICS1893AF. Figure 6-4. ICS1893AF ICS1893AF LED - PHY Interface ICS1893AF ICS1893AF P4RD P3TD 8 P2LI 6 REC P1CL 4 3 LINK TRANS P0AC 1 COL ACTIVITY VDD 10K 10K LED 10K 1K LED 1K 10K 1K LED 10K This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. 2. Caution: PHY address 00 tri-states the MII interface. Don't use PHY address 00. 3. For more reliable address capture during power-on reset, add a 10K resistor across the LED. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 32 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 7 Functional Blocks Chapter 7 Functional Blocks This chapter discusses the following ICS1893AF ICS1893AF functional blocks. · · · · · · Section 7.1, "Functional Block: Media Independent Interface" Section 7.2, "Functional Block: Auto-Negotiation" Section 7.3, "Functional Block: 100Base-X PCS and PMA Sublayers" Section 7.4, "Functional Block: 100Base-TX TP-PMD Operations" Section 7.5, "Functional Block: 10Base-T Operations" Section 7.6, "Functional Block: Management Interface" ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 33 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.1 Chapter 7 Functional Blocks Functional Block: Media Independent Interface All ICS1893AF ICS1893AF MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893AF ICS1893AF MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for 10Base-T operations). The Media Independent Interface (MII) consists of two primary components: 1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893AF ICS1893AF). This MAC-PHY part of the MII consists of three subcomponents: a. A synchronous Transmit interface that includes the following signals: (1) A data nibble, TXD[3:0] (2) An error indicator, TXER (3) A delimiter, TXEN (4) A clock, TXCLK b. A synchronous Receive interface that includes the followings signals: (1) A data nibble, RXD[3:0] (2) An error indicator, RXER (3) A delimiter, RXDV (4) A clock, RXCLK c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision Detection signal (COL). 2. An interface between the PHY (the ICS1893AF ICS1893AF) and an STA (Station Management entity). The STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following: a. A clock (MDC) b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the ICS1893AF ICS1893AF Management Register set The ICS1893AF ICS1893AF Management Register set (discussed in Chapter 8, "Management Register Set") consists of the following: · Basic Management registers. As defined in the ISO/IEC 8802-3 standard, these registers include the following: ­ Control Register (register 0), which handles basic device configuration ­ Status Register (register 1), which reports basic device capabilities and status · Extended Management registers. As defined in the ISO/IEC 8802-3 standard, the ICS1893AF ICS1893AF supports Extended registers that provide access to the Organizationally Unique Identifier and all auto-negotiation functionality. · ICS (Vendor-Specific) Management registers. The ICS1893AF ICS1893AF provides vendor-specific registers for enhanced PHY operations. Among these is the QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a single register access. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 34 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.2 Chapter 7 Functional Blocks Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893AF ICS1893AF has the following main functions: · To determine the capabilities of the remote link partner, (that is, the device at the other end of the link segment's medium or cable) · To advertise the capabilities of the ICS1893AF ICS1893AF to the remote link partner · To establish a protocol with the remote link partner using the highest-performance operating mode that they have in common The design of the ICS1893AF ICS1893AF Auto-Negotiation sublayer supports both legacy 10Base-T connections as well as new connections that have multiple technology options for the link. For example, when the ICS1893AF ICS1893AF has the auto-negotiation process enabled and it is operating with a 10Base-T remote link partner, the ICS1893AF ICS1893AF monitors the link and automatically selects the 10Base-T operating mode ­ even though the remote link partner does not support auto-negotiation. This process, called parallel detection, is automatic and transparent to the remote link partner and allows the ICS1893AF ICS1893AF to function seamlessly with existing legacy network structures without any management intervention. (For an overview of the auto-negotiation process, see Section 5.4, "Auto-Negotiation Operations".) ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 35 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.2.1 Chapter 7 Functional Blocks Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard. During the auto-negotiation process, both the ICS1893AF ICS1893AF and its remote link partner use Fast Link Pulses (FLPs) to simultaneously `advertise' (that is, exchange) information on their respective technology capabilities as follows: 1. For the auto-negotiation process to take place, both the ICS1893AF ICS1893AF and its remote link partner must first both support and be enabled for Auto-Negotiation. 2. The ICS1893AF ICS1893AF obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893AF ICS1893AF and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893AF ICS1893AF transmits information on its technology capability through its Link Control Word, which includes link configuration and status data. 4. Similarly, the ICS1893AF ICS1893AF places the Auto-Negotiation data received from its remote link partner's FLP bursts into the Auto-Negotiation Link Partner Ability Register (Register 5). 5. After the ICS1893AF ICS1893AF and its remote link partner exchange technology capability information, the ICS1893AF ICS1893AF Auto-Negotiation sublayer contrasts the data in Registers 4 and 5 and automatically selects for the operating mode the highest-priority technology that both Register 4 and 5 have in common. (That is, both the ICS1893AF ICS1893AF and its remote link partner use a predetermined priority list for selecting the operating mode, thereby ensuring that both sides of the link make the same selection.) As follows from Annex 28B of the ISO/IEC 8802-3 standard, the pre-determined technology priorities are listed from 1 (highest priority) to 5 (lowest priority): (1) 100Base-TX full duplex (2) 100Base-T4. (The ICS1893AF ICS1893AF does not support this technology.) (3) 100Base-TX (half duplex) (4) 10Base-T full duplex (5) 10Base-T (half duplex) Table 7-1 shows an example of how the selection process of the highest-priority technology takes place. Table 7-1. Example of Selection Process of Highest-Priority Technology If Register 4 Has These Technologies: If Register 5 Has These Technologies: Resulting Highest-Priority Common Technology from Auto-Negotiation Sublayer (3) 100Base-TX half duplex (1) 100Base-TX full duplex (3) 100Base-TX half duplex (4) 100Base-T full duplex (3) 100Base-TX half duplex 6. To indicate that the auto-negotiation process is complete, the ICS1893AF ICS1893AF sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893AF ICS1893AF Auto-Negotiation sublayer performs the following steps: a. It sets to logic one the Status Register's Auto-Negotiation Complete bit (bit 1.5, which is also available in the QuickPoll register as bit 17.4). b. It enables the negotiated link technology (such as the 100Base Transmit modules and 100Base Receive modules). c. It disables the unused technologies to reduce the overall power consumption. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 36 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.2.2 Chapter 7 Functional Blocks Auto-Negotiation: Parallel Detection The ICS1893AF ICS1893AF supports parallel detection. It is therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well as 100Base-TX link partners that do not have an auto-negotiation capability. The Auto-Negotiation sublayer performs this parallel detection function when it does not get a response to its FLP bursts. In these situations, the Auto-Negotiation sublayer performs the following steps: 1. It sets the LP_AutoNeg_Able bit (bit 6.0) to logic zero, thereby identifying the remote link partner as not being capable of executing the auto-negotiation process. 2. It sets the bit in the Auto-Negotiation Link Partner Abilities Register that corresponds to the 'parallel detected' technology [for example, half-duplex, 10Base-T (bit 5.5) or half-duplex, 100Base-TX (bit 5.7)]. 3. It sets the Status Register's Auto-Negotiation Complete bit (bit 1.5) to logic one, indicating completion of the auto-negotiation process. 4. It enables the detected link technology and disables the unused technologies. A remote link partner that does not support the auto-negotiation process does not respond to the transmitted FLP bursts. The ICS1893AF ICS1893AF detects this situation and responds according to the data it receives. The ICS1893AF ICS1893AF can receive one of five potential responses to the FLP bursts it is transmitting: FLP bursts, 10Base-T link pulses (that is, Normal Link Pulses), scrambled 100Base IDLEs, nothing, or a combination of signal types. A 10Base-T link partner transmits only Normal Link Pulses when idle. When the ICS1893AF ICS1893AF receives Normal Link Pulses, it concludes that the remote link partner is a device that can use only 10Base-T technology. A 100Base-TX node without an Auto-Negotiation sublayer transmits 100M scrambled IDLE symbols in response to the FLP bursts. Upon receipt of the scrambled IDLEs, the ICS1893AF ICS1893AF concludes that its remote link partner is a 100Base-TX node that does not support the auto-negotiation process. For both 10Base-T and 100Base-TX nodes without an Auto-Negotiation sublayer, the ICS1893AF ICS1893AF clears bit 6.0 to logic zero, indicating that the link partner cannot perform the auto-negotiation process. If the remote link partner responds to the FLP bursts with FLP bursts, then the link partner is a 100Base-TX node that can support the auto-negotiation process. In this case, the ICS1893AF ICS1893AF sets to logic one the Auto-Negotiation Expansion Register's Link Partner Auto-Negotiation Ability bit (bit 6.0). If the Auto-Negotiation sublayer does not receive any signal when monitoring the receive channel, then the QuickPoll Detailed Status Register's Signal Detect bit (bit 17.3) is set to logic one, indicating that no signal is present. Another possibility is that the ICS1893AF ICS1893AF senses that it is receiving multiple technology indications. In this situation, the ICS1893AF ICS1893AF cannot determine which technology to enable. It informs the STA of this problem by setting to logic one the Auto-Negotiation Expansion Register's Parallel Detection Fault bit (bit 6.4). 7.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893AF ICS1893AF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel. Similarly, if the ICS1893AF ICS1893AF detects a link fault, it transmits a remote fault-detected condition to its remote link partner. In this situation, the ICS1893AF ICS1893AF sets to logic one the Auto-Negotiation Link Partner Ability Register's Remote Fault Indication bit (bit 4.13). For details, see Section 8.14.3, "Remote Fault (bit 19.13)" and Section 8.3.9, "Remote Fault (bit 1.4)". ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 37 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.2.4 Chapter 7 Functional Blocks Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1893AF ICS1893AF auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: · ICS1893AF ICS1893AF reset · Auto-Negotiation Restart 7.2.4.1 Auto-Negotiation Reset During a reset, the ICS1893AF ICS1893AF initializes its Auto-Negotiation sublayer modules to their default states. (That is, the Auto-Negotiation Arbitration State Machine and the Auto-Negotiation Progress Monitor reset to their idle states.) In addition, the Auto-Negotiation Progress Monitor status bits are all set to logic zero. This action occurs for any type of reset (hardware reset, software reset, or power-on reset). 7.2.4.2 Auto-Negotiation Restart As with a reset, during an Auto-Negotiation restart, the ICS1893AF ICS1893AF initializes the Auto-Negotiation Arbitration State Machine and the Auto-Negotiation Progress Monitor modules to their default states. However, during an Auto-Negotiation Restart, the Auto-Negotiation Progress Monitor status bits maintain their current state. Only three events can alter the state of the Auto-Negotiation Progress Monitor status bits after a Restart: (1) an STA read operation, (2) a reset, or (3) the Auto-Negotiation Arbitration State Machine progressing to a higher state or value. The Auto-Negotiation Progress Monitor Status bits change only if they are progressing to a state with a value greater than their current state (that is, a state with a higher logical value than that of their current state). For a detailed explanation of these bits and their operation, see Section 7.2.5, "Auto-Negotiation: Progress Monitor". After the Auto-Negotiation Arbitration State Machine reaches its final state (which is Auto-Negotiation Complete), only an STA read of the QuickPoll Detailed Status Register or an ICS1893AF ICS1893AF reset can alter these status bits. Any of the following situations initiates a restart of the ICS1893AF ICS1893AF Auto-Negotiation sublayer: · A link failure · In software mode: ­ Writing a logic one to the Control Register's Restart Auto-Negotiation bit (bit 0.9), which is a selfclearing bit. ­ Toggling the Control Register's Auto-Negotiation Enable bit (bit 0.12) from a logic one to a logic zero, and back to a logic one. 7.2.5 Auto-Negotiation: Progress Monitor Under typical circumstances, the Auto-Negotiation sublayer can establish a connection with the ICS1893AF ICS1893AF's remote link partner. However, some situations can prevent the auto-negotiation process from properly achieving this goal. For these situations, the ICS1893AF ICS1893AF has an Auto-Negotiation Progress Monitor to provide detailed status information to its Station Management (STA) entity. With this status information, the STA can diagnose the failure mechanism and ­ in some situations ­ establish the link by correcting the problem. When enabled, the auto-negotiation process typically requires less than 500 ms to execute, independent of the link partner's ability to perform the auto-negotiation process. Typically, an STA polls both the Auto-Negotiation Complete bit (bit 1.5) and the Link Status bit (bit 1.2) to determine when a link is successfully established, either through auto-negotiation or parallel detection. The STA can then poll the Auto-Negotiation Link Partner Ability Register and determine the highest-performance operating mode in common with the capabilities it is advertising. ICS1893AF ICS1893AF, Rev D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 38 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release Chapter 7 Functional Blocks The ISO/IEC-defined priority table determines the established link type. As a simpler alternative, the STA can read the QuickPoll Detailed Status Register and determine the link type from the Data Rate bit (bit 17.15) and the Duplex bit (bit 17.14). For convenience, the QuickPoll Register also includes the Link Status bit (bit 17.0) and the Auto-Negotiation Complete bit (bit 17.4). If (1) the auto-negotiation process does not complete, or (2) the link is not established, or (3) both the auto-negotiation process does not complete and the link is not established, then the STA can determine the cause of the link failure by using the outputs of the ICS1893AF ICS1893AF Auto-Negotiation Progress Monitor. The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the history and the present state of the auto-negotiation process. This status data is provided in the QuickPoll Detailed Status register by using the Auto-Negotiation Complete bit (bit 17.4) as well as bits 17.13:11. The bit order, from most-significant bit to least-significant bit, is 17.4, 17.13, 17.12, and 17.11. Using these four bits, the Auto-Negotiation Progress Monitor provides nine state codes detailing the operation of the auto-negotiation process for the STA. [For more information, see Section 8.12.3, "Auto-Negotiation Progress Monitor (bits 17.13:11)".] The nine Auto-Negotiation Progress Monitor state codes are 0h through 8h and Fh. The Auto-Negotiation Progress Monitor automatically latches the values of the Auto-Negotiation Arbitration State Machine into the status bits only if the value of the present state is greater than the value that is currently in the status bits. For example, if the status bits have a value of 3h and the auto-negotiation process moves into: · State 1, the Auto-Negotiation Progress Monitor does not update the status bits to indicate the new state. · State 5, the Auto-Negotiation Progress Monitor updates the status bits to indicate the new state, State 5. In this case, the status bits increase in value until either the auto-negotiation process successfully completes or the STA reads the Auto-Negotiation Progress Monitor status bits. When the STA reads the status bits, the present state of the auto-negotiation process is automatically latched into the status bits, regardless of how they compare to the value currently in the latch. However, the read presents the STA with the previously latched values of the status bits, not the values just latched into the status register by the read. Therefore, the STA must perform two reads of the status bits to determine the present state of the Auto-Negotiation Arbitration State Machine. The first read provides a 'history' of the auto-negotiation process, (that is, the highest state achieved by the auto-negotiation process). The second read provides the present state of the auto-negotiation process. This behavior allows management to determine the greatest forward progress made by the auto-negotiation logic, which is valuable for diagnosing link errors and failures. Note: Once the auto-negotiation process completes successfully, the value of all the Progress Monitor status bits and the Auto-Negotiation Complete bit have a value of logic one. A read operation of the QuickPoll Register provides a value of logic one for the Auto-Negotiation Complete bit and an octal value of 111 for the status bits. Subsequent reads of the QuickPoll Register also provide a value of logic one for the Auto-Negotiation Complete bit. However, the value of the status bits are 000b, providing the link remains established. ICS1893AF ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 39 October, 2004 ICS1893AF ICS1893AF Data Sheet - Release 7.3 Chapter 7 Functional Blocks Functional Block: 100Base-X PCS and PMA Sublayers The ICS1893AF ICS1893AF is fully compliant with clause 24 of the ISO/IEC specification, which defines the 100Base-X Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 7.3.1 PCS Sublayer The ICS1893AF ICS1893AF 100Base-X PCS sublayer provides two interfaces: one to a MAC/repeater and the other to the ICS1893AF ICS1893AF PMA sublayer. An ICS1893 ICS1893's PCS sublayer performs the transmit, receive, and control functions and consists of the following: · PCS Transmit