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ICL3221E ICL3222E ICL3223E ICL3232E ICL3241E ICL3243E RS-232 IEC1000 ICL32XXE - Datasheet Archive
ICL3241E, ICL3243E TM Data Sheet December 2000 +/-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232
ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E TM Data Sheet December 2000 +/-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232 RS-232 Transmitters/Receivers File Number 4910.2 Features · ESD Protection for RS-232 RS-232 I/O Pins to ±15kV (IEC1000 IEC1000) The Intersil ICL32XXE ICL32XXE devices are 3.0V to 5.5V powered RS-232 RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide ±15kV ESD protection (IEC 1000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 RS-232 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic powerdown functions (except for the ICL3232E ICL3232E), reduce the standby supply current to a 1µA trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V only systems, mixed 3.3V and 5.0V systems, and 5.0V only systems. · Drop in Replacements for MAX3221E MAX3221E, MAX3222E MAX3222E, MAX3223E MAX3223E, MAX3232E MAX3232E, MAX3241E MAX3241E, MAX3243E MAX3243E, SP3243E SP3243E · ICL3222E ICL3222E is Low Power, Pin Compatible Upgrade for 5V MAX242E MAX242E, and SP312E SP312E · ICL3232E ICL3232E is Low Power Upgrade for HIN232E/ICL232 HIN232E/ICL232 and Pin Compatible Competitor Devices · Meets EIA/TIA-232 EIA/TIA-232 and V.28/V.24 Specifications at 3V · Latch-Up Free · On-Chip Voltage Converters Require Only Four External 0.1µF Capacitors · Manual and Automatic Powerdown Features (Except ICL3232E ICL3232E) · Guaranteed Mouse Driveability · Receiver Hysteresis For Improved Noise Immunity · Guaranteed Minimum Data Rate . . . . . . . . . . . . 250kbps The ICL324XE ICL324XE are 3 driver, 5 receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting alwaysactive receivers for "wake-up" capability. The ICL3221E ICL3221E, ICL3223E ICL3223E and ICL3243E ICL3243E, feature an automatic powerdown function which powers down the onchip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS-232 RS-232 cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS-232 RS-232 voltage is applied to any receiver input. Table 1 summarizes the features of the devices represented by this data sheet, while Application Note AN9863 AN9863 summarizes the features of each device comprising the ICL32XXE ICL32XXE 3V family. · Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs · Wide Power Supply Range. . . . . . . . Single +3V to +5.5V · Low Supply Current in Powerdown State . . . . . . . . . . 1µA Applications · Any System Requiring RS-232 RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones Related Literature · Technical Brief TB363 TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" TABLE 1. SUMMARY OF FEATURES PART NUMBER NO. OF NO. OF Tx. Rx. NO. OF MONITOR Rx. (ROUTB) DATA RATE (kbps) Rx. ENABLE FUNCTION? READY OUTPUT? MANUAL POWERDOWN? AUTOMATIC POWERDOWN FUNCTION? ICL3221E ICL3221E 1 1 0 250 YES NO YES YES ICL3222E ICL3222E 2 2 0 250 YES NO YES NO ICL3223E ICL3223E 2 2 0 250 YES NO YES YES ICL3232E ICL3232E 2 2 0 250 NO NO NO NO ICL3241E ICL3241E 3 5 2 250 YES NO YES NO ICL3243E ICL3243E 3 5 1 250 NO NO YES YES 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Ordering Information (NOTE 1) PART NO. TEMP. RANGE (oC) PACKAGE PKG. NO. ICL3221ECA ICL3221ECA 0 to 70 16 Ld SSOP M16.209 ICL3221EIA ICL3221EIA -40 to 85 16 Ld SSOP M16.209 ICL3221ECV ICL3221ECV 0 to 70 16 Ld TSSOP M16.173 ICL3222ECA ICL3222ECA 0 to 70 20 Ld SSOP M20.209 ICL3222EIA ICL3222EIA -40 to 85 20 Ld SSOP M20.209 ICL3222ECB ICL3222ECB 0 to 70 18 Ld SOIC M18.3 ICL3222EIB ICL3222EIB -40 to 85 18 Ld SOIC M18.3 ICL3222ECP ICL3222ECP 0 to 70 18 Ld PDIP E18.3 ICL3222ECV ICL3222ECV 0 to 70 20 Ld TSSOP M20.173 ICL3222EIV ICL3222EIV -40 to 85 20 Ld TSSOP M20.173 ICL3223ECA ICL3223ECA 0 to 70 20 Ld SSOP M20.209 ICL3223EIA ICL3223EIA -40 to 85 20 Ld SSOP M20.209 ICL3223ECP ICL3223ECP 0 to 70 20 Ld PDIP E20.3 ICL3223ECV ICL3223ECV 0 to 70 20 Ld TSSOP M20.173 ICL3223EIV ICL3223EIV -40 to 85 20 Ld TSSOP M20.173 ICL3232ECA ICL3232ECA 0 to 70 16 Ld SSOP M16.209 ICL3232EIA ICL3232EIA -40 to 85 16 Ld SSOP M16.209 ICL3232ECB ICL3232ECB 0 to 70 16 Ld SOIC M16.3 ICL3232EIB ICL3232EIB -40 to 85 16 Ld SOIC M16.3 ICL3232ECP ICL3232ECP 0 to 70 16 Ld PDIP E16.3 ICL3232ECV-16 ICL3232ECV-16 0 to 70 16 Ld TSSOP M16.173 ICL3232EIV-16 ICL3232EIV-16 -40 to 85 16 Ld TSSOP M16.173 ICL3232ECV-20 ICL3232ECV-20 0 to 70 20 Ld TSSOP M20.173 ICL3232EIV-20 ICL3232EIV-20 -40 to 85 20 Ld TSSOP M20.173 ICL3241ECA ICL3241ECA 0 to 70 28 Ld SSOP M28.209 ICL3241EIA ICL3241EIA -40 to 85 28 Ld SSOP M28.209 ICL3241ECB ICL3241ECB 0 to 70 28 Ld SOIC M28.3 ICL3241EIB ICL3241EIB -40 to 85 28 Ld SOIC M28.3 ICL3241ECV ICL3241ECV 0 to 70 28 Ld TSSOP M28.173 ICL3241EIV ICL3241EIV -40 to 85 28 Ld TSSOP M28.173 ICL3243ECA ICL3243ECA 0 to 70 28 Ld SSOP M28.209 ICL3243EIA ICL3243EIA -40 to 85 28 Ld SSOP M29.209 ICL3243ECB ICL3243ECB 0 to 70 28 Ld SOIC M28.3 ICL3243EIB ICL3243EIB -40 to 85 28 Ld SOIC M28.3 ICL3243ECV ICL3243ECV 0 to 70 28 Ld TSSOP M28.173 ICL3243EIV ICL3243EIV -40 to 85 28 Ld TSSOP M28.173 NOTE: 1. Most surface mount devices are available on tape and reel; add "-T" to suffix. 2 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Pinouts ICL3221E ICL3221E (SSOP, TSSOP) TOP VIEW 16 FORCEOFF EN 1 ICL3222E ICL3222E (PDIP, SOIC) TOP VIEW EN 1 18 SHDN C1+ 2 15 VCC C1+ 2 17 VCC V+ 3 14 GND V+ 3 16 GND C1- 4 13 T1OUT C1- 4 15 T1OUT C2+ 5 12 FORCEON C2+ 5 14 R1IN C2- 6 11 T1IN C2- 6 13 R1OUT 10 INVALID V- 7 9 R1OUT R1IN 8 V- 7 12 T1IN T2OUT 8 11 T2IN R2IN 9 ICL3222E ICL3222E (SSOP, TSSOP) TOP VIEW 20 SHDN EN 1 C1+ 2 19 VCC V+ 3 18 GND 10 R2OUT ICL3223E ICL3223E (PDIP, SSOP, TSSOP) TOP VIEW EN 1 20 FORCEOFF C1+ 2 19 VCC V+ 3 18 GND C1- 4 17 T1OUT C1- 4 17 T1OUT C2+ 5 16 R1IN C2+ 5 16 R1IN C2- 6 15 R1OUT C2- 6 15 R1OUT 14 NC V- 7 V- 7 14 FORCEON T2OUT 8 13 T1IN T2OUT 8 13 T1IN R2IN 9 12 T2IN R2IN 9 12 T2IN 11 NC R2OUT 10 ICL3232E ICL3232E (PDIP, SOIC, SSOP, TSSOP) TOP VIEW R2OUT 10 11 INVALID ICL3241E ICL3241E (SOIC, SSOP, TSSOP) TOP VIEW C1+ 1 16 VCC C2+ 1 28 C1+ V+ 2 15 GND C2- 2 27 V+ V- 3 26 VCC 13 R1IN R1IN 4 25 GND 12 R1OUT R2IN 5 24 C1- V- 6 11 T1IN R3IN 6 23 EN T2OUT 7 10 T2IN R4IN 7 22 SHDN R5IN 8 21 R1OUTB T1OUT 9 20 R2OUTB T2OUT 10 19 R1OUT T3OUT 11 18 R2OUT T3IN 12 17 R3OUT T2IN 13 16 R4OUT T1IN 14 15 R5OUT C1- 3 14 T1OUT C2+ 4 C2- 5 9 R2OUT R2IN 8 3 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Pinouts (Continued) ICL3243E ICL3243E (SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 28 C1+ C2- 2 27 V+ V- 3 26 VCC R1IN 4 25 GND R2IN 5 24 C1- R3IN 6 23 FORCEON R4IN 7 22 FORCEOFF R5IN 8 21 INVALID T1OUT 9 20 R2OUTB T2OUT 10 19 R1OUT T3OUT 11 18 R2OUT T3IN 12 17 R3OUT T2IN 13 16 R4OUT T1IN 14 15 R5OUT Pin Descriptions PIN VCC FUNCTION System power supply input (3.0V to 5.5V). V+ Internally generated positive transmitter supply (+5.5V). V- Internally generated negative transmitter supply (-5.5V). GND Ground connection. C1+ External capacitor (voltage doubler) is connected to this lead. C1- External capacitor (voltage doubler) is connected to this lead. C2+ External capacitor (voltage inverter) is connected to this lead. C2- External capacitor (voltage inverter) is connected to this lead. TIN TTL/CMOS compatible transmitter Inputs. TOUT RIN ±15kV ESD Protected, RS-232 RS-232 level (nominally ±5.5V) transmitter outputs. ±15kV ESD Protected, RS-232 RS-232 compatible receiver inputs. ROUT TTL/CMOS level receiver outputs. ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs. INVALID Active low output that indicates if no valid RS-232 RS-232 levels are present on any receiver input. EN SHDN Active low receiver enable control; doesn't disable ROUTB outputs. Active low input to shut down transmitters and on-board power supply, to place device in low power mode. FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2). FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high). 4 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Typical Operating Circuits ICL3221E ICL3221E +3.3V + 0.1µF 15 2 + C1+ 4 C15 + C2+ 6 C2- C1 0.1µF C2 0.1µF T1IN TTL/CMOS LOGIC LEVELS R1OUT VCC 3 V- 7 C4 + 0.1µF T1 11 + C3 0.1µF V+ 13 9 T1OUT 8 R1IN RS-232 RS-232 LEVELS 5k R1 1 EN 16 VCC FORCEOFF 12 FORCEON GND INVALID 10 TO POWER CONTROL LOGIC 14 ICL3222E ICL3222E +3.3V C1 0.1µF C2 0.1µF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT + 0.1µF 2 + 4 5 + 6 17 C1+ VCC 3 V+ C1C2+ 12 11 7 V- C2- + T1 15 T2 C4 0.1µF T1OUT 8 T2OUT 14 13 R1IN 5k R1 9 10 R2OUT R2IN 1 EN 5k R2 SHDN GND 16 5 + C3 0.1µF 18 VCC RS-232 RS-232 LEVELS ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Typical Operating Circuits (Continued) ICL3223E ICL3223E +3.3V + 0.1µF 2 + 4 C1 0.1µF 5 + 6 C2 0.1µF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 19 C1+ C2- 3 + C3 0.1µF V- 7 VCC C1C2+ C4 0.1µF + V+ T1 13 17 T2 12 8 15 R2OUT R2 5k 9 EN FORCEOFF 14 R1IN RS-232 RS-232 LEVELS 5k 10 1 T2OUT 16 R1 T1OUT INVALID FORCEON R2IN 20 11 VCC TO POWER CONTROL LOGIC GND 18 ICL3232E ICL3232E +3.3V + 1 C1 0.1µF + C2 0.1µF + T1IN TTL/CMOS LOGIC LEVELS 0.1µF T2IN R1OUT 3 4 5 11 10 C1+ 16 VCC V+ C1C2+ V- C2T1 + C3 0.1µF 6 C4 0.1µF + 14 T2 T1OUT 7 T2OUT 13 12 R1 R1IN 5k 9 8 R2OUT R2 5k GND 15 6 2 R2IN RS-232 RS-232 LEVELS ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Typical Operating Circuits (Continued) ICL3241E ICL3241E +3.3V + C1 0.1µF C2 0.1µF +3.3V 0.1µF 28 + 24 1 + 2 ICL3243E ICL3243E C1+ VCC V+ C1C2+ V- C2- 27 3 14 T1 T2 + C3 0.1µF + T3 12 + V+ VT1 T2 3 10 T2OUT T3 12 RS-232 RS-232 LEVELS 11 T3OUT 20 R2OUTB 19 R2OUTB 4 R1OUT R1 19 R1IN 5k 18 17 16 18 5 R2IN R2 R3IN 5k R3 5k R2OUT 6 R3OUT R1IN R1 TTL/CMOS LOGIC LEVELS R2IN 5k R2 4 R1OUT 5 R2OUT RS-232 RS-232 LEVELS 5k 17 6 R3OUT 7 R3IN R3 R4OUT R4 R4IN 5k 15 EN 5k R5 5k 16 7 R4OUT 8 R5OUT 23 C4 0.1µF + T1OUT T3IN 20 C3 0.1µF 9 T2IN R1OUTB VCC VCC 13 RS-232 RS-232 LEVELS T3OUT 21 27 C11 C2+ + 2 C2- C1+ 24 T1IN 11 T3IN 26 14 T1OUT T2OUT 28 C2 0.1µF C4 0.1µF + 10 T2IN TTL/CMOS LOGIC LEVELS 0.1µF C1 0.1µF 9 13 T1IN + 26 R4IN R4 R5IN 5k 15 8 R5OUT 22 SHDN R5IN 23 GND 5k R5 FORCEON 25 VCC TO POWER CONTROL LOGIC 7 22 FORCEOFF 21 INVALID GND 25 RS-232 RS-232 LEVELS ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical, Note 2) JA (oC/W) 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 90 18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 80 20 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 77 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 100 18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135 20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140 28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100 Moisture Sensitivity (see Technical Brief TB363 TB363) All Packages Not Listed Below. . . . . . . . . . . . . . . . . . . . . . Level 1 16 Ld SSOP and TSSOP Packages . . . . . . . . . . . . . . . . . Level 2 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC, SSOP, TSSOP - Lead Tips Only) Operating Conditions Temperature Range ICL32XXECX ICL32XXECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ICL32XXEIX ICL32XXEIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 TB379 for details. Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25oC PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS DC CHARACTERISTICS Supply Current, Automatic Powerdown All RIN Open, FORCEON = GND, FORCEOFF = VCC (ICL3221E ICL3221E, ICL3223E ICL3223E, ICL3243E ICL3243E Only) 25 - 1.0 10 µA Supply Current, Powerdown FORCEOFF = SHDN = GND (Except ICL3232E ICL3232E) 25 - 1.0 10 µA Supply Current, Automatic Powerdown Disabled VCC = 3.0V, ICL3241-43 ICL3241-43 All Outputs Unloaded, FORCEON = FORCEOFF = VCC = 3.15V, ICL3221-32 ICL3221-32 SHDN = VCC 25 - 0.3 1.0 mA 25 - 0.3 1.0 mA LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN, SHDN VCC = 3.3V Full 2.0 - - V VCC = 5.0V Full 2.4 - - V Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Full - ±0.01 ±1.0 µA Output Leakage Current (Except ICL3232E ICL3232E) FORCEOFF = GND or EN = VCC Full - ±0.05 ±10 µA Output Voltage Low IOUT = 1.6mA Full - - 0.4 V Output Voltage High IOUT = -1.0mA Full - V VCC -0.6 VCC -0.1 AUTOMATIC POWERDOWN (ICL3221E ICL3221E, ICL3223E ICL3223E, ICL3243E ICL3243E Only, FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to Enable Transmitters ICL32XXE ICL32XXE Powers Up (See Figure 6) Full -2.7 - 2.7 V Receiver Input Thresholds to Disable Transmitters ICL32XXE ICL32XXE Powers Down (See Figure 6) Full -0.3 - 0.3 V INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V 8 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25oC (Continued) TEMP (oC) MIN TYP MAX UNITS Receiver Threshold to Transmitters Enabled Delay (tWU) 25 - 100 - µs Receiver Positive or Negative Threshold to INVALID High Delay (tINVH) 25 - 1 - µs Receiver Positive or Negative Threshold to INVALID Low Delay (tINVL) 25 - 30 - µs 25 -25 - 25 V VCC = 3.3V 25 0.6 1.2 - V VCC = 5.0V 25 0.8 1.5 - V VCC = 3.3V 25 - 1.5 2.4 V VCC = 5.0V 25 - 1.8 2.4 V Input Hysteresis 25 - 0.5 - V Input Resistance 25 3 5 7 k PARAMETER TEST CONDITIONS RECEIVER INPUTS Input Voltage Range Input Threshold Low Input Threshold High TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3k to Ground Full ±5.0 ±5.4 - V Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Full - ±35 ±60 mA Full - - ±25 µA T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3k to GND, T1OUT and T2OUT Loaded with 2.5mA Each Full ±5 - - V Maximum Data Rate RL = 3k, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps Receiver Propagation Delay Receiver Input to Receiver Output, CL = 150pF 25 - 0.15 - µs 25 - 0.15 - µs Receiver Output Enable Time Normal Operation (Except ICL3232E ICL3232E) 25 - 200 - ns Receiver Output Disable Time Normal Operation (Except ICL3232E ICL3232E) 25 - 200 - ns Transmitter Skew tPHL - tPLH (Note 3) 25 - 100 - ns Receiver Skew tPHL - tPLH 25 - 50 - ns Transition Region Slew Rate CL = 150pF to 2500pF VCC = 3.3V, RL = 3k to 7k, CL = 150pF to 1000pF Measured From 3V to -3V or -3V to 3V 25 4 - 30 V/µs 25 6 - 30 V/µs Human Body Model 25 - ±15 - kV Output Short-Circuit Current VOUT = ±12V, VCC = 0V or 3V to 5.5V, Automatic Powerdown or FORCEOFF = SHDN = GND Output Leakage Current (Except ICL3232E ICL3232E) MOUSE DRIVEABILITY (ICL324XE ICL324XE Only) Transmitter Output Voltage (See Figure 9) TIMING CHARACTERISTICS tPHL tPLH ESD PERFORMANCE RS-232 RS-232 Pins (TOUT, RIN) IEC1000-4-2 IEC1000-4-2 Contact Discharge - ±8 - kV 25 - ±15 - kV Human Body Model All Other Pins 25 IEC1000-4-2 IEC1000-4-2 Air Gap Discharge 25 - ±3 - kV NOTE: 3. Transmitter skew is measured at the transmitter zero crossing points. 9 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Detailed Description ICL32XXE ICL32XXE interface ICs operate from a single +3V to +5.5V supply, guarantee a 250kbps minimum data rate, require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C RS-232C and V.28 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers. Charge-Pump Intersil's new ICL32XXE ICL32XXE family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at VCC = 3.3V. See the "Capacitor Selection" section, and Table 3 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 RS-232 levels over a wide range of single supply system voltages. Except for the ICL3232E ICL3232E, all transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to ±12V when disabled. All devices guarantee a 250kbps data rate for full load conditions (3k and 1000pF), VCC 3.0V, with one transmitter operating at full speed. Under more typical conditions of VCC 3.3V, RL = 3k, and CL = 250pF, one transmitter easily operates at 900kbps. Transmitter inputs float if left unconnected, and may cause ICC increases. Connect unused inputs to GND for the best performance. Receivers All the ICL32XXE ICL32XXE devices contain standard inverting receivers that three-state (except for the ICL3232E ICL3232E) via the EN or FORCEOFF control lines. Additionally, the two ICL324XE ICL324XE products include noninverting (monitor) receivers (denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS-232 RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3k to 7k input impedance (see Figure 1) even if the power is off (VCC = 0V). The receivers' Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. 10 The ICL3221E/22E/23E/41E ICL3221E/22E/23E/41E inverting receivers disable only when EN is driven high. ICL3243E ICL3243E receivers disable during forced (manual) powerdown, but not during automatic powerdown (see Table 2). ICL324XE ICL324XE monitor receivers remain active even during manual powerdown and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral's protection diodes (see Figures 2 and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3. VCC RXIN -25V VRIN +25V RXOUT 5k GND VROUT VCC GND FIGURE 1. INVERTING RECEIVER CONNECTIONS Powerdown Functionality (Except ICL3232E ICL3232E) This 3V family of RS-232 RS-232 interface devices requires a nominal supply current of 0.3mA during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA current required of 5V RS-232 RS-232 devices. The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to VCC, V- collapses to GND), and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in powerdown; refer to Table 2 for details. This micro-power mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Powerdown Most devices in the ICL32XXE ICL32XXE family provide pins that allow the user to force the IC into the low power, standby state. On the ICL3222E ICL3222E and ICL3241E ICL3241E, the powerdown control is via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into it's powerdown state. Connect SHDN to VCC if the powerdown function isn't needed. Note that all the receiver outputs remain enabled during shutdown (see Table 2). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN input high (see next section, and Figures 2 and 3). The ICL3221E ICL3221E, ICL3223E ICL3223E, and ICL3243E ICL3243E utilize a two pin approach where the FORCEON and FORCEOFF inputs determine the IC's mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and powerdown modes, under logic or software control, only the FORCEOFF input need be driven. ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E The FORCEON state isn't critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic powerdown circuitry. Inverting (standard) receiver outputs also disable when the device is in powerdown, thereby eliminating the possible current path through a shutdown peripheral's input protection diode (see Figures 2 and 3). The INVALID output always indicates whether or not a valid RS-232 RS-232 signal is present at any of the receiver inputs (see Table 2), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to GND by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic powerdown feature, enabling them to function as a manual SHUTDOWN input (see Figure 4). TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE RS-232 RS-232 SIGNAL PRESENT AT RECEIVER INPUT? FORCEOFF (NOTE 4) OR SHDN FORCEON EN TRANSMITTER RECEIVER ROUTB INVALID INPUT INPUT INPUT OUTPUTS OUTPUTS OUTPUTS OUTPUT MODE OF OPERATION ICL3222E ICL3222E, ICL3241E ICL3241E N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/Rcvr. Disabled N.A. H N.A. L Active Active Active N.A. Normal Operation N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/Rcvr. Disabled ICL3221E ICL3221E, ICL3223E ICL3223E NO H H L Active Active N.A. L Normal Operation (Auto Powerdown Disabled) NO H H H Active High-Z N.A. L YES H L L Active Active N.A. H YES H L H Active High-Z N.A. H NO H L L High-Z Active N.A. L NO H L H High-Z High-Z N.A. L YES L X L High-Z Active N.A. H Manual Powerdown YES L X H High-Z High-Z N.A. H Manual Powerdown w/Rcvr. Disabled NO L X L High-Z Active N.A. L Manual Powerdown NO L X H High-Z High-Z N.A. L Manual Powerdown w/Rcvr. Disabled NO H H N.A. Active Active Active L Normal Operation (Auto Powerdown Disabled) YES H L N.A. Active Active Active H Normal Operation (Auto Powerdown Enabled) NO H L N.A. High-Z Active Active L Powerdown Due to Auto Powerdown Logic YES L X N.A. High-Z High-Z Active H Manual Powerdown NO L X N.A. High-Z High-Z Active L Manual Powerdown Normal Operation (Auto Powerdown Enabled) Powerdown Due to Auto Powerdown Logic ICL3243E ICL3243E NOTE: 4. Applies only to the ICL3241E ICL3241E and ICL3243E ICL3243E. 11 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E VCC With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 100µs. A mouse, or other application, may need more time to wake up from shutdown. If automatic powerdown is being utilized, the RS-232 RS-232 device will reenter powerdown if valid receiver levels aren't reestablished within 30µs of the ICL32XXE ICL32XXE powering up. Figure 5 illustrates a circuit that keeps the ICL32XXE ICL32XXE from initiating automatic powerdown for 100ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS-232 RS-232 output levels. VCC CURRENT FLOW VCC VOUT = VCC Rx POWERED DOWN UART Tx OLD RS-232 RS-232 CHIP SHDN = GND GND POWER MANAGEMENT UNIT FIGURE 2. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL 1M FORCEON ICL3221E/23E/43E ICL3221E/23E/43E TRANSITION DETECTOR FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR 100ms AFTER FORCED POWERUP TO WAKE-UP LOGIC ICL324XE ICL324XE Automatic Powerdown (ICL3221E/23E/43E ICL3221E/23E/43E Only) VCC R2OUTB POWERED DOWN UART 0.1µF FORCEOFF VCC RX MASTER POWERDOWN LINE VOUT = HI-Z R2OUT TX R2IN T1IN T1OUT FORCEOFF = GND OR SHDN = GND, EN = VCC FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN Even greater power savings is available by using the devices which feature an automatic powerdown function. When no valid RS-232 RS-232 voltages (see Figure 6) are sensed on any receiver input for 30µs, the charge pump and transmitters powerdown, thereby reducing supply current to 1µA. Invalid receiver levels occur whenever the driving peripheral's outputs are shut off (powered down) or when the RS-232 RS-232 interface cable is disconnected. The ICL32XXE ICL32XXE powers back up whenever it detects a valid RS-232 RS-232 voltage level on any receiver input. This automatic powerdown feature provides additional system power savings without changes to the existing operating system. FORCEOFF VALID RS-232 RS-232 LEVEL - ICL32XXE ICL32XXE IS ACTIVE 2.7V PWR MGT LOGIC FORCEON INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR INVALID ICL3221E/23E/43E ICL3221E/23E/43E 0.3V INVALID LEVEL - POWERDOWN OCCURS AFTER 30µs -0.3V INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR I/O UART -2.7V CPU VALID RS-232 RS-232 LEVEL - ICL32XXE ICL32XXE IS ACTIVE FIGURE 6. DEFINITION OF VALID RS-232 RS-232 RECEIVER LEVELS FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT 12 Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF input is high. Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF input. Table 2 summarizes the automatic powerdown functionality. ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Devices with the automatic powerdown feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 7). INVALID switches high 1µs after detecting a valid RS-232 RS-232 level on a receiver input. INVALID operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry. When automatic powerdown is utilized, INVALID = 0 indicates that the ICL32XXE ICL32XXE is in powerdown mode. INVALID } REGION RECEIVER INPUTS VCC tINVH tINVL 0 PWR UP AUTOPWDN V+ VCC 0 V- FIGURE 7. AUTOMATIC POWERDOWN AND INVALID TIMING DIAGRAMS The time to recover from automatic powerdown mode is typically 100µs. Receiver ENABLE Control (ICL3221E/22E/23E/41E ICL3221E/22E/23E/41E Only) Several devices also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting (standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (VCC = GND) peripheral (see Figure 2). The enable input has no effect on transmitter nor monitor (ROUTB) outputs. Capacitor Selection The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without increasing C1's value, however, do not increase C1 without also increasing C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal 13 TABLE 3. REQUIRED CAPACITOR VALUES VCC (V) C1 (µF) C2, C3, C4 (µF) 3.0 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.1 0.47 Power Supply Decoupling In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC. TRANSMITTER OUTPUTS INVALID OUTPUT value. The capacitor's equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-. Transmitter Outputs when Exiting Powerdown Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3k in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V. 5V/DIV. FORCEOFF T1 2V/DIV. T2 VCC = +3.3V C1 - C4 = 0.1µF TIME (20µs/DIV.) FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN Mouse Driveability The ICL324XE ICL324XE have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least ±5V during worst case conditions (15mA for paralleled V+ transmitters, 7.3mA for single V- transmitter). The Automatic Powerdown feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to VCC. ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E 5V/DIV. TRANSMITTER OUTPUT VOLTAGE (V) 6 5 T1IN VOUT+ 4 3 VCC = 3.0V 2 1 T1 T1OUT 0 VOUT+ -1 T2 -2 ICL3241E/43E ICL3241E/43E -3 VCC -4 VOUT - T3 R1OUT VOUT - VCC = +3.3V C1 - C4 = 0.1µF -5 -6 1 0 3 2 5 4 7 6 8 9 10 5µs/DIV. LOAD CURRENT PER TRANSMITTER (mA) FIGURE 11. LOOPBACK TEST AT 120kbps FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL VOUT+ CURRENT) T1IN High Data Rates The ICL32XXE ICL32XXE maintain the RS-232 RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 10 details a transmitter loopback test circuit, and Figure 11 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 RS-232 loads in parallel with 1000pF, at 120kbps. Figure 12 shows the loopback results for a single transmitter driving 1000pF and an RS-232 RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 RS-232 receiver. VCC = +3.3V C1 - C4 = 0.1µF C1+ FIGURE 12. LOOPBACK TEST AT 250kbps VCC V+ C1 C1- + C3 ICL32XXE ICL32XXE V- C2+ C2 C4 + C2TIN Interconnection with 3V and 5V Logic The ICL32XXE ICL32XXE directly interface with most 5V logic families, including ACT and HCT CMOS. See Table 4 for more information on possible combinations of interconnections. TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES TOUT EN 1000pF 5k SHDN OR FORCEOFF FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT 14 SYSTEM POWER-SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) 3.3 3.3 5 5 5 RIN ROUT VCC R1OUT + 0.1µF + T1OUT 2µs/DIV. VCC + 5V/DIV. 3.3 COMPATIBILITY Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, or CD4000 CD4000 CMOS. ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E ±15kV ESD Protection All pins on ICL32XX ICL32XX devices include ESD protection structures, but the ICL32XXE ICL32XXE family incorporates advanced structures which allow the RS-232 RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±15kV. The RS-232 RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and don't interfere with RS-232 RS-232 signals as large as ±25V. Human Body Model (HBM) Testing As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5k current limiting resistor, making the test less severe than the IEC-1000 IEC-1000 test which utilizes a 330 limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-232 RS-232 pins on "E" family devices can withstand HBM ESD events to ±15kV. IEC1000-4-2 IEC1000-4-2 Testing to suffer an ESD event are those that are exposed to the outside world (the RS-232 RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device's RS-232 RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 RS-232 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The "E" device RS-232 RS-232 pins withstand ±15kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±8kV. All "E" family devices survive ±8kV contact discharges on the RS-232 RS-232 pins. The IEC 1000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely Typical Performance Curves VCC = 3.3V, TA = 25oC 25 VOUT+ 4 20 SLEW RATE (V/µs) TRANSMITTER OUTPUT VOLTAGE (V) 6 2 1 TRANSMITTER AT 250kbps 1 OR 2 TRANSMITTERS AT 30kbps 0 -2 15 -SLEW +SLEW 10 VOUT - -4 -6 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE 15 5 0 1000 2000 3000 4000 LOAD CAPACITANCE (pF) FIGURE 14. SLEW RATE vs LOAD CAPACITANCE 5000 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Typical Performance Curves VCC = 3.3V, TA = 25oC (Continued) 45 45 ICL324XE ICL324XE ICL3221E ICL3221E - ICL3232E ICL3232E 250kbps 40 40 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 250kbps 35 30 25 120kbps 20 15 20kbps 10 35 30 120kbps 25 20 20kbps 15 10 5 5 0 0 0 1000 2000 3000 4000 FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA NO LOAD ALL OUTPUTS STATIC 3.0 ICL3221E ICL3221E - ICL3232E ICL3232E 2.5 2.0 1.5 1.0 ICL324XE ICL324XE 0.5 ICL324XE ICL324XE 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics DIE DIMENSIONS: PASSIVATION: ICL3221E/22E/23E/32E ICL3221E/22E/23E/32E: 100 mils x 100 mils (2540µm x 2540µm) ICL3241E/43E ICL3241E/43E: 100 mils x 127 mils (2550µm x 3230µm) Type: Silox Thickness: 13kÅ TRANSISTOR COUNT: ICL3221E ICL3221E: 286 ICL3222E ICL3222E: 338 ICL3223E ICL3223E: 357 ICL3232E ICL3232E: 296 ICL324XE ICL324XE: 464 METALLIZATION: Type: Metal 1: AISi(1%) Thickness: Metal 1: 8kÅ Type: Metal 2: AISi (1%) Thickness: Metal 2: 10kÅ PROCESS: SUBSTRATE POTENTIAL (POWERED UP): 16 4000 5000 FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 3.5 GND 3000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 2000 1000 0 5000 Si Gate CMOS ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL D E BASE PLANE -C- A2 A MAX MIN MAX NOTES - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 -A- MIN A -B- 0.115 0.195 2.93 4.95 - D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 eA L C L C 0.008 0.014 C D 0.735 0.775 D1 0.005 - E SEATING PLANE 0.300 0.325 E1 0.240 0.280 6.10 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 17 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 - 19.68 5 0.13 - 5 7.62 8.25 6 7.11 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 16 0.355 18.66 10.92 2.93 3.81 16 7 4 9 Rev. 0 12/93 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Dual-In-Line Plastic Packages (PDIP) E18.3 (JEDEC MS-001-BC MS-001-BC ISSUE D) N 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL E D BASE PLANE -C- A2 A MAX MIN MAX NOTES - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 -A- MIN A -B- 0.115 0.195 2.93 4.95 - D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 eA L C L C 0.008 0.014 C D 0.845 0.880 21.47 D1 0.005 - 0.13 - 5 E SEATING PLANE 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 18 e 0.204 0.100 BSC eA - L 0.115 2.54 BSC 0.300 BSC eB N 7.62 BSC 0.430 - 0.150 18 0.355 22.35 2.93 5 6 10.92 3.81 18 7 4 9 Rev. 0 12/93 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL E D BASE PLANE -C- A2 A MAX MIN MAX NOTES - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 -A- MIN A -B- 0.115 0.195 2.93 4.95 - e B1 D1 A1 eC B 0.010 (0.25) M C A B S 0.014 0.022 0.356 0.558 - 0.045 0.070 1.55 1.77 8 C 0.008 0.014 C D 0.980 1.060 24.89 D1 0.005 - 0.300 0.325 E1 D1 B B1 eA L C L E SEATING PLANE 0.240 0.280 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 19 e 0.204 0.13 - 5 7.62 8.25 6 6.10 7.11 5 - L 0.115 2.54 BSC 0.300 BSC eB N 7.62 BSC 0.430 - 0.150 20 5 0.100 BSC eA 0.355 26.9 2.93 6 10.92 3.81 20 7 4 9 Rev. 0 12/93 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N INDEX AREA E 0.25(0.010) M 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M E1 INCHES GAUGE PLANE -B- MILLIMETERS 2 0.05(0.002) -A- SEATING PLANE - 0.002 0.006 0.05 0.15 - 0.031 0.051 0.80 1.05 - 0.0075 0.0118 0.19 0.30 9 0.0035 0.0079 0.09 0.20 - D A2 A1 b c 0.10(0.004) B S 0.193 0.201 4.90 5.10 3 E1 e C A M NOTES 1.20 c -C- 0.10(0.004) M MAX - b A D MIN 0.047 A2 L 0.25 0.010 MAX - A1 3 MIN A 1 SYMBOL 0.169 0.177 4.30 4.50 4 e 0.026 BSC E 0.246 L 0.0177 N NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 20 0.65 BSC 0.256 6.25 0.0295 0.45 16 0o - 0.75 6 16 8o 0o - 6.50 7 8o Rev. 0 6/98 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Small Outline Plastic Packages (SSOP) M16.209 (JEDEC MO-150-AC MO-150-AC ISSUE B) N 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E GAUGE PLANE MILLIMETERS 1 2 SYMBOL -A- NOTES 2.00 - 0.002 - 0.05 - - 0.065 0.072 1.65 1.85 - B A D MAX - 0.009 0.014 0.22 0.38 9 C L MIN 0.078 A2 0.25 0.010 SEATING PLANE MAX - A1 3 MIN A -B- 0.004 0.009 0.09 0.25 - D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 21 0.255 5.90 6.50 3 0.197 0.220 5.00 5.60 4 e A2 A1 0.233 E 0.026 BSC H 0.292 L 0.022 N 0.65 BSC 0.322 7.40 0.037 0.55 16 0o - 8.20 - 0.95 6 16 8o 0o 7 8o Rev. 2 3/95 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E MILLIMETERS SYMBOL -A- h x 45o A D -C- A1 B 0.25(0.010) M B S NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 22 0.0118 0.10 0.30 - 0.013 0.0200 0.33 0.51 9 0.0091 0.0125 0.23 0.32 - 0.3977 0.4133 10.10 10.50 3 0.2914 0.2992 7.40 7.60 4 0.050 BSC 1.27 BSC - H C 0.10(0.004) C A M 0.0040 e e - D SEATING PLANE NOTES 2.65 A1 L MAX 2.35 C 3 MIN 0.1043 E 2 MAX 0.0926 B 1 MIN A -B- 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 N 16 0o 1.27 16 8o 0o 6 7 8o Rev. 0 12/93 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Small Outline Plastic Packages (SOIC) M18.3 (JEDEC MS-013-AB MS-013-AB ISSUE C) 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E MILLIMETERS SYMBOL -A- h x 45o A D -C- A1 B 0.25(0.010) M B S NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 23 0.0118 0.10 0.30 - 0.013 0.0200 0.33 0.51 9 0.0091 0.0125 0.23 0.32 - 0.4469 0.4625 11.35 11.75 3 0.2914 0.2992 7.40 7.60 4 0.050 BSC 1.27 BSC - H C 0.10(0.004) C A M 0.0040 e e - D SEATING PLANE NOTES 2.65 A1 L MAX 2.35 C 3 MIN 0.1043 E 2 MAX 0.0926 B 1 MIN A -B- 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N 18 0o 18 8o 0o 7 8o Rev. 0 12/93 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) M20.173 N INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M SYMBOL MAX MILLIMETERS MIN MAX NOTES A 1.20 - 0.05 0.15 - 0.031 0.051 0.80 1.05 - 0.0075 0.0118 0.19 0.30 9 c A2 A1 b c 0.10(0.004) C A M B S 0.0079 0.09 0.20 - 0.252 0.260 6.40 6.60 3 E1 e 0.0035 D -C- 0.10(0.004) M - 0.006 b A D 0.047 0.002 A2 L 0.25 0.010 SEATING PLANE - A1 3 0.05(0.002) -A- MIN 0.169 0.177 4.30 4.50 4 e 0.026 BSC 24 - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.65 BSC 20 0o 20 7 8o Rev. 1 6/98 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Shrink Small Outline Plastic Packages (SSOP) M20.209 (JEDEC MO-150-AE MO-150-AE ISSUE B) N 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E GAUGE PLANE MILLIMETERS 1 2 SYMBOL L MIN MAX NOTES 0.078 - 2.00 - 0.002 - 0.05 - - A2 0.25 0.010 SEATING PLANE MAX - A1 3 MIN A -B- 0.065 0.072 1.65 1.85 - -C- e B C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 25 0.014 0.22 0.38 9 0.009 0.09 0.25 - 0.272 0.295 6.90 7.50 3 0.197 0.220 5.00 5.60 4 e A2 A1 0.009 0.004 E A D 0.25(0.010) M B C D -A- 0.026 BSC H 0.292 L 0.022 N 0.65 BSC 0.322 7.40 0.037 0.55 20 0o - 0.95 6 20 8o 0o - 8.20 7 8o Rev. 2 4/95 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) M28.173 N INDEX AREA E 0.25(0.010) M 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M E1 INCHES GAUGE PLANE -B- MILLIMETERS 2 0.05(0.002) -A- SEATING PLANE - 0.002 0.006 0.05 0.15 - 0.031 0.051 0.80 1.05 - 0.0075 0.0118 0.19 0.30 9 0.0035 0.0079 0.09 0.20 - D A2 A1 b c 0.10(0.004) B S 0.378 0.386 9.60 9.80 3 E1 e C A M NOTES 1.20 c -C- 0.10(0.004) M MAX - b A D MIN 0.047 A2 L 0.25 0.010 MAX - A1 3 MIN A 1 SYMBOL 0.169 0.177 4.30 4.50 4 e 0.026 BSC E 0.246 L 0.0177 N NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 26 0.65 BSC 0.256 6.25 0.0295 0.45 28 0o - 0.75 6 28 8o 0o - 6.50 7 8o Rev. 0 6/98 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Shrink Small Outline Plastic Packages (SSOP) M28.209 (JEDEC MO-150-AH MO-150-AH ISSUE B) N 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E GAUGE PLANE MILLIMETERS 1 2 SYMBOL L MIN MAX NOTES 0.078 - 2.00 - 0.002 - 0.05 - - A2 0.25 0.010 SEATING PLANE MAX - A1 3 MIN A -B- 0.065 0.072 1.65 1.85 - -C- e B C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 27 0.014 0.22 0.38 9 0.004 0.009 0.09 0.25 - 0.390 0.413 9.90 10.50 3 0.197 0.220 5.00 5.60 4 e A2 A1 0.009 E A D 0.25(0.010) M B C D -A- 0.026 BSC H 0.292 L 0.022 N 0.65 BSC 0.322 7.40 0.037 0.55 28 0o - 0.95 6 28 8o 0o - 8.20 7 8o Rev. 1 3/95 ICL3221E ICL3221E, ICL3222E ICL3222E, ICL3223E ICL3223E, ICL3232E ICL3232E, ICL3241E ICL3241E, ICL3243E ICL3243E Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 MIN MAX MILLIMETERS MIN MAX NOTES A 3 L 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B -C- 0.25(0.010) M C 0.10(0.004) C A M 9 0.32 - 0.6969 0.7125 17.70 18.10 3 0.2914 0.2992 7.40 7.60 4 0.05 BSC 1.27 BSC - H A1 B 0.51 0.23 e e 0.33 0.0125 D h x 45o A D 0.0200 0.0091 E -A- 0.013 C SEATING PLANE B S 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 28 0o 28 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 28 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369