ICD2042A VGA/8514 ICD2042A2 ICD2042A1 ICD2061A ICD2042A3 ICD2042A4 ICD2042A5 - Datasheet Archive

 

Dual VGA Clock Generator D D Features D Three independent clock outputs: 5V operation Super buffered reference clock D and 8514.

 

ICD2042A ICD2042A Dual VGA Clock Generator D D Features D Three independent clock outputs: 5V operation Super buffered reference clock D and 8514. These parts a single monolithic device, thus lowering technology separate pixel and memory clocks and VGA, synthesize all the required frequencies in Lowpower, highspeed CMOS D Phaselocked loop output range of Functional Description manufacturing Available in 16pin SOIC package costs and significantly reducing the printed circuit board space required. 1350 kHz - 120 MHz D The single 14.318 MHz crystal D Ideally suited for VGA, XGA, and proliferation graphics chip sets which generate output frequency present of in video the DOS graphics select information. crystal PC clock outputs for the pixel clock and the board. requires no external components ICD2042A ICD2042A different Sophisticated internal loopfilter A frequency memory clock which are chosen via select can new oscillators family of per features two The community often require as many as six 8514 graphics applications D ator supports new designs using the newer screen resolutions, and different memory PC system bus or from The ICD2042A ICD2042A Dual VGA Clock Gener speeds derived from standards, support for various monitors, increasing Phaselocked loop oscillator input independent D lines. Threestate output control disables replaces stateable outputs and direct support for outputs for test purposes D synthesis parts from Cypress/IC Designs oscillators required to build such multi popular Changeonthefly frequency selection function graphic boards as EGA, VGA, codes. the large number of these Additional features include three graphics chip set selection de supports most popular VGA/8514 VGA/8514 chip sets Logic Block Diagram XBUF f(REF)/ XTALIN n XTALOUT 7 VCO PCLK Internal Loop Filter ROM P0 P1 P2 P3 Charge Pump Phase Detector m 7 PhaseLocked Loop #1 MCLK PLL #2 M0 M1 M2 OE GND VDD AVDD ICD2042A2 ICD2042A2 Pin Configuration SOIC Top View XBUF MCLK OE GND f(REF)/XTALIN XTALOUT P0 M0 1 2 3 4 5 6 7 8 AVDD PCLK P3 VDD M2 P2 P1 M1 16 15 14 13 12 11 10 9 ICD2042A1 ICD2042A1 Cypress Semiconductor Corporation D 3901 North First Street 1 D San Jose D CA 95134 D 408-943-2600 January 1995 - Revised April 1995 ICD2042A ICD2042A Pin Summary Name Number Description XBUF 1 Buffered reference frequency output (14.318 MHz) MCLK 2 Memory Clock output (see OE 3 Output Enable, threestates output when signal is LOW (pin has internal pullup) GND 4 Ground f(REF)/ XTALIN[1] 5 Reference Oscillator input for all internal phaselocked loops (nominally from a parallelresonant 14.318MHz crystal). XTALOUT[1] 6 Oscillator output to a reference crystal. (Pin is noconnect if external reference oscillator or PC System Bus clock signal is used.) P0 7 Pixel Clock Select inputBit 0 (internal pullup) M0 8 Memory Clock Select inputBit 0 (internal pullup) M1 9 Memory Clock Select inputBit 1 (internal pullup) P1 10 Pixel Clock Select inputBit 1 (internal pullup) P2 11 Pixel Clock Select inputBit 2 (internal pullup) M2 12 Memory Clock Select inputBit 2 (internal pullup) VDD 13 +5V to I/O Ring P3 14 Pixel Clock Select inputBit 3 (internal pulldown) PCLK 15 Pixel Clock Output AVDD 16 +5V to Analog Core (special order: bond VDD to AVDD internally) Table 1) General Considerations Table 1. Memory Clock ROM Decode Options 2042-23 2042-24 2042-27 Frequencies in MHz M2 M1 M0 Word Design Recommendations The ICD2061A ICD2061A, with its ability to program the output frequencies, is recommended for designs in which a fixed ROM would be inconvenient and/or the desired volume does not warrant a custom ROM. 0 48.000 40.000 0 1 1 39.800 39.800 41.000 1 0 2 66.000 66.000 41.500 1 1 3 50.000 50.000 42.000 1 0 0 4 56.644 56.644 42.500 1 0 1 5 32.200 32.000 43.000 1 1 0 6 44.000 44.000 44.000 1 1 1 7 39.800 39.800 48.000 ThreeState Output Operation At any time during operation, the select lines can be changed to select a different frequency. When this occurs, the internal phaselocked loop will immediately seek the newly selected frequency. During the transition period, the clock output will multiplex glitchfree to the reference signal until the PLL settles to the new frequency. The OE signal, when pulled LOW, will threestate the MCLK, PCLK, and XBUF output lines. This supports procedures such as automated testing, where the clock must be disabled. The OE signal contains an internal pullup but should be tied to VDD if not used. Normally, the MCLK select lines are hardwired during manufacturing to correspond to the desired memory speed. A different memory clock frequency output may be generated by changing the memory select lines of the ICD2042A ICD2042A. The timing for this transition is shown in AC Characteristics. Note: 1. 48.000 0 The output frequency value of the Pixel clock oscillator (PCLK) is selected by the four Pixel clock selection inputs: P0, P1, P2, and P3. This feature allows the ICD2042A ICD2042A to support different video configurations. The output frequency value of the Memory clock oscillator (MCLK) is selected by the three Memory clock selection inputs: M0, M1, and M2. The selection table is shown in Table 1. 0 0 Pixel and Memory Clock Oscillator Selection 0 0 The ICD2042A ICD2042A is currently a custom order only. 0 For best accuracy, use a parallelresonant crystal, asume CLOAD = 17 pF . 2 ICD2042A ICD2042A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C not tested.) Supply Voltage to Ground Potential . . . . . . . . . -0.5V to +7.0V Operating Range Ambient DC Input Voltage . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V Temperature VDD & AVDD Storage Temperature . . . . . . . . . . . . . . . . . . . -65_C to +150_C 0_C v TAMBIENT v 70_C 5V ± 5% Max soldering temperature (10 sec) . . . . . . . . . . . . . . . . . 260_C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IADD Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Power Supply Current Analog Power Supply Current Test Conditions IOH = -4.0mA IOL = 4.0 mA Except crystal inputs Except crystal inputs VIH = VDD-0.5V VIL= 0.5V (Threestate) Inputs @ VDD and GND Switching Characteristics Over the Operating Range[2] Parameter Name f(REF) t(REF) t1 t2 t3 t4 t5 t6 t7 tMUXREF Reference Frequency Ref Clock Period Input Duty Cycle Output Period Output Duty Cycle Rise Time Fall Time ThreeState Clk Valid Clk Stable t8 t9 f(REF) Mux Time tfreq2 Mux Time Notes: Description Min. VDD-0.4 2.0 Min. Max. 0.4 0.8 150 -250 10 60 6 Typ. Max. Reference Oscillator nominal value[3] 4 14.318 25 1 f(REF) 40 69.8 250 Duty cycle for the input oscillators defined 25% 50% 75% as t1A t1B Clock output time period 8.3 2857 120 MHz 350 KHz Duty cycle for the outputs defined as 40% 60% t1A t1B (measured at 2.5V) Rise time for the outputs into a 25 pF load 4 Fall time for the outputs into a 25 pF load 4 Time for the outputs to go into threestate 12 mode after OE signal deassertion Time for the outputs to recover from three 12 state mode after OE signal goes HIGH Time required for the outputs to become 3.4 5 6.9 valid after P0-P3 or M0-M2 select signals change value Time clock output remains HIGH while t(REF)/2 3(t(REF)/2 output muxes to reference frequency Time clock output remains HIGH while tfreq2/2 3(tfreq2)/2 output muxes to new frequency value 2. Input capacitance is typically 10 pF, except for the crystal pads. Unit V V V V mA mA mA mA mA Unit MHz ns ns ns ns ns ns msec ns ns 3. Different reference frequencies require a custom ROM; standard parts use 14.31818 MHz, unless otherwise stated. 3 ICD2042A ICD2042A Switching Waveforms Duty Cycle Timing t1B t1A ICD2042A3 ICD2042A3 Rise and Fall Times f(REF) PCLK MCLK XBUF t(REF) t1 t2 t4 90% t5 90% 10% 10% ICD2042A4 ICD2042A4 ThreeState Timing OE t6 PCLK MCLK Selection Timing P0-P3 M0-M2 t7 THREESTATE OUTPUT ICD2042A5 ICD2042A5 Original Frequency VCO Settle Time New Frequency tMUXREF (Internal MUXREF) PCLK MCLK t(REF) t8 t9 ICD2042A6 ICD2042A6 4 ICD2042A ICD2042A Test Circuit DEVICE UNDER TEST VDD + AVDD 22W 2.2 mF Tantalum + GND ICD2042A7 ICD2042A7 Ordering Information Ordering Code ICD2042A ICD2042A Package Name S1 CLOAD CLK out Operating Range Package Type Commercial[4] 16Pin SOIC Note: 4. 0°C to +70°C Document #: 38-00402 5 ICD2042A ICD2042A Package Diagram 16Lead Molded SOIC S1 ICD2042A8 ICD2042A8 E Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure of the product may reasonably be expected to result in significant 6 injury to the user. The inclusion of Cypress Semiconductor products in lifesupport systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.