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Part Manufacturer Description Datasheet BUY
LTC1090CSW Linear Technology LTC1090 - Single Chip 10-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1293DCSW Linear Technology LTC1293 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1289CCSW#TRPBF Linear Technology LTC1289 - 3 Volt Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1293BCSW#TRPBF Linear Technology LTC1293 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1296BISW#PBF Linear Technology LTC1296 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1296DCSW#TRPBF Linear Technology LTC1296 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy

IC sequential DATA BASE

Catalog Datasheet MFG & Type PDF Document Tags

pin DIAGRAM OF IC 7474

Abstract: INTERNAL DIAGRAM OF IC 7474 . CLK IC The 3.57/3.68 MHZ crystal oscillator input clock for the core PLL. This is the base , Description IC Data bus enable. When this input is low, the data bus, D[31:0], is put into a high , the PLL clock; when low, the internal PLL output is used. TDI IC Test interface data input , updated. If the instruction would normally have overwritten the base with data (for example, an LDM , .1-3 1.4.5 Data Cache
Intel
Original

EC-QV44A-TE

Abstract: DBE103 while MCLK is low. DBE IC Data bus enable. When this input is low, the data bus, D[31:0] is put , contain data to be accessed. The MAS signals follow address bus timing. MCCFG[2:0] IC Memory , MCLK to achieve similar effects. MSE IC Memory request/sequential enable. When this input is , PLL output is used. TDI IC Test interface data input. Note this pin does NOT have an internal , would normally have overwritten the base with data (for example, a LDM instruction with the base in the
Digital Equipment
Original
Abstract: IC Data bus enable. W hen this input is low, the data bus, D[31:0] is put into a high impedance , -bit data bus contain data to be accessed. The M AS signals follow address bus timing. MCCFG[2:0] IC , place of the PLL clock, when low the internal PLL output is used. TDI IC Test interface data , data (for example, a LDM instruction with the base in the transfer list), the original value in the base register is restored. W hen either a prefetch or data abort occurs, the SA-110 performs the -
OCR Scan
21281-DA 21281-EA 21A81-11 21B81-01 21B81-02

21281EB

Abstract: FA21281FB . CLK IC The 3.57/3.68 MHZ crystal oscillator input clock for the core PLL. This is the base , Description IC Data bus enable. When this input is low, the data bus, D[31:0], is put into a high , the PLL clock; when low, the internal PLL output is used. TDI IC Test interface data input , updated. If the instruction would normally have overwritten the base with data (for example, an LDM , .1­4 1.4.5 Data Cache
Intel
Original
21281EB FA21281FB crystal oscillator 3.57MHz fa21281 MRC 1435 21281AB

MRC 1435

Abstract: STR 6252 equivalent operations (when nRW is high), the output data will become valid while MCLK is low. ABE ABORT IC IC , updated. If the instruction would normally have overwritten the base with data (for example, an LDM , .1­4 1.4.5 Data Cache , .5­3 5.2.3 Register 2 ­ Translation Table Base .5­4 , Disabling the Icache. 6­2 Data Cache (Dcache
Intel
Original
STR 6252 equivalent 21281DB

AP8942A

Abstract: aP89XX AP8942A 42" OTP VOICE IC VOICE SECTION COMBINATIONS Voice files created by the PC base developing system , AMBITION ELECTRONICS CO.,LTD AP8942A 42" OTP VOICE IC FEATURES Standard CMOS process. Embedded , available for voice block combinations. User selectable PCM or ADPCM data compress. Two triggering modes , ~ S8 to trigger up to 32 voice groups; SBT for sequential trigger. - CPU Parallel Trigger Mode ­ , @126.comszyadi@126.comWEBwww.cszyadi.com 1/20 AMBITION ELECTRONICS CO.,LTD AP8942A 42" OTP VOICE IC PIN CONFIGURATIONS 20PIN DIP
Ambition Electronics
Original
aP89XX AP89042 circuit diagram of ic TDA2822 VOICE IC ap89042 16pin TDA2822 s P8942A

Logitech mouse ic

Abstract: hulapoint easy-to-use single-chip encoder that interfaces to an innovative sensor developed by Fujitsu. The IC and , two-button mice and Logitech three-button mice. The IC automatically detects the port type (serial or PS/2 , device operating at 4 MHz. The low power consumption of the IC makes it suitable for battery operated systems. In serial mode, like any standard serial mouse, the IC can draw power from the RS232 lines of , RIGHT BUTTON BUTTON BUTTON Data Buffer Switch Interface PS2CLK PS/2 Communication Port
Semtech
Original
Logitech mouse ic hulapoint logitech x 530 TC55RP5002ECB713 logitech mouse encoder logitech ps2 mouse DOC7-DMP-DS-109

Logitech mouse ic

Abstract: logitech mouse encoder 20 pin ic that interfaces to an innovative sensor developed by Fujitsu. The IC and sensor together make the , two-button mice and Logitech three-button mice. The IC automatically detects the port type (serial or PS/2 , . The HulaCoderTM is a CMOS device operating at 4 MHz. The low power consumption of the IC makes it suitable for battery operated systems. In serial mode, like any standard serial mouse, the IC can draw , and operate concurrently. FUNCTIONAL DIAGRAM LEFT MIDDLE RIGHT BUTTON BUTTON BUTTON Data Buffer
Semtech
Original
logitech mouse encoder 20 pin ic IC sequential DATA BASE Logitech PS2 mouse ic logitech mouse schematic logitech logitech mouse circuit diagram DOC7-DMP-DS-108

clap switch applications

Abstract: KEY16 hold (for all keys) - R epeat (for all keys) - Sequential playing (only for KEY1) FLAG options: - Busy , Description The HT3894 is a single chip melody and voice synthesis IC im plem ented in th e CMOS tech nology. I t includes an on-chip voice and melody ROM for storing data, a key ROM of key ad dress pointers , prepared for fabrication except th e key option and ROM data. The custom er's key function, voice, and , - 4 K x 14 64x16 iL ROM Address Counter Voice ROM 64K x 5 Time Base Generator -4-ÒVD D + - 0 vss
-
OCR Scan
KEY16 clap switch applications Turkey in the straw SONG LONG clap switch W80 RESISTOR KEY10 KEY11 KEY12 KEY13 KEY14 KEY15

8 pin ic base socket round pin type lead

Abstract: IC sequential DATA BASE data output is sequential, with the data from address(n) followed by the data from address(n+1). The , FUJITSU SEMICONDUCTOR DATA SHEET D S 0 5 -1 1 1 0 2 -2 E M Ê Ë tm Ë Ê Ê Ê Ê Ê Ê Ê M , I I I I I I Function Address Input Row Address Strobe Column Address Strobe Write Enable Data (DQ , Supply (+3.3 V) Ground (0 V) No Connection Serial PD Address Input Serial PD Clock Serial PD Address/Data Input/Output I/O Data Input/Data Output - - - RAS CAS WE DQMBo to DQMB7 CLKo, CLK 1 N.C
-
OCR Scan
8 pin ic base socket round pin type lead MB8502S064AC-100/-84/-67 MB8502S064AC MB81117822A MB8502S064AC-100 MB8502S064AC-84 MB8502S064AC-67

ARM710a

Abstract: MRC 453 extension, see ·11.10 Use of the ALE Pin on page 11-14. DIN[31:0] IC Input data bus. During read , nENDOUT is HIGH. DBE IC Data bus enable. When this input is LOW, the nENDOUT output is forced , instruction would normally have overwritten the base with data (i.e. LDM with the base in the transfer list , Preliminary Data Sheet Document Number: ARM DDI 0033D Issued: September 1995 Copyright Advanced , 1995 AW AP AP Created using ARM710a version C and ARM710C version C Data Sheets. First formal
ARM
Original
ARM710 ARM710a MRC 453 CP15 MRC 452 mrc 438

s5l840fx

Abstract: S5L840F CPAD-WALTZ(S5L840F) Internet Audio Decoder for Flash Memory Media Data Sheet INTRODUCTION S5L840F is a single chip digital audio player IC supporting various compressed audio format on Flash , Serial Data In for IIS 87 LRCLK/P7.1 B Left-Right Clock for IIS 88 INTVSS4 P , Data Out for IIS 91 BCLK/P7.3 B Bit Clock for IIS 92 MCLK/P7.4 B Over-sampling , for Program Memory - 4M byte for Data Memory MCU Team LSI Division System LSI Business
Samsung Electronics
Original
MAC2424 s5l840fx calmRISC16 P9336 CalmRISC-16 and pin diagram of MMC 4017 CALMRISC16TM RISC16 128-TQFP-1414

5V piezo buzzer

Abstract: low cost eeprom programmer circuit diagram encoding. The encoded data is programmed into a IVR device by using our IVR writer. The sound is ready to , Voice ROM Conventional voice ROM utilizes mask ROM technology to store sound data. A semiconductor manufacturing photo mask corresponding to the sound data has to be made. With this mask, the sound data can be , sound ROMs. First, the IVR is based on OTP EPROM technology. Sound data is programmed into the memory , generate and program sound data using one of our user-friendly development systems within their own
Integrated Silicon Solution
Original
IS22C011 5V piezo buzzer low cost eeprom programmer circuit diagram Voice Record Integrated Circuits IS22VP003 EEPROM COPIER circuit VP81996INTRO
Abstract: device to bus host Data Acknowledge READ Command STOP Condition NO Acknowledge Figure 8: Sequential , FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 1.0 · · · · Features 2 ä 2.0 , . The FS6477 is a CMOS clock generator IC designed to minimize cost and component count in a variety of , CLK_F/S1 MODE FS6477 ISO9001 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC , VSS XIN XOUT XTUNE CLK_F/S1 CLK_E/S0 MODE CLK_D VSS CLK_C CLK_B VDD CLK_A SCL Serial interface data American Microsystems
Original

FS6477-02

Abstract: FS6477-02 AMERICAN MICROSYSTEMS, INC. Three-PLL VCXO Programmable Clock Generator IC , CMOS clock generator IC designed to minimize cost and component count in a variety of electronic , . Three-PLL VCXO Programmable Clock Generator IC Preliminary Information July 2000 Table 1: Pin , SDA Serial interface data input/output 2 P VDD Power supply (3.3V nominal) 3 P , -02 AMERICAN MICROSYSTEMS, INC. Three-PLL VCXO Programmable Clock Generator IC Preliminary Information
American Microsystems
Original

FS6477-01

Abstract: AMI AMERICAN FS6477-01 Three-PLL VCXO Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Advance , generator IC designed to minimize cost and component count in a variety of electronic systems. It is , Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Advance Information April 2000 Table 1 , DI O SDA Serial interface data input/output 2 P VDD Power supply (3.3V nominal , -01 Three-PLL VCXO Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Advance Information
American Microsystems
Original
AMI AMERICAN

son-8 IC

Abstract: HN58X2432SI : 10 Cycles (Page write mode) · Data retention: 10 Years Rev.1.00, Oct.27.2003, page 1 of 21 , TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel SON 8-pin: 3,000 IC/reel · Temperature range , data input/output WP Write protect VCC Power supply VSS Ground Block Diagram , characteristics and data retention. 2. Vin (min): -3.0 V for pulse width 50 ns. 3. Should not exceed VCC + 1.0 , ns Data in setup time tSU.DAT 100 ns Input rise time tR 300
Renesas Technology
Original
HN58X2432SI HN58X2464SI son-8 IC 063 8pin HN58X2432SFPI HN58X2432SNI HN58X2432STI HN58X2432SI/HN58X2464SI REJ03C0135-0100Z ADE-203-1385 D-85622

son-8 IC

Abstract: TM 1628 pins bit pin write mode) 5 · Data retention: 10 Years Rev.4.00, Oct.21.2003, page 1 of 21 HN58X2408I , Shipping tape and reel TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel SON 8-pin: 3,000 IC/reel , Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data , . Including electrical characteristics and data retention. 2. Vin (min): -3.0 V for pulse width 50 ns. 3 , Notes ns 1 Start setup time tSU.STA 600 ns Data in hold time tHD.DAT
Renesas Technology
Original
TM 1628 pins bit pin HN58X2408FPI HN58X2408TI HN58X2416 HN58X2416FPI HN58X2416TI HN58X2408I/HN58X2416I HN58X2432I/HN58X2464I REJ03C0131-0400Z ADE-203-1108C HN58X24

son-8 IC

Abstract: HN58X2408SFPI : 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V) · Endurance: 10 Cycles (Page write mode) 5 · Data , TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel SON 8-pin: 3,000 IC/reel · Temperature range , Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output , electrical characteristics and data retention. 2. Vin (min): -3.0 V for pulse width 50 ns. 3. Should not , ns Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 100
Renesas Technology
Original
HN58X2408SFPI HN58X2408SFPIE HN58X2408SNI HN58X2408STI HN58X2416SFPI HN58X2416SFPIE HN58X2408SI/HN58X2416SI REJ03C0097-0100Z
Abstract: TTT ill DATA BUS ACTIVITY SPD 16 MB8502S072AG-100/-84/-67 SEQUENTIAL READ Sequential Read , sequence of address, acknowledge and data transfer. The data output is sequential, with the data from , data for each acknowledge received. Fig. 5 - SEQUENTIAL READ SLAVE ADDRESS BUS ACTIVITY : - 1 I , +2) I I I I I I I I I I I I I I I I DATA (n+x) 4. DC C H A R A C T E R IS T IC S Value , Function Address Input Row Address Strobe Column Address Strobe W rite Enable Data (DQ) Mask Clock Input -
OCR Scan
MB8502S072AG B81117822A MB8502S072AG-100 MB8502S072AG-84 D-63303 F9802
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