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Part Manufacturer Description Datasheet BUY
DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
LT1490AIS8#TRA1PBF Linear Technology Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps visit Linear Technology - Now Part of Analog Devices
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit visit Linear Technology - Now Part of Analog Devices
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit visit Linear Technology - Now Part of Analog Devices

IC of XOR GATE

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: g ic diagram , one in p u t o f the XOR gate is co nn e cte d to a sin g le p ro d u c t term , w h ile th e second inp u t is connected to the o u tp u t o f th e OR logic array. The XOR gate o u tp u t feeds th e in p u t o f th e D flip -flo p . The w ay in w hich the XOR gate is used to , co nsistin g o f a basic D -typ e flip -flo p driven b y an XOR gate. This allows the user to choose , d m a n ip u la tio n o f th e XOR gate inp u ts and the D flip -flo p output. The tra n sfe r fu -
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PAL32VX10C

Abstract: PAL32VX10 m acroce ll lo g ic diagram , one in p u t o f the XOR gate is c o n n e cte d to a sing le p ro d u , o n sistin g o f a basic D -typ e flip -flo p drive n b y an XOR gate. This allows the user to , XOR gate o u tp u t feeds th e in p u t o f th e D flip -flo p . The w ay in w hich the XOR g ate is , D flip -flo p o p tio n is im plem ented directly. In this c o n fig u ra tio n , the XOR gate o n , istica te d m a n ip u la tio n o f th e XOR gate inputs and the D flip -flo p outp ut. The tra n sfe r
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24v xor IC

Abstract: Qo GND - GATE ARRAT ( N o te ) F F E A T U R E Cell ;0 R . XOR. POLARITY : F E A , utput > Note ; -777777K D ata unknown ic o mm 1-4 CMOS EPL 2 0 B Configurations of , It EPL 20B SERIES G E N E R A L D ESC RIPTIO N R IC O H E P L 20B Series are Field-programmable , A T IO N 10-INPUT, 8-O UTPUT, AND -OR/XOR A R R A Y 1 2 -IN PUT, 6 O U T P U T , AND -OR/XOR A R R A , class="hl">XOR ARRAY 8-INPUT. 6-FEEDBACK, 2-INPUT/OUTPUT. 8-OUTPUT, 6 - REGISTERED. AND-OR/XOR ARRAY 8
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24v xor IC 16RP8 16RP6 16RP4 EPL16P2B EPL16RP4B

CM3000

Abstract: 20XV10B OUTPUT LOGIC MACROCELLS - XOR Gate C apability on all O utputs - Full Function and Param etric C om , XOR bit controls the polarity of the output. The register is clocked by the lowto-high transition of , common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array , combinatorial output The XOR bit con trols the polarity of the output. The inverting output buffer is enabled by , Electronic Signature is always available regardless of the security cell state. D E V IC E P R O G R A M M
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CM3000 20XV10B PAL12L10 20L10 20X10 GAL20XV10B

DM4011

Abstract: "XOR Gate" 12.5 Gb/sec XOR gate (Preliminary Information) Electrical Characteristics1 2. In the case of , DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Description The DM4011 is a high-speed , +39 (06) 5582904 FAX +39 (06) 5587394 DM4011 12.5 Gb/sec XOR gate (Preliminary Information , (06) 5587394 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Eye Diagram Performance DM4011 used as XOR gate. 10.709 Gb/s NRZ inputs, 1.8 Vpp differential on DIN1 and DIN2. Power supply
Digimimic
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IC 4011 IC of XOR GATE DATA SHEET IC 4011 DELL power supply diagram Applications of "XOR Gate"

"XOR Gate"

Abstract: karnaugh map indicated in the macrocell logic diagram, one input of the XOR gate is connected to a single product term, while the second i nput is connected to the output of the OR logic array. The XOR gate output feeds the input of the D flip-flop. The way in which the XOR gate is used to synthesize the different flip-flop , configuration, the XOR gate on the input o f the flip-flop can be used to program the logic polarity of the , sophisticated manipulation of the XOR gate inputs and the D flip-flop output. The transfer function of a J-K
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karnaugh map 8 pin dip j k flipflop ic PAL22RX8A PAL24A
Abstract: Electrical Erasure ( , true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high , common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array , combinatorial output. The XOR bit con trols the polarity of the output. The inverting output buffer is enabled , of SCR induced latching. E L E C T R O N IC S IG N A T U R E An electronic signature word is -
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GAL20XV10

IC of XNOR GATE

Abstract: N20R MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2-Input XOR/XNOR Gate The MC1OE/100E107 is a quint 2-input XO R /XN O R gate. The function output F is the OR of all five XOR outputs, while F is the , . Propagation Delay · O R /NOR Function Outputs · Extended 100E V g g Range of - 4.2V to - 5.46V · 7 5 k ii Input Pulldown R esistors M C10E107 MC100E107 QUINT 2-INPUT XOR/XNOR GATE Pinout: 2B-Lead PLCC , 500 410 725 600 100 250 500 410 7 25 600 1 000 PS 'S K E W W ith in -D e v ic e S
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IC of XNOR GATE N20R MC10E107
Abstract: Retention â'¢ TEN OUTPUT LOGIC MACROCELLS â'" XOR Gate Capability on all Outputs â'" Full Function , XOR bit controls the polarity of the output. The register is docked by the lowto-high transition of , into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed to , output enable that is common to aU XOR macrocells. In Feedback mode, the state of the I/O pin is , the combinatorial output The XOR bit con­ trols the polarity of the output The inverting output -
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PAL22R

Abstract: "XOR Gate" flipflop consisting of a basic D-type flip-flop driven by an XOR gate. This allows the user to choose the , of the OR logic array. The XOR gate output feeds the input of the D flip-flop. The way in which the , . The D flip-flop option is implemented directly. In this configuration, the XOR gate on the input of , sophisticated manipulation of the XOR gate inputs and the D flip-flop output. The transfer function of a J-K , ARRAY LOGIC NUMBER OF ARRAY INPUTS OUTPUT TYPE-RX = Registered XOR NUMBER OF OUTPUTS
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PAL22R

IC of XNOR GATE

Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2-Input XOR/XNOR G ate The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the , MC100E107 â'¢ 600ps Max. Propagation Delay â'¢ OR/NOR Function Outputs QUINT 2-INPUT XOR/XNOR GATE â'¢ Extended 100E V e e Range of - 4.2V to - 5.46V â'¢ 75k£i Input Pulldown Resistors Pinout , FN SUFFIX v e e [ P L A S T IC P A C K A G E C A S E 7 7 6 -0 2 15 ] 0 3 © °1 a
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toggle type flip flop ic

Abstract: crc-16 implementation quad D-type flip flop with XOR gate or 2:1 MUX data inputs (D0A-D3A, D0B-D3B). When the DA and DB inputs are connected together, data to each of the four stages is the XOR of this input and the SEL Input , DnA = DnB Output Qn (t+1) 10G024 OPERATION (Truth Table with XOR Gate Inputs Configured) Function , device is configured for XOR gate inputs by connecting together the DA and DB inputs and using this as , MUX select or XOR gate inputs Individual flip flop clock inputs Common clock input to all four flip
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toggle type flip flop ic crc-16 implementation QQ00405 10G024K 10G061 90GHS 050P3

IC of XNOR GATE

Abstract: IC of XOR GATE Introduction A configurable multifunction logic gate is a versatile IC that can be used to create pulse , circuits that are created by adding an external resistor and capacitor to the input pin of the logic gate , falling edge of a clock signal. An exclusive OR gate provides a dual edge detector circuit, as shown in , Figure 7. A resistor, capacitor and XOR gate with an inverted input forms an alternative method to create , a delay at powerup and a quick warning at powerdown buffer gate. Figure 14 provides an example of
ON Semiconductor
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AND8408/D AND8408 ULLGA8 Package XOR schmitt trigger create pulse frequency doubler
Abstract: * QUINT 2-INPUT XOR/XNOR GATE SYNERGY SY10E107 SY100E107 SEMICONDUCTOR FEATURES â  â  600ps max. propagation delay â  Extended 100E V e e range of -4.2V to -5.5V â  True and , levels DESCRIPTION The SY10/100E107 offer five 2-input XOR/XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and complementary outputs are provided. â -
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T0013 SY10E107JC J28-1 SY10E107JCTR SY100E107JC SY100E107JCTR
Abstract: function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and , * SYNERGY QUINT 2-INPUT XOR/XNOR GATE SY10E107 SY100E107 SEMICONDUCTOR DESCRIPTION FEATURES 600ps max. propagation delay Extended 100E V ee range of -4.2V to -5.5V True and complementary , 75K£2 input pulldown resistors ESD protection of 2000V The SY10/100E107 offer five 2-input XOR/XNOR , Data Inputs Q o -Q 4 XOR Outputs Q 0-Q 4 XNOR Outputs F OR Output F NOR Output -
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XOR schmitt trigger

Abstract: Quad NOR / XTR5486 Quad XOR Description 1 1A Input A of first 2-input gate. 2 1B , ² Schmitt trigger inputs. â² Compatible with NAN, NOR, XOR, INVERTER functions of the standard 54HC , Input A of first 2-input gate / Input of first inverter. 2 1B / 1Y Input B of first 2-input gate / Output of first inverter. 3 1Y / 2A Output of first 2-input gate / Input of second inverter. 4 2A / 2Y Input A of second 2-input gate / Output of second inverter. PR E Pin
X-REL Semiconductor
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XTR54000 DS-00443-13

PAL20L10 LATTICE

Abstract: Year Data Retention â'¢ TEN OUTPUT LOGIC MACROCELLS â'" XOR Gate Capability on all Outputs â'" Full , term. The output is enabled while this product term is true. The XOR bit controls the polarity of the , for the combinatorial output. The XOR bit con­ trols the polarity of the output. The inverting , Combinatorial with Polarity â'¢ PRELOAD AND POWER-ON RESET OF ALL REGISTERS â'¢ APPLICATIONS INCLUDE: â , (E2 floating gate technology to provide ) the highest speed Exclusive-OR PLD available in the market
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PAL20L10 LATTICE
Abstract: with a more sophisticated manipulation of the XOR gate inputs and the D flip-flop output. j ^ 0 0 , XOR gate on the input of the flip-flop can be used to program the logic polarity of the transfer , indicated in the macrocell logic diagram, one input of the XOR gate is connected to a single product term , input of the D flip-flop. The way in which the XOR gate is used to synthesize the different flip-flop , macrocell. Note that the macrocell data input is a function of the two-input XOR gate, whose inputs are -
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MIL-STD-883 PAL22V10 PAL32VX10/A 02S7S3
Abstract: function^utput, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and , * QUINT 2-INPUT XOR/XNOR GATE SYNERGY SEMICONDUCTOR FEATURES SY10E107 SY100E107 , function outputs ESD protection of 2000V Fully compatible with Industry standard 10KH, 100K I/O levels â  Extended 100E V e e range of -4.2V to -5.46V â  Internal 75KQ input pulldown resistors â  Fully compatible with Motorola MC10E/100E107 The SY10E107 and SY100E107 offer five 2-input XOR/ XNO -
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transistor C710

Abstract: C712 transistor . Frequency (Load Current = lRM s of fundamental) Ic , Collector-to-Emitter Current (A) 1 10 VCE , Eotr, t(j^oif^, tf GATE VOLTAGE D U T. Fig. 18c - Test Waveforms for Circuit of Defining E , bitemational ^Rectifier INSULATED GATE BIPOLAR TRANSISTOR WITH ULTRAFAST SOFT RECOVERY DIODE , Co-packaged IGBTs are a natural extension of International Rectifier's well known IGBT line. They provide the convenience of an IGBT and an ultrafast recovery diode in one package, resulting in substantial benefits to a
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IRGPC30UD2 transistor C710 C712 transistor diode C710 transistor C715 c714 C715 diode C-714 C-715 C-716
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