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PIM400K6Z GE Critical Power PIM400 Series; ATCA Board Power Input Module, -36 to -75 Vdc; 400W/10A, I2C Digital Interface & Short pins (3.68mm) visit GE Critical Power
AXA016A0X3-SR12 GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
AXA016A0X3-SR12Z GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
EHHD010A0B41-18HZ GE Critical Power DC-DC Regulated Power Supply Module visit GE Critical Power
EHHD036A0F41-SZ GE Critical Power DC-DC Regulated Power Supply Module visit GE Critical Power
EHHD024A0A41-18HZ GE Critical Power DC-DC Regulated Power Supply Module visit GE Critical Power

IC 3-8 decoder 74138 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of ic 74138

Abstract: application of IC 74138 SOJ (small outline J-Lead) package, three 74FCT244A buffers, one 74-138 decoder and forty-two 0.1 , Mega-word by 32 bit static random access memory module in a 80 pin DIP (Dual In-Line Package) pressfit , technologies in SOJ pin format. Performance specifications and electrical characteristics are determined by the IC devices used. A typical memory component module will draw 12mW in standby and 2W during operation (TYP. for SONY L version IC). These items can vary according to the type and manufacturer of the
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pin diagram of ic 74138 application of IC 74138 IC 3-8 decoder 74138 pin diagram ic 74138 pin diagram AEPSD1M32

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 > 4-BIT SHIFT REGISTER 7495 * 8 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER 74138 9 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER 1/2 74139 10 8-LINE TO 3-LINE PRIORITY ENCODER 74148 11 , Note: Terminal capacities are average values and include package pin capacities and chip internal pad , ) b-68 b-75 b-81 (1) ^ 1 ! io PN! !a) ¿.J I (C) b-76 (11 b-69 Z2> (2) I IC , DECODER 7442 2 4-BIT MAGNITUDE COMPARATOR 7485 1 3 8-BIT SHIFT REGISTER 7491 * 4
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binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 MSM91H000

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 ral cells providing adequate interface with external circuitry. B A S IC C E L L The basic logic , - Effective 1.5 |i · Consum ption by gate : - Static 5 nA typ (AT OKRADS (Si) - Dynam ic 3 \i A/M , . 4. These inputs can be re-routed to any other I/O PAD. TMODE pin at logic HIGH enables the test mode func tion and then CKTEST pin configures it. CKTEST can also be used as a conventional input signal and , an exam ple the diagram of a DFFNR1, Macro cell (D Flip-Flop with Reset) as it appears to the routing
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full adder using ic 74138 circuit diagram for IC 7483 full adder ttl ic 7485 0850R 7483 4 bit binary full adder circuit diagram for 7483 transistor KD 617 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC for most requirements. Output drive may be increased from the basic 1mA to a maximum of 48mA per pin , 2 to 4 decoder 2 to 1 Mux 4 to 1 Mux 8 to 1 Mux SR latch with separate gate SR latch with common , r ty p ic a l p ro p a g a tio n d e la y s a re g e n e ra lly th e slo w est tim e s fo r a n y in , 2 to 4 decoder (outputs active high) 3 to 8 decoder (outputs active high) 3 to 8 decoder (outputs active low) 4 to 10 decoder (outputs active high) 4 to 1 multiplexer 16 to 1 gated multiplexer (74LS150
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74LS82 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 TC140G SC12D4 SC18D4 SC27D4 SC37D4 SC44D4

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 CARRIERS (LCC) C E R A M IC J -L E A D E D CHIP CARRIERS (JLCC) C E R A M IC PIN GRID ARR AY (PGA) PACKAGE , configured into any by-four multiple from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder , common logic Macros. FEATURES · · · · · · 1.4 ns g a te d e la y ty p ic a l. (2 -in p u t N A N D g a te ,F .O .= 2 ) S ta tic R A M or RO M on c h ip . S ilic o n -g a te 1.8 m ic ro n d ual m e ta l , s s -0 .5 -80 -40 -65 Ceramic T y p ic a l - M a x im u m 6.0 VDD + 0.5 VDD + 0.5 140 70 150
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pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 DN 74352 IC 74195 application of ic 74153 74171 MB65XXXX MB66XXXX MB67XXXX C4002

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC workstation workstation â'¢ Product idea diagram including IC Logic diagram layout Breadboard , 48mA per pin by means of parallel bond wires within the package. It should be remembered that an I/O , tristate buffer 3 1.01 D24L 2 to 4 decoder 5 0.67 MUX21H 2 to 1 Mux 4 0.80 MUX41 4 to 1 Mux 6 1.12 , multiplexed inputs 37 MR81 8 bit register with 2 bit multiplexed inputs 73 D24H 2 to 4 decoder (outputs active high) 6 D38H 3 to 8 decoder (outputs active high) 19 D38L 3 to 8 decoder (outputs active low) 19
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ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder Quad 2 input nand gate cd 4093

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram is depicted in Figure 1 wherein a simple three to eight decoder is fused into the array. The , generated at the input receivers. Hence, this diagram could be trimmed by six gates, down to eight to , whose inputs span the complete NAND gate foldback structure. 1 OF 8 DECODER/DEMULITPLEXER 8 , ); 8 EN Figure 1. Decoder Implementation in NAND Foldback Structure October 1993 27 , perform customized functions like a 5 to 27 decoder or a 14 to 4 encoder or, even an 18 to 7
Philips Semiconductors
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full 18*16 barrel shifter design TTL SN 7404 pn sequence generator using d flip flop 12 bit comparator images of pin configuration of IC 74138 8 bit barrel shifter PLHS501 AN049
Abstract: available in 155-lead Ceramic Pin Grid Array Package. The processor is ideally suited for real-time , important. © 1 9 8 7 ,1 9 8 8 ,1 9 8 9 , 1 9 9 0 , 1 9 9 1 L S I L o g ic C o rp o ra tio n . All rig h ts , Pin Grid Array) package The L64240 performs convolution/correlation operations of the type: L -1 , L64240 M ulti-Bit Filter (MFIR) Block Diagram WE 100 REGADR.O to REGAR.5 _ COEFF , . Pin Listing and Description Note: For all buses, SIGNALY.X denotes the Xth bit of SIGNALY. The -
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L64210/L64211 155-P MIL-STD-883C

images of pin configuration of IC 74138

Abstract: L64240 power HCMOS technology, the L64240 is available in 155-lead Ceramic Pin Grid Array Package. L64240 Chip , Ability to perform Sobel edge extraction Available in 155-lead CPGA (Ceramic Pin Grid Array) package , 2003 lsi logic L64240 M U Iti-Bit Fi Iter (MFIR) Block Diagram ci.o to O CI.7 REGAOR.O _to _ WE REGAR , ) lsi i a k;ic Architecture (Continued) Each of the 64 taps accepts two's complement or unsigned 8 , register length. Pin Listing and Description Note: For all buses, SI6NALY.X denotes the Xth bit of SIGNALY
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DI-74 L64240-15IWCCOM 74138 decoder 18 x 16 barrel shifter 4 bit barrel shifter circuit for left shift opera

AMD K6

Abstract: 74147 decimal to binary encoder easily BLOCK DIAGRAM g /E x u j u u u u u E I/O Blocks / + , Plastic Leaded Chip Carrier G = Pin Grid Array b. SPEED OPTION -50 (50 MHz toggle rate) -70 (70 MHz , TYPE Z = 84-pin PGA (Am3020) Z = 84-pin PGA (Am3030) Z = 132-pin PGA (Am3042)* Z = 132-pin PGA (Am3064)* Z = 175-pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED/POWER OPTION -50 = 50 MHz , interface between the deviceâ'™s external package pin and the internal user logic. Each IOB includes both
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AMD K6 74147 decimal to binary encoder C10BCPRD C10BCRD C10BPRD C10JCR C12JCR C16BARD

IC TTL 7432

Abstract: ic 74138 previously treated lightly. PLHS501 REVIEW The PLHS501 is a 52-Pin, bipolar programmable logic device , x4 X1, X3, X5, X7 x2 O0, O2 x2 x2 x2 Figure 1. PLHS501 Logic Diagram April 1989 , LATCHED D E tPD1 HOLD TIME NAND Gate Diagram OPERATING MODE 21 E tPD0 SETUP , Gate Diagram ns MIN 21 Timing Waveforms: CL G3 G4 G5 CLOCK WIDTH SETUP HOLD , the 74LS74. R ­>Q NAND Gate Diagram 4 (R) G3 G4 G2 G7 2 (D) 1 (C) 5 (Q
Philips Semiconductors
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IC TTL 7432 ic 74138 IC 7400 TTL S20 IC 7400 truth table 74521 comparator free 74ls74 pin configurations ODAT15

IC 3-8 decoder 74138 pin diagram

Abstract: f9444 with Single Clock up to 24 MHz LS TTL Input/Output Structure with l3L Internal Circuits 40-Pin DIP , Technology Comprehensive Family of Support Circuits Pin Functions CLK fOi M ULTIPROCESSOR I , perature Am bient Tem perature Under Bias Vcc Pin Potential to Ground Pin Input Voltage (dc) Input Current , . Timing and Status SYN, Pin 7 - Synchronize O utput - Active every cycle; may be used fo r external synchronization of memory and I/O control. STRBD, Pin 6 - Data Strobe - Active LOW output; active only d u ring
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f9444 74874 Fairchild 9445 74164 counter pin diagram of ic 74164 74164 with ic PIN DIAGRAM F9445 F9444 F9446 F9447 F9448 F9449

p54c

Abstract: SiS 85C503 shows the system block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC , Address Data Figure 1.1 System Block Diagram Preliminary V2.0 January 9, 1995 1 Silicon , Snoop Frequency · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 January 9, 1995 , Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M , # TURBO# OSC ACLK CLK PWRGD SiS85C501 Functional Block Diagram Preliminary V2.0 January 9, 1995
Silicon Integrated Systems
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p54c SiS 85C503 85c501 3-8 decoder 74138 pin diagram 3-8 decoder 74138 85c503 85C501/502/503 S85C501 S85C502 S85C503 85C502

A5 GNC mosfet

Abstract: SL1626 largest electronic publisher in the world. Contents Quick Guide to IC Master . 2 Part Number Index , has been expended to make IC MASTER accurate and complete, but IC MASTER cannot assume responsibility , may be reproduced without express written permission of the publishers. Copyright IC MASTER, 1977. IC , Corp., 643 Stewart Ave., Garden City, N.Y. 11530. TWX: 510-222-1673. @ IC MASTER 1977 1 1 II quick guide to your IC fflASTER APPLICATION To prepare this directory each IC NOTE manufacturer reviewed his
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A5 GNC mosfet SL1626 HA1452 ABB inverter motor fault code itt9012 TDA0470 AMI6800H AMI6800 VMI6800

IC 3-8 decoder 74138 pin diagram

Abstract: F9444 24 MHz â'¢ LS TTL Input/Output Structure with l3L Internal Circuits â'¢ 40-Pin DIP Needing a Single , Pin Functions MULTIPROCESSOR SIGNALS EXTERNAL REQUESTS bus i CONTROL) CLK _F9445 MR 16 , -65to+150°C Ambient Temperature Under Bias -55 to + 125°C Vcc Pin Potential to Ground Pin -0.5 to +6.0 V , |JU1-nunvc cvciy ojoic, may be used for external synchronization of memory and I/O control. STRBD, Pin 6 â , ; STRBA, Pin 5 â'" Strobe Memory Address Register â'" Active LOW output; active only during normal memory
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MSI IC 74138 decoder power control F9444 F9445 self-test 74138 FAIRCHILD 74ls240 bus transfer switch F9445-16DM F9470 M38510 F9445-24 F9445-20 F9445-16

HP5082-7760

Abstract: hp 4514 opto allowances for CTR degradation. Chapter 4 covers the theory and applica tions of high-speed PIN photodiodes , . 1-2 Materials Available for L E D D e v ic e s , .1.3 Quantum Efficiency of L E D D e v ic e s . 1.3 Relative E f f ic ie n c y , .jj Relative E f f ic ie n c y
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HP5082-7760 hp 4514 opto led 7 segment anode TIL 702 HP 2231 opto coupler uaa170 seven segment to BCD converter LM 7447 IC

d6406

Abstract: laser sharp measurement CIRCUITS DIVISION (CICD) C IC D is dedicated to the development and production of custom/semi-custom and , communications. C IC D employs high performance CM O S and bipolar technologies to meet the needs of high-end major military and hi-reliability programs. C IC D is oriented to engineering and manufacturing to , circuits that meet a variety of Department of Defense environmental specifications. (See complete C IC D , . C IC D Rad Hard Pro d u cts
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d6406 laser sharp measurement Transistor AF 138 pin diagram AMD FX 9590 80C86/88 AA22846 J22912 K29793 NZ21084 RS39191

induction cooker fault finding diagrams

Abstract: compressor catalogue controls using the TDA1023 763 NE587 NE589 NE594 SA594 LED decoder/driver LED decoder/driver , LED decoder/drivers: using the NE587 and NE589 809 ICM7555 NE555 NE556 NE556 1 NE558 SA555 , SE5570 servo am plifier programmable seven-channel RC encoder seven channel RC decoder brushless DC , encoder applications using the NE5045 decoder applications using the NE544 servo amplifier NE5570: a , generator tone/frequency decoder PLL phase-locked loop; up to 150 MHz call progress decoder phase-locked
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induction cooker fault finding diagrams compressor catalogue Vernitron TRANSDUCER b2 SPICE model NTC Inrush Current Limiters Thermistor str 1265 smps power supply circuit of tv XR558CP

f9454

Abstract: F9445 perations A p p lica tio n s In stru ctio n Execution Times Tim ing Diagram s and S p e cifica tio n s O rdering Inform ation Page 1 2 2 4 5 15 19 30 31 36 Pin Functions C LK _ F 9445 HR 16-B IT M IC R O P , address reg ister, data b u ffer and address decoder are required fo r any memory, static o r dynam ic , Fairchild's Isoplanar Integrated Inje ctio n'L o g ic (l3La ) technology. This bipolar technology and a , Under Bias Vcc Pin Potential to Ground Pin Input Voltage (dc) Input Current (dc) ' O utput Voltage
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f9454 74l93 9347S F9454

smi 5502

Abstract: T54B block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC DRAM 244 , * * * 245 ISA BUS Address Data Figure 1.1 System Block Diagram Preliminary V2.0 April 2, 1995 , Buffer Strength · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 April 2, 1995 , Functional Block Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA , # SIOREQ# SIOGNT# KBRST#/BREAK# TURBO# OSC ACLK CLK PWRGD SiS5501 Functional Block Diagram
Silicon Integrated Systems
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smi 5502 T54B ha 501 9ROM pin diagram priority decoder 74138 73 5503 S5501 S5502 S5503
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