IBM11S1320NL1M IBM11S1320NN1M IBM11S4325BP IBM11S4325BM IBM11S4325BP/M 50H4745 - Datasheet Archive

 

IBM11S4325BP IBM11S4325BM 4M x 32 SO DIMM Module Features · 72-Pin Small Outline Dual-In-Line Memory Module ·

 

IBM11S1320NL1M IBM11S1320NL1M x 3212/8, 5.0V, Au. IBM11S1320NN1M IBM11S1320NN1M x 3212/8, 3.3V, Au. IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Features · 72-Pin Small Outline Dual-In-Line Memory Module · Performance: -60 -70 tRAC RAS Access Time 60ns 70ns tCAC CAS Access Time 15ns 20ns tAA Access Time From Address 30ns 35ns tRC Cycle Time 104ns 124ns tHPC EDO Mode Cycle Time 25ns 30ns · High Performance CMOS process · Manufactured with 16Mb DRAMS (4M x 4) · Single 3.3V ± 0.3V or 5.0V ± 0.5V Power Supply · Optimized for use in byte-write non-parity applications. · Low active current consumption · All inputs & outputs are LVTTL(3.3V) or TTL(5V) compatible · Extended Data Out (EDO) access cycle · Refresh Modes: RAS-Only, CBR, Hidden Refresh and Self Refresh · 2048 refresh cycles distributed across 128ms · 11/11 Addressing (Row/Column) · Au contacts Description The IBM11S4325BP/M IBM11S4325BP/M are 4MB industry standard 72-pin 4-byte small outline dual in-line memory modules (SO DIMMs). The modules are organized as 4Mx32 high speed memory arrays that are intended for use in 16, 32 and 64 bit applications. They are manufactured with eight 4Mx4 TSOP devices, each in a 300mil package. The use of EDO DRAMs allows for a reduction in Page Mode cycle time from 40ns (Fast Page) to 25ns (EDO, 60ns sort). The use of TSOP packages allows tight DIMM spacing (.3" on center). This assembly is intended for use in space constrained and/or low power applications. The IBM 72-Pin SO DIMMs provide a high performance, flexible 4-byte interface in a 2.35" long footprint. Card Outline Detail A See Detail A for 5.0V version 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 (Front) 1 (Back) 2 71 72 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Pin Description RAS0, RAS2 Row Address Strobe CAS0 - CAS3 Column Address Strobe WE DQ0-7, 9-16, 18-25, 27-34 Pin# Name Pin# Name Pin# Name Pin# Name Pin# Name Pin# Name 1 VSS 13 A1 25 DQ13 37 DQ18 49 DQ20 61 VCC 2 DQ0 14 A2 26 DQ14 38 DQ19 50 DQ21 62 DQ32 3 Read/write Input A0 - A10 Pinout DQ1 15 A3 27 DQ15 39 VSS 51 DQ22 63 DQ33 4 DQ2 16 A4 28 A7 40 CAS0 52 DQ23 64 DQ34 Address Inputs Data Input/output VCC Power (+3.3V or +5.0V) 5 DQ3 17 A5 29 NC 41 CAS2 53 DQ24 65 NC VSS Ground 6 DQ4 18 A6 30 VCC 42 CAS3 54 DQ25 66 PD2 NC No Connect 7 DQ5 19 A10 31 A8 43 CAS1 55 NC 67 PD3 8 DQ6 20 NC 32 A9 44 RAS0 56 DQ27 68 PD4 9 DQ7 21 DQ9 33 NC 45 NC 57 DQ28 69 PD5 10 VCC 22 DQ10 34 RAS2 46 NC 58 DQ29 70 PD6 11 PD1 23 DQ11 35 DQ16 47 WE 59 DQ31 71 PD7 12 A0 24 DQ12 36 NC 48 NC 60 DQ30 72 VSS PD1 - PD7 Presence Detects Ordering Information Part Number Organization Speed Dimensions Power IBM11S4325BP-60T IBM11S4325BP-60T 4M x 32 60ns 2.35" x 1" x .1496" 3.3V IBM11S4325BP-70T IBM11S4325BP-70T 4M x 32 70ns 2.35" x 1" x .1496" 3.3V IBM11S4325BM-60T IBM11S4325BM-60T 4M x 32 60ns 2.35" x 1" x .1496" 5.0V IBM11S4325BM-70T IBM11S4325BM-70T 4M x 32 70ns 2.35" x 1" x .1496" 5.0V ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Block Diagram DQ0 DQ7 DQ1-4 WE CAS0 RAS0 DQ9 DQ16 DQ1-4 DQ1-4 WE CAS U1 DQ1-4 WE WE CAS U2 WE CAS U3 CAS RAS RAS RAS OE OE OE U4 RAS OE A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 11 11 CAS1 DQ18 DQ25 DQ1-4 U5 DQ1-4 WE WE CAS DQ34 DQ1-4 DQ1-4 WE CAS2 RAS2 DQ27 CAS U6 WE CAS U7 CAS RAS RAS RAS OE OE OE U8 RAS OE A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 11 A0-A10 A0-A10 11 CAS3 A0-A10 A0-A10 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Truth Table RAS CAS WE Row Address Column Address All DQ bits Standby H HX X X X High Impedance Read L L H Row Col Valid Data Out Early-Write L L L Row Col Valid Data In EDO Mode - Read: 1st Cycle L HL H Row Col Valid Data Out Subsequent Cycles L HL H N/A Col Valid Data Out EDO Mode - Write: 1st Cycle L HL L Row Col Valid Data In Subsequent Cycles L HL HL N/A Col Valid Data In Function RAS-Only Refresh L H X Row N/A High Impedance HL L H X N/A High Impedance Read LHL L H Row Col Data Out Write LHL L L Row Col Data In HL L H X X High Impedance CAS-Before-RAS Refresh Hidden Refresh Self Refresh Presence Detect Pin -60 -70 PD1 NC NC PD2 VSS VSS PD3 VSS VSS PD4 NC NC PD5 NC VSS PD6 NC NC PD7 VSS VSS 1. NC= OPEN, Vss = GND ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Absolute Maximum Ratings Rating Symbol Parameter Units 3.3 Volt -0.5 to + 4.6 -1.0 to + 7.0 Notes V 5.0 Volt 1 VCC Power Supply Voltage VIN Input Voltage -0.5 to min (VCC + 0.5, 4.6) -0.5 to min (VCC + 0.5, 7.0) V 1 VOUT Output Voltage -0.5 to min (VCC + 0.5, 4.6) -0.5 to min (VCC + 0.5, 7.0) V 1 TOPR Operating Temperature TSTG Storage Temperature °C 1 -55 to +150 -55 to +150 °C 1 3.6 5.5 W 1 Short Circuit Output Current IOUT 0 to +70 Power Dissipation PD 0 to +70 50 50 mA 1 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions Symbol (TA = 0 to 70°C) 3.3 Volt Parameter 5.0 Volt Min Typ Max Min Typ Max Units Notes VCC Supply Voltage 3.0 3.3 3.6 4.5 5.0 5.5 V 1 VIH Input High Voltage 2.0 - VCC + 0.5 2.4 - VCC + 0.5 V 1, 2 VIL Input Low Voltage -0.5 - 0.8 -0.5 - 0.8 V 1, 2 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 1.2V for pulse widths of 4.0ns with 3.3 Volt, or VCC + 2.0V for pulse widths of 4.0ns (or VCC + 1.0V for 8.0ns) with 5.0 Volt. Additionally, VIL may undershoot to -2.0V for pulse widths 4.0ns (or -1.0V for 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA = 0 to +70°C, VCC = 3.3V ± 0.3V or 5.0V ± 0.5V) Symbol Max Units Input Capacitance (A0-A10 A0-A10) 53 pF CI2 Input Capacitance (RAS) 40 pF CI3 Input Capacitance (CAS) 23 pF CI4 Input Capacitance (WE) 67 pF CI/O Output Capacitance (DQ0-DQ34 DQ0-DQ34) 15 pF CI1 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 Parameter ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module DC Electrical Characteristics (TA = 0 to +70°C, VCC = 3.3 0.3V or 5.0 0.5V) 3.3 Volt Symbol Parameter 5.0 Volt ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) Max Min - 1000 - - 880 - 880 - 8 - 8 1, 2, 3 1000 -70 Notes Max -60 Units mA Min ICC2 Standby Current (TTL) Power Supply Standby Current (RAS = CAS VIH) RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS VIH: tRC = tRC min) -60 - 1000 - 1000 ICC3 -70 - 880 - 880 EDO Mode Current Average Power Supply Current, EDO Mode (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) -60 - 920 - 920 -70 - 800 - 800 - 1600 - 1600 ICC4 mA mA mA ICC5 Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) CAS Before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) -60 - 1000 - -70 - 880 - 880 Self Refresh Current Average Power Supply Current during Self Refresh CBR cycle with RAS tRASS (min); CAS held low; WE = VCC - 0.2V; Addresses and DIN = VCC - 0.2V or 0.2V. -60 - 1600 - 2400 -70 - 1600 - 2400 RAS -40 +40 -40 +40 CAS -20 +20 -20 +20 All others -80 +80 -80 1, 2, 3 1000 ICC6 1, 3 +80 ICC7 II(L) Input Leakage Current Input Leakage Current, any input (0.0 VIN (VCC + 0.3v) All Other Pins Not Under Test = 0V µA mA 1, 3 µA µA IO(L) Output Leakage Current (DOUT is disabled, 0.0 VOUT VCC) -10 +10 -10 +10 µA VOH Output High Level Output "H" Level Voltage (IOUT = -2.5mA for 3.3V, or IOUT = -5mA for 5.0V) 2.4 VCC 2.4 VCC V VOL Output Low Level Output "L" Level Voltage (IOUT = +2.1mA for 3.3V, or IOUT = +4.2mA for 5.0V) 0.0 0.4 0.0 0.4 V 1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 2. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module AC Characteristics (TA = 0 to +70°C, VCC = 3.3V 0.3V or 5.0V 0.5V) 1. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required. 2. AC measurements assume tT=2ns. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 4. When both CAS0 & CAS1 or CAS2 & CAS3 go low at the same time, all 16 bits of data are read/written into the device. CAS0 & CAS1 or CAS2 & CAS3 (CAS'S to the same DRAM) cannot be staggered within the same read/write cycle. Read, Write, and Refresh Cycles (Common Parameters) -60 Symbol -70 Parameter Units Min Max Min Notes Max tRC Random Read or Write Cycle Time 104 - 124 - ns tRP RAS Precharge Time 40 - 50 - ns tCP CAS Precharge Time 10 - 10 - ns tRAS RAS Pulse Width 60 10K 70 10K ns tCAS CAS Pulse Width 10 10K 12 10K ns tASR Row Address Setup Time 0 - 0 - ns tRAH Row Address Hold Time 10 - 10 - ns tASC Column Address Setup Time 0 - 0 - ns tCAH Column Address Hold Time 10 - 12 - ns tRCD RAS to CAS Delay Time 14 45 14 50 ns 1 tRAD RAS to Column Address Delay Time 12 30 12 35 ns 2 tRSH RAS Hold Time 10 - 12 - ns tCSH CAS Hold Time 50 - 55 - ns tCRP CAS to RAS Precharge Time 5 - 5 - ns tDZC CAS Delay Time from DIN 0 - 0 - ns Transition Time (Rise and Fall) 2 30 2 30 ns tT 3 1. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: if tRCD is greater than the specified tRCD (max) limit, then access time is controlled by tCAC. 2. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 3. AC measurements assume tT = 2ns. 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Write Cycle -60 Symbol -70 Parameter Units Min Max Min Notes Max tWCS Write Command Set Up Time 0 - 0 - ns tWCH Write Command Hold Time 10 - 12 - ns tWP Write Command Pulse Width 10 - 12 - ns tRWL Write Command to RAS Lead Time 10 - 12 - ns tCWL Write Command to CAS Lead Time 10 - 12 - ns tDS DIN Setup Time 0 - 0 - ns 1 tDH DIN Hold Time 10 - 12 - ns 1 Units Notes 1. This timing parameter is not applicable to this product, but applies to a related product in this family. Read Cycle Symbol Parameter -60 -70 Min Max Min Max tRAC Access Time from RAS - 60 - 70 ns 1, 2 tCAC Access Time from CAS - 15 - 20 ns 1, 2 tAA Access Time from Address - 30 - 35 ns 1, 2 tRCS Read Command Setup Time 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - ns 3 tRRH Read Command Hold Time to RAS 0 - 0 - ns 3 tRAL Column Address to RAS Lead Time 30 - 35 - ns tCLZ CAS to Output in Low-Z 0 - 0 - ns tCDD CAS to DIN Delay Time 15 - 20 - ns tOFF Output Buffer Turn-off Delay - 15 - 20 ns 1. 2. 3. 4. 4 Measured with the specified current load and 100pF. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA. Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Extended Data Out Cycle Symbol -60 Parameter -70 Min. Max. Min. Max. Units tHCAS CAS Pulse Width (EDO Mode) 10 10K 12 10K ns tHPC EDO Mode Cycle Time (Read/Write) 25 - 30 - Notes ns tDOH Data-out Hold Time from CAS 5 - 5 - ns tWHZ Output buffer Turn-Off Delay from WE 0 10 0 15 ns tWPZ WE Pulse Width to Output Disable at CAS High 10 - 10 - ns tCPRH RAS Hold Time from CAS Precharge 35 - 40 - ns tCPA Access Time from CAS Precharge - 35 - 40 ns tRASP EDO Mode RAS Pulse Width 60 125K 70 125K ns 1 1. Measured with the specified current load and 100pFat VOL = 0.8V and VOH = 2.0V. Refresh Cycle Symbol Parameter -60 -70 Min Max Min Max Units tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 5 - 5 - ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tWRH WE Hold Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - ns tREF Refresh Period - 128 - 128 ms Notes 1 1. 2048 refreshes are required every 128ms. 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Self Refresh Cycle Symbol Parameter -60 -70 Min. Max. Min. Max. Units Notes tRASS RAS Pulse Width During Self Refresh Cycle 100 - 100 - µs 1 tRPS RAS Precharge Time During Self Refresh Cycle 104 - 124 - ns 1 tCHS CAS Hold Time During Self Refresh Cycle -50 - -50 - ns 1, 2 tCHD CAS Hold Time From RAS Falling During Self Refresh Cycle 350 - 350 - µs 1, 2 1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed in a EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 2. If tRASS > tCHD (min) then tCHD applies. If tRASS tCHD (min) then tCHS applies. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Read tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH VIH UCAS LCAS VIL tCRP tCAS tRAD tRAL tASR tCAL tAR tRAH tASC tCAH VIH Address VIL Row Column tWRP tWRH tRCH tRRH tRCS VIH NOTE 1 WE VIL tAA tDZC tCDD VIH DIN Hi-Z VIL tCAC tOFF tCLZ VOH DOUT Hi-Z VOL Valid Data Out Hi-Z tRAC : "H" or "L" 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH V UCAS IH LCAS V IL tCRP tCAS tRAD tASR tRAH tAR tASC tCAH VIH Address VIL Row Column tWRP tWRH tWCS VIH WE VIL tWCH tWP NOTE 1 tWCR tDHR tDS tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : "H" or "L" NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Extended Data Out Mode Read Cycle tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tHCAS VIH tRSH tHCAS UCAS LCAS VIL tCAL tCSH tASR Address tRAH tAR tASC tRAL tCAH tASC tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tRCH tRRH tWRP tWRH tRCS VIH WE VIL NOTE 1 tCAC tCAC tCPA tCPA tDOH tCAC tOFF tAA tAA tRAC tAA tWP tDOH tCLZ DOUT VOH VOL Hi-Z : "H" or "L" 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 Data Out 1 Data Out 2 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Extended Data Out Mode Read Cycle (WE Control) tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tRSH tHCAS tHCAS UCAS VIH LCAS VIL tCAL tCSH tASR Address tRAH tAR tRAL tASC tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 tRCH tWRP tWRH tRCS tRCH tRRH tCAC tRCS tRCH tOFF tRCS tWPZ VIH VIL Column N tAA tAA tRAD WE tASC tWPZ NOTE 1 tCAC tCPA tRAC tAA tCAC tWHZ tCPA tWHZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" Data Out 1 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 22 Data Out 2 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Extended Data Out Mode Write Cycle tRP tRASP VIH RAS VIL tCRP tHPC tRCD tCP tCP tHCAS UCAS VIH LCAS VIL tHCAS tRSH tHCAS tRAD tCSH tASR Address tRAH tAR tASC tCAH tASC tCAH tASC tCAH VIH Row VIL Column 1 Column 2 Column N tCWL tWCR tWCS VIH WE VIL tRWL tWCH tWRP tWRH tWCS tWP tWCH tWCS tWP tWCH tWP NOTE 1 tDHR tDS DIN tDH tDS tDH tDS tDH VIH Data In 1 VIL : "H" or "L" 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 Data In 2 Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRCD tRSH tCRP tCHR UCAS VIH LCAS VIL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE VIL tAA tDZC tCDD VIH DIN Hi-Z VIL tCAC tOFF tCLZ VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : "H" or "L" ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 22 tOH tOHO 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP UCAS VIH LCAS VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL t DS tDH VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : "H" or "L" 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Self Refresh Cycle (Sleep Mode) tRASS tRPS VIH RAS VIL tRPC tCSR tCHS tCP tCRP UCAS VIH LCAS V IL tWRH tWRP VIH WE VIL tOFF DOUT VOH Hi-Z VOL : "H" or "L" NOTE: Address is "H" or "L" Once tRASS (min) is provided and RAS remains low, the DRAM will be in Self Refresh, commonly known as "Sleep Mode." ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP UCAS VIH LCAS VIL tASR tRAH VIH Address Row VIL VOH Hi-Z DOUT VOL : "H" or "L" Note: WE, DIN are "H" or "L" 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module CAS Before RAS Refresh Cycle t RC tRAS tRP VIH RAS VIL t RPC tCSR t UCAS LCAS tRPC CP tCRP tCHR VIH VIL tWRH tWRP VIH WE VIL tCDD DIN VIH Hi-Z VIL tOFF DOUT VOH Hi-Z VOL : "H" or "L" Note: Addresses are "H" or "L" ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Layout Drawing 59.69 2.35 2.00 MIN .0787 51.66 2.034 5.00 .197 25.4 1.00 4.00 .157 Front 2.00 .0787 1.80 .0709 A 17.78 .700 (2X) 0 3.1877 .1255 1.27 PITCH .050 1.00 WIDTH .039 44.45 1.750 REF. 3.3V A= 3.175 .125 5.0V 6.35 .246 Side 3.80 5.01 .197 MIN. .1496 MAX. _ 1.00 + 0.10 _ .039 + .0039 Note: All dimensions are typical unless otherwise stated. 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 Millimeters Inches ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 22 IBM11S4325BP IBM11S4325BP IBM11S4325BM IBM11S4325BM 4M x 32 SO DIMM Module Revision Log Rev Contents of Modification 8/95 Initial release of 4Mx32 EDO specification using 4Mx4 with 11/11 Addressed DRAMs. 4/96 Correct typo's ©IBM Corporation, 1996. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 22 50H4745 50H4745 SA14-4458-01 SA14-4458-01 Released 4/96 ® © International Business Machines Corp.1996 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com