IBM11M1720B1M QC10/10 IBM11M1720B 50H4346 SA14-4606-02 IBM11M1720B-60 - Datasheet Archive

 

IBM11M1720B 1M x 72 DRAM MODULE Features · Optimized for byte-write parity applications · 168 Pin JEDEC Standard, 8

 

IBM11M1720B1M IBM11M1720B1M x 72 QC10/10 QC10/10, 5.0V, AuMMDL20DSU-001015627. IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Features · Optimized for byte-write parity applications · 168 Pin JEDEC Standard, 8 Byte Dual In-line Memory Module · System Performance Benefits: - · 1Mx72 Fast Page Mode DIMM · Performance: Buffered inputs (except RAS, Data) Reduced noise (32 VSS/VCC pins) 4 Byte Interleave Enabled Byte write, byte read accesses Buffered PDs -60 -70 RAS Access Time 60ns 70ns CAS Access Time 20ns 25ns · Fast Page Mode, Read-Modify-Write Cycles tAA Access Time From Address 35ns 40ns tRC Cycle Time 110ns 130ns · Refresh Modes: RAS-Only, CBR and Hidden Refresh tPC Fast Page Mode Cycle Time 40ns 45ns tRAC tCAC · 1024 refresh cycles distributed across 16ms · All inputs and outputs are fully TTL compatible · 10/10 addressing (Row/Column) · Single 5V, ± 0.5V Power Supply · Card size: 5.25" x 1.0" x 0.354" · Au contacts · DRAMS in SOJ Package Description IBM11M1720B IBM11M1720B is an industry standard 168-pin 8-byte Dual In-line Memory Module (DIMM) which is organized as a 1Mx72 high speed memory array for parity applications. The DIMM uses 16 1Mx4 DRAMs and 2 1Mx4 Quad CAS DRAMs in SOJ packages. Improved system performance is provided by the on-DIMM buffering of selected input signals. The specified timings include all buffer, net and skew delays, which simplifies the memory subsystem design analysis. The data and RAS signals are not buffered, which preserves the DRAM access specifications of 60ns and 70ns. Presence Detect (PD) and Identification Detect (ID) bits provide information about the DIMM density, addressing, performance and features. PD bits can be dotted at the system level and activated for each DIMM position using the PD enable (PDE) signal. ID bits also allow detection of card features, and may be dot-or'd at the system level to provide information for the entire DIMM bank. For example, if a x64 or x72 (ECC) DIMM were inserted into a bank of x72 parity DIMMs, IDO (grounded) would indicate that at least one DIMM in that memory bank will not function properly. PD8 would indicate what positions, if any, contained an ECC DIMM. All IBM 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 5.25" long space-saving footprint. Related products are the x64 non-parity (5V) and ECC DIMMs (5V and 3.3V). Card Outline (Front) (Back) 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 1 85 10 11 94 95 40 41 124 125 84 168 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Pin Description Pinout RAS0, RAS2 Row Address Strobe CAS0 - CAS7 Column Address Strobe (Buffered) WE0, WE2 Output Enable (Buffered) A0, B0, A1 - A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Read/write Input (Buffered) OE0, OE2 Pin# Address Inputs (Buffered) DQx Data Input/Output PQx Parity Input/Output VCC Power (+5V) VSS Ground NC PD1 - PD8 PDE ID0 - ID1 No Connect Presence Detects (Buffered) Presence Detect Enable ID Bits Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 PQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 PQ17 VSS NC NC VCC WE0 CAS0 CAS2 RAS0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC NC NC Pin# 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Back Side VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 PQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 PQ53 VSS NC NC VCC NC CAS1 CAS3 NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC B0 Pin# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front Side VSS OE2 RAS2 CAS4 CAS6 WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 PQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 PQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC Pin# Back Side VSS NC NC CAS5 CAS7 PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ60 NC NC NC NC DQ61 PQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 PQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC Note: All pin assignments are consistent for all 8 Byte versions. Ordering Information Part Number Organization IBM11M1720B-60 IBM11M1720B-60 Speed Addr. Leads Dimension 10/10 Au Notes 5.25"x1.0"x 0.354" 60ns IBM11M1720B-70 IBM11M1720B-70 70ns 1Mx72 IBM11M1720B-60J IBM11M1720B-60J 60ns 1 IBM11M1720B-70J IBM11M1720B-70J 70ns 1 1. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev G. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Block Diagram OE0 WE0 CAS0 OE2 WE2 RAS0 CAS4 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ0 DQ1 DQ2 DQ3 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ4 DQ5 DQ6 DQ7 CAS RAS PQ8 I/O 0 WE OE WE DQ9 DQ10 DQ11 DQ12 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ13 DQ14 DQ15 DQ16 CAS RAS PQ17 I/O 0 WE OE WE OE WE OE D9 D17 (1/4) WE RAS CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS CAS RAS PQ53 I/O 0 OE D3 WE CAS I/O 0 I/O 1 I/O 2 I/O 3 DQ49 DQ50 DQ51 DQ52 D2 OE D16 (2/4) WE OE WE OE WE OE D10 D11 D17 (2/4) CAS6 RAS DQ18 DQ19 DQ20 DQ21 CAS I/O 0 I/O 1 I/O 2 I/O 3 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ22 DQ23 DQ24 DQ25 CAS RAS I/O 0 WE OE WE CAS RAS OE D5 WE CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ58 DQ59 DQ60 DQ61 D4 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ54 DQ55 DQ56 DQ57 OE D16 (3/4) PQ62 CAS3 I/O 0 WE OE WE OE WE OE D12 D13 D17 (3/4) CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS OE DQ63 DQ64 DQ65 DQ66 D6 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS RAS I/O 0 WE WE OE WE D16 (4/4) OE PQ71 OE A1 - AN A1 - AN: DRAMS D0 - D17 A0: DRAMS D0-D7, D16 B0 WE A0: DRAMS D8-D15 D8-D15, D17 D14 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS RAS I/O 0 PD 1 - 8 (when =0, 1=NC) A0 RAS CAS DQ67 DQ68 DQ69 DQ70 D7 CAS I/O 0 I/O 1 I/O 2 I/O 3 VSS PDE CAS7 CAS 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 OE D8 DQ45 DQ46 DQ47 DQ48 CAS2 PQ35 WE CAS5 RAS DQ31 DQ32 DQ33 DQ34 RAS I/O 0 OE D16 (1/4) CAS I/O 0 I/O 1 I/O 2 I/O 3 DQ27 DQ28 DQ29 DQ30 CAS PQ44 OE D1 WE CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ40 DQ41 DQ42 DQ43 D0 CAS I/O 0 I/O 1 I/O 2 I/O 3 RAS DQ36 DQ37 DQ38 DQ39 CAS1 PQ26 RAS2 WE OE VCC WE D0 - D17, Buffers VSS D15 D0 - D17, Buffers OE D17 (4/4) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Truth Table Function RAS CAS WE OE Row Address Column Address PDE DQx Standby H HX X X X X X High Impedance Read L L H L Row Col X Valid Data Out Early-Write L L L X Row Col X Valid Data In Late-Write / RMW L L HL LH Row Col X Valid Data Out, Valid Data In Fast Page Mode - Read 1st Cycle L HL H L Row Col X Valid Data Out Subsequent Cycles L HL H L N/A Col X Valid Data Out Fast Page Mode - Write 1st Cycle L HL L X Row Col X Valid Data In Subsequent Cycles L HL L X N/A Col X Valid Data In Fast Page Mode - RMW 1st Cycle L HL HL LH Row Col X Valid Data Out, Valid Data In Subsequent Cycles L HL HL LH N/A Col X Valid Data Out, Valid Data In RAS-Only Refresh L H X X Row N/A X High Impedance HL L H X X X X High Impedance Read LHL L H L Row Col X Data Out Write LHL L H X Row Col X Data In X X X X X X L Not Affected (PD Bits Valid) CAS-Before-RAS Refresh Hidden Refresh Read Presence Detects Presence Detect Pin -60 -70 PD1 (PD1 - PD4: Addressing/Density) 0 0 PD2 0 0 PD3 1 1 PD4 0 0 PD5 (EDO Detection) 0 0 PD6 (PD6 - PD7: Speed) 1 0 PD7 1 1 PD8 (Parity/ECC Designator) 1 1 ID0 (DIMM Type/Width) 1 1 ID1 (Refresh Mode) 0 0 1. PD1-8 are buffered outputs (0 = driven to VOL, 1 = open) 2. ID0-1 are unbuffered outputs (0 = VSS, 1 = open) 3. PDE should be tied high or low at system level if not used ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Absolute Maximum Ratings Symbol Parameter Rating Units Notes -1.0 to 6.0 V 1 VCC Power Supply Voltage VIN Input Voltage -0.5 to min (VCC +0.5, 6.0) V 1 VOUT Output Voltage -0.5 to min (VCC +0.5, 6.0) V 1 TOPR Operating Temperature 0 to +70 °C 1 TSTG Storage Temperature -55 to +125 °C 1 PD Power Dissipation 8.6 W 1 IOUT Short Circuit Output Current 50 mA 1 Short Circuit Output Current (PD) 60 mA 1 IOUTPD 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating condition for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0 to 70°C) Symbol Parameter Min Typ Max Units Notes VCC Supply Voltage 4.5 5.0 5.5 V 1 VIH Input High Voltage 2.4 - VCC +0.5 V 1, 2 VIL Input Low Voltage -0.5 - 0.8 V 1, 2 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 2.0V for pulse widths of 4.0ns (or VCC + 1.0V for 8.0ns). Additionally, VIL may undershoot to -2.0V for pulse widths 4.0ns (or -1.0V for 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA = 0 to +70°C, VCC = 5.0V ± 0.5V) Symbol Max Units CI1 Input Capacitance (A0, B0, A1-A9) 13 pF CI2 Input Capacitance (RAS) 70 pF CI3 Input Capacitance (CAS, WE, OE) 13 pF CI4 Input Capacitance (PDE) 18 pF CIO1 Input/Output Capacitance (DQX) 15 pF CIO2 Input/Output Capacitance (PQX) 15 pF CO1 Output Capacitance (PD) 15 pF CO2 Output Capacitance (ID) 5 pF 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 Parameter ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE DC Electrical Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V) Symbol ICC1 Parameter Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) Min Max -60 - 1560 -70 - 1290 - 37 Standby Current (TTL) Power Supply Standby Current (RAS = CAS VIH) RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS VIH: tRC = tRC min) -60 - -70 - 1290 Fast Page Mode Current Average Power Supply Current, Fast Page Mode (RAS VIL, CAS, Address Cycling: tPC = tPC min) -60 - 1100 -70 - 1080 - 18 -60 - 1560 -70 - 1290 All but RAS -10 +10 RAS -90 1,2,3 1560 ICC3 Notes mA ICC2 Units +90 ICC4 ICC5 CAS before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) mA II(L) Input Leakage Current Input Leakage Current, any Input (0.0 VIN (VCC < 6.0V), All Other Pins Not Under Test = 0V 1,3 mA Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) ICC6 mA 1,2,3 mA mA 1,3 µA IO(L) Output Leakage Current (DOUT is disabled, 0.0 VOUT VCC) -10 +10 µA VOH Output High Level Output "H" Level Voltage (IOUT = -5mA @ 2.4V) 2.4 - V VOL Output Low level Output "L" Level Voltage (IOUT = +4.2mA @ 0.4V) - 0.4 V 1. ICC1,ICC3,ICC4 and ICC6 depend on cycle rate. 2. ICC1,ICC4 depend on output loading. Specified values are obtained with output open. 3. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE AC Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V) 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required. The 1Mx4 DRAM outputs will remain disabled until these 8 cycles have occurred. This prevents data contention (excessive current) during power on. To prevent excess power dissipation during power-up, RAS should rise coincident with the power supply voltage. 3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAM access specifications of 60ns and 70ns. 4. AC measurements assume tT = 5ns. . Read, Write, Read-Modify-Write and Refresh Cycles Symbol Parameter (Common Parameters) -60 -70 Min Max Min Max Unit tRC Random Read or Write Cycle Time 110 - 130 - ns tRP RAS Precharge Time 40 - 50 - ns tCP CAS Precharge Time 10 - 10 - ns tRAS RAS Pulse Width 60 10K 70 10K ns tCAS CAS Pulse Width 15 100K 20 100K ns Notes tASR Row Address Setup Time 5 - 5 - Row Address Hold Time 8 - 8 - ns - 2 - 2 ns tRAH 1 ns ns tASC Column Address Setup Time 2 tCAH Column Address Hold Time 10 - 10 - tRCD RAS to CAS Delay Time 18 40 18 45 ns 3 tRAD RAS to Column Address Delay Time 13 25 13 30 ns 4 tRSH RAS Hold Time 20 - 25 - ns tCSH CAS Hold Time 58 - 68 - ns tCRP CAS to RAS Precharge Time 10 - 10 - ns tODD OE to DIN Delay Time 20 - 25 - ns 5 tDZO OE Delay Time from DIN -2 - -2 - ns 6 tDZC CAS Delay Time from DIN -2 - -2 - ns 6 tAR Column Address Hold Time Referenced to RAS 57 - 62 - - Hold Time CAS Low to CAS High 10 - 10 - ns Transition Time (Rise and Fall) 3 50 3 50 ns tCLCH tT 7 1. Last rising CASx edge to first falling CASx edge. 2. The minimum tCAS requires tCSH to be met for both writes and reads. Also, because of the buffer, the minimum tCAS for a read cycle must be extended to guarantee the data out window (tOH) in the application. For example, a tCAS of 15ns plus a minimum tOH of 2ns would result in turning data out of the DIMM at 17ns (3ns before max tCAC of 20ns). 3. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD is greater than the specified tRCD(max) limit, then access time is controlled by tCAC. 4. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 5. Either tCDD or tODD must be satisfied. 6. Either tDZC or tDZO must be satisfied. 7. Last falling CASx edge to first rising CASx edge. 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Write Cycle Symbol Parameter -60 Min -70 Max Min Max Unit Notes 1 tWCS Write Command Set Up Time 2 - 2 - ns tWCH Write Command Hold Time 17 - 17 - ns tWP Write Command Pulse Width 15 - 15 - ns tRWL Write Command to RAS Lead Time 20 - 25 - ns tCWL Write Command to CAS Lead Time 17 - 22 - ns tWCR Write Command Hold Time Referenced to RAS 47 - 57 - ns tDHR Data Hold Time Referenced to RAS 50 - 55 - ns tDS DIN Setup Time -2 - -2 - ns 2 tDH DIN Hold Time 17 - 20 - ns 2 1. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.), tAWD tAWD(min.) and tCPW tCPW(min.)(Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Read Cycle Symbol Parameter -60 -70 Min Max Min Max Unit Notes tRAC Access Time from RAS - 60 - 70 ns 1, 2 tCAC Access Time from CAS - 20 - 25 ns 1, 2 tAA Access Time from Address - 35 - 40 ns 1, 2 tOEA Access Time from OE - 20 - 25 ns 1, 2 tRCS Read Command Setup Time 2 - 2 - ns tRCH Read Command Hold Time to CAS 2 - 2 - ns 3 tRRH Read Command Hold Time to RAS 0 - 0 - ns 3 tRAL Column Address to RAS Lead Time 35 - 40 - ns tCAL Column Address to CAS Lead Time - - - - ns tCLZ CAS to Output in Low-Z 2 - 2 - ns tROH RAS Hold to Output Enable 5 - 5 - 4 ns tOH Output Data Hold Time 2 - 2 - ns tOHO Output Data Hold Time from OE 2 - 2 - ns tOEZ Output Buffer Turn-off Delay from OE 2 20 2 20 ns 5 tCDD CAS to DIN Delay Time 20 - 25 - ns 6 tOFF Output Buffer Turn-off Delay 2 20 2 20 ns 5 1. 2. 3. 4. 5. Measured with the specified current load and 100pF. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA. Either tRCH or tRRH must be satisfied. This timing parameter is not applicable to this product, but applies to a related product in this family. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. Either tCDD or tODD must be satisfied. 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Fast Page Mode Cycle -60 Symbol -70 Parameter Unit Notes Min Max Min Max Fast Page Mode Cycle Time 40 - 45 - ns tRASP Fast Page Mode RAS Pulse Width 60 100K 70 100K ns tCPRH RAS Hold Time from CAS Precharge 40 - 45 - ns tCPA Access Time from CAS Precharge - 40 - 45 ns 1, 2 Unit Notes Min Max Min Max tPC 1. Measured with the specified current load and 100pF. 2. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA. Read-Modify-Write Cycle -60 Symbol -70 Parameter tRWC Read-Modify-Write Cycle Time 158 - 188 - ns tRWD RAS to WE Delay Time 83 - 98 - ns 1 tCWD CAS to WE Delay Time 45 - 55 - ns 1 tAWD Column Address to WE Delay Time 58 - 68 - ns 1 tOEH OE Command Hold Time 15 - 15 - ns 1. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.), tAWD tAWD(min.) and tCPW tCPW(min.)(Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. Fast Page Mode Read-Modify-Write Cycle -60 Symbol -70 Parameter Unit Min Max Min Notes Max tPRWC Fast Page Mode Read-Modify-Write Cycle Time 83 - 98 - ns tCPW WE Delay time from CAS Precharge - - - - ns 1 1. This timing parameter is not applicable to this product, but applies to a related product in this family. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Refresh Cycle -60 Symbol -70 Parameter Unit Min Max Min Notes Max tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 8 - 8 - ns tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 14 - 14 - ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 15 - 15 - ns tWRH WE Hold Time (CAS before RAS Refresh Cycle) 8 - 8 - ns tRPC RAS Precharge to CAS Hold Time 3 - 3 - ns tREF Refresh Period - 16 - 16 ms 1 1. 1024 refreshes are required every 16ms. Presence Detect Read Cycle -60 Symbol -70 Parameter Unit Notes 10 ns 1 10 ns 2 Min tPD tPDOFF Max Min Max PDE to Valid Presence Detect Data - 10 - PDE Inactive to Presence Detects Inactive 0 10 0 1. Measured with the specified current load and 100pF. 2. tPDOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Read Cycle tRC tRP tRAS VIH RAS VIL tCSH tCRP tRSH tRCD CAS VIH tCAS tCLCH or CASx VIL tRAL tRAD tASR tCAL tASC tRAH tAR tCAH VIH Address Row Column VIL tRCH tRCS tRRH VIH WE VIL tAA tROH VIH tOEA OE VIL tDZC tCDD tDZO tODD VIH Hi-Z DIN VIL tCAC tCLZ tOFF tOEZ VOH Hi-Z DOUT Valid Data Out Hi-Z VOL tRAC : "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 26 tOH tOHO 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD or tRSH tCRP tCAS tCLCH CAS VIH CASx VIL tRAD tASR tASC tRAH tCAH tAR VIH Address Row Column VIL tWCR tWCS VIH tWCH tWP WE VIL VIH OE VIL tDS tDHR tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : "H" or "L" 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Write Cycle (Late Write) tRC tRAS tRP VIH RAS VIL tCSH tRSH tRCD or CAS VIH tCRP tCAS tCLCH CASx VIL tRAD tASR tASC tRAH tCAH tAR VIH Address Row Column VIL tRCS tWCR VIH tCWL tWP WE VIL tRWL VIH OE tOEH VIL tDH tODD tDZO tDZC VIH DIN tDS tDHR Valid Data In Hi-Z VIL tOEZ tCLZ tOEA VOH DOUT VOL Hi-Z Hi-Z* : "H" or "L" *Output remains Hi-Z because WE is latched internally following twp min. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Read-Modify-Write-Cycle tRWC tRP tRAS VIH RAS VIL tCSH tRCD or CAS VIH tCAS tCLCH tRAD CASx VIL tASR tCRP tRSH tASC tCAH tRAH tAR VIH Address Column Row VIL tCWD tRWL tCWL tAWD tWCR tRWD VIH WE tWP tAA VIL tRCS tOEH VIH tOEA OE VIL tDHR tDZC tDH tDS tDZO VIH Hi-Z DIN VIL DIN tCAC tCLZ tODD tOEZ VOH DOUT Hi-Z Hi-Z* DOUT VOL tRAC tOHO : "H" or "L" 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 *Output remains Hi-Z because WE is latched internally following twp min. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Fast Page Mode Read Cycle tRASP tRP tCPRH VIH RAS VIL or tPC tCP tRCD CAS VIH CASx VIL tCAL tCSH tAR tASR tRAH tCAS tCLCH tCAS tCLCH tCAS tCLCH tASC tCAH tCAH tASC tCRP tRSH tCP tCAH tASC tRAL VIH Address Row Column 1 Column 2 Column N VIL tRAD tRCS tRCS tRCS tRCH tRCH tRCH VIH WE VIL tRRH tAA tAA tAA tCPA tOEA tCPA tOEA VIH tROH tOEA OE VIL tOHO tOHO tOH tOH tDZC tDZC tDZO tDZO tDZC tDZO tODD tOHO tOH tCDD tODD tODD VIH DIN VIL tCAC tCAC tRAC tOFF tCLZ VOH DOUT DOUT 1 VOL tOEZ tOEZ tCLZ tCAC tOFF DOUT 2 tOFF tCLZ tOEZ DOUT N : "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Fast Page Mode Write Cycle tRP tRASP VIH RAS VIL tPC tRCD or tCP CAS VIH tASR tCSH tAR tRAH tASC tCRP tCAS tCLCH tCAS tCLCH tCAS tCLCH CASx VIL tRSH tCP tCAH tASC tCAH tASC tCAH Column 1 Column 2 Column N tCWL tCWL VIH Address Row VIL tRAD tCWL tRWL tWCR tWCH tWCH tWCS tWCS tWP VIH tWCH tWCS tWP tWP WE VIL VIH OE VIL tDHR tDS tDH tDS tDH tDS tDH VIH DIN DIN 1 VIL DIN 2 DIN N VOH DOUT VOL : "H" or "L" 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Fast Page Mode Read-Modify-Write Cycle tRASP tRP VIH RAS VIL tPRWC tCP tRCD CAS VIH or CASx VIL tCAS tCLCH tCSH tASR tRAH tASC tCAH tCWL tASC tCAS tCLCH tCWL tCAS tCLCH tAR tCRP tRSH tCP tCWL tCAH tASC tCAH tRWL VIH Address Row Column 1 Column 2 Column N VIL tCPW tAWD tCPW tAWD tCWD tRWD tAWD tRCS tCWD tRCS tRCS tCWD tWCR tWP tWP tWP VIH WE tCAC VIL tCAC tCAC tAA tAA tAA tRAD tCPA tCPA VIH OE tOEH VIL tOEH tOEA tOEA tDH tDS tDZC tDHR tOEH tDZO tODD tOEA tDH tDH tDS tDS tODD tODD VIH DIN DIN 1 VIL tCLZ DIN 2 DIN N tOEZ tOHO tOEZ tOHO tCLZ tOEZ tOHO tCLZ VOH DOUT VOL tRAC DOUT 1 DOUT 2 DOUT N : "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP CAS VIH or CASx VIL tRAH tASR VIH Address Row VIL VOH Hi-Z DOUT VOL : "H" or "L" Note: WE, OE, DIN are "H" or "L" 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE CAS Before RAS Refresh Cycle t RC tRAS tRP VIH RAS VIL t RPC tRPC tCSR tCSR tCP t CHR CAS VIH or CASx VIL tWRH tWRH tWRP tWRP VIH WE VIL VIH OE VIL tODD tCDD VOH DIN Hi-Z VOL tOEZ tOFF DOUT VOH Hi-Z VOL : "H" or "L" NOTE: Address is "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRCD tRSH tCRP tCHR CAS VIH or CASx VIL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE tORD VIL tAA VIH tOEA OE VIL tDZC tDZO VIH DIN tCDD tODD Hi-Z VIL tCAC tOFF tCLZ tOEZ VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : "H" or "L" 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP CAS VIH or CASx VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL VIH OE VIL t DS tDH VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 26 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Presence Detect Read Cycle vIH PDE vIL tPDOFF* tPD vOH PD1-PD8 Valid Presence Detect vOL *PD pins must be pulled high at next level of assembly 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 26 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Layout Drawing 133.35 5.25 131.35 5.171 (2X) 4.00 .157 127.35 5.014 Front 6.35 .250 3.0 .118 25.4 1.00 (2) 0 3.1877 .1255 17.78 .700 1.27 PITCH .050 1.00 WIDTH .039 42.18 1.661 65.68 2.586 SEE DETAIL A Side Detail A SCALE 4/1 9.00 .354 MAX. Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 26 2.0 .078 3.0 .118 _ 1.27 + 0.10 _ .050 + .004 5.232 .206 MIN. R 1.00 .0393 Millimeters Inches 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 IBM11M1720B IBM11M1720B 1M x 72 DRAM MODULE Revision Log Rev 07/95 Contents of Modification Initial Release. Updated ordering information 5/96 Corrected 70ns currents: ICC1, ICC3, ICC6 Added timing: tCAS Improved timings: tCAH, tCRP, tDH, tRRH, tROH, tOEZ, tCDD, tOFF, tOEH, tCSR, tCHR 50H4346 50H4346 SA14-4606-02 SA14-4606-02 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 26 ® © International Business Machines Corp.1996 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant. SA14-4606-02 SA14-4606-02