IBM11D4325B4M EDOMMDS47DSU-021041221 IBM11D8325B8M IBM11D4325B IBM11D8325B - Datasheet Archive

 

IBM11D4325B IBM11D8325B 4M/8M x 32 DRAM Module Features · 72-Pin JEDEC Standard Single-In-Line Memory Module ·

 

IBM11D4325B4M IBM11D4325B4M x 3211/11, 5.0V, Sn/Pb, EDOMMDS47DSU-021041221 EDOMMDS47DSU-021041221. IBM11D8325B8M IBM11D8325B8M x 3211/11, 5.0V, Sn/Pb, EDOMMDS47DSU-021041221 EDOMMDS47DSU-021041221. IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Features · 72-Pin JEDEC Standard Single-In-Line Memory Module · Performance: -60 -70 tRAC RAS Access Time 60ns 70ns tCAC CAS Access Time 15ns 20ns tAA Access Time From Address 30ns 35ns tRC Cycle Time 104ns 124ns tHPC EDO Mode Cycle Time 25ns · High Performance CMOS process · Single 5V, ± 0.5V Power Supply · All inputs & outputs are fully TTL & CMOS compatible · Extended Data Out (EDO) access cycle · Refresh Modes: RAS-Only, CBR and Hidden Refresh · 2048 refresh cycles distributed across 32ms · 11/11 Addressing (Row/Column) · Optimized for use in byte-write non-parity applications · Sn/Pb tab versions only · 16MB versions in TSOP or SOJ packages. · 32MB version only in SOJ package. 30ns Description The IBM11D8325B IBM11D8325B is a 32MB industry standard 72-pin 4-byte single in-line memory module (SIMM) manufactured using EDO DRAMs. The use of EDO DRAMs allows for a reduction in Page Mode Cycle Time from 40ns (Fast Page) to 25ns (EDO, 60ns sort). The module is organized as an 8Mx32 high speed memory array, and is configured as two 4Mx32 banks -each independently selectable via unique RAS inputs. The assembly is manufactured with sixteen 4Mx4 devices, each in a 300mil SOJ package, and is compatible with the JEDEC 72-Pin SIMM standard. The IBM11D4325B IBM11D4325B is a 16MB half populated version, manufactured with eight 4Mx4 devices each in a 300mil TSOP or SOJ package. The IBM 72-Pin SIMMs provide a high performance, flexible 4-byte interface in a 4.25" long footprint. Card Outline 1 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 36 37 72 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Pin Description Pinout Pin # RAS0 - RAS3 Row Address Strobe (32MB) CAS0 - CAS3 Column Address Strobe WE A0 - A10 DQ0-7, 9-16, 18-25, 27-34 Name VSS Name Pin # 25 DQ24 49 DQ9 2 3 4 5 Row Address Strobe (16MB) Pin # 1 RAS0, RAS2 DQ0 DQ18 DQ1 DQ19 26 27 28 29 50 51 52 53 DQ27 DQ10 DQ28 DQ11 54 DQ29 55 56 57 DQ12 DQ30 DQ13 6 Address Inputs Data Input/output DQ2 30 7 8 9 Read/write Input DQ7 DQ25 A7 NC VCC 31 32 33 A8 A9 RAS3* Name VCC Power (+5V) VSS Ground 10 DQ20 DQ3 DQ21 VCC 34 RAS2 58 DQ31 NC No Connect 11 NC 35 NC 59 VCC Presence Detects 12 13 14 A0 A1 A2 36 37 38 60 61 62 DQ32 DQ14 DQ33 15 A3 39 NC NC NC VSS 63 DQ15 16 17 18 19 20 21 22 23 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 40 41 42 43 44 45 46 47 CAS0 CAS2 CAS3 CAS1 RAS0 RAS1* NC WE 64 65 66 67 68 69 70 71 24 DQ6 48 NC 72 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS PD1 - PD4 Ordering Information Part Number Organization Speed IBM11D4325B-60 IBM11D4325B-60 Package 4.25" x 1" x .205" 60ns Dimensions SOJ Notes 70ns IBM11D4325B-60J IBM11D4325B-60J Leads 60ns IBM11D4325B-70 IBM11D4325B-70 Addr. IBM11D4325B-70J IBM11D4325B-70J 4M x 32 1 1 70ns IBM11D4325B-60 IBM11D4325B-60 60ns IBM11D4325B-70 IBM11D4325B-70 70ns IBM11D4325B-60T IBM11D4325B-60T 60ns IBM11D4325B-70T IBM11D4325B-70T 70ns IBM11D8325B-60 IBM11D8325B-60 60ns IBM11D8325B-70 IBM11D8325B-70 11/11 Sn/Pb 4.25" x 1" x .104" TSOP 1 1 70ns 8M x 32 4.25" x 1" x .360" SOJ IBM11D8325B-60J IBM11D8325B-60J 60ns 1 IBM11D8325B-70J IBM11D8325B-70J 70ns 1 1. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev E. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Block Diagram Applies to both 16MB and 32MB SIMMs DQ7 DQ0 DQ1-4 WE CAS0 RAS0 WE CAS RAS OE U1 DQ16 DQ9 DQ1-4 DQ1-4 WE CAS RAS OE U2 WE CAS RAS OE U3 DQ1-4 WE CAS RAS OE U4 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 11 11 CAS1 DQ18 DQ25 DQ1-4 CAS2 RAS2 WE CAS RAS OE U5 DQ27 DQ1-4 DQ1-4 WE CAS RAS OE DQ34 U6 WE CAS RAS OE U7 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 DQ1-4 WE CAS RAS OE 11 U8 A0-A10 A0-A10 11 CAS3 A0-A10 A0-A10 Applies to 32MB SIMM only DQ0 DQ7 DQ1-4 WE CAS0 RAS1 WE CAS RAS OE U15 DQ1-4 WE CAS RAS OE U16 DQ9 DQ16 DQ1-4 WE CAS RAS OE U11 DQ1-4 WE CAS RAS OE U12 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 11 11 CAS1 DQ18 DQ25 DQ1-4 CAS2 RAS3 WE CAS RAS OE U13 DQ1-4 WE CAS RAS OE U14 DQ27 DQ34 DQ1-4 WE CAS RAS OE U9 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 A0-A10 11 11 11 DQ1-4 WE CAS RAS OE U10 A0-A10 A0-A10 11 CAS3 A0-A10 A0-A10 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Truth Table RAS CAS WE Row Address Column Address All DQ bits Standby H HX X X X High Impedance Read L L H Row Col Valid Data Out Early-Write L L L Row Col Valid Data In EDO Mode - Read: 1st Cycle L HL H Row Col Valid Data Out Subsequent Cycles L HL H N/A Col Valid Data Out EDO Mode - Write: 1st Cycle L HL L Row Col Valid Data In Subsequent Cycles L HL L N/A Col Valid Data In RAS-Only Refresh L H X Row N/A High Impedance HL L H X X High Impedance Read LHL L H Row Col Data Out Write LHL L L Row Col Data In Function CAS-Before-RAS Refresh Hidden Refresh Presence Detect 4M x 32 8M x 32 Pin -60 -70 -60 -70 PD1 VSS VSS NC NC PD2 NC NC VSS VSS PD3 NC VSS NC VSS PD4 NC NC NC NC 1. NC= OPEN, Vss = GND ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Absolute Maximum Ratings Symbol Parameter Rating Units Notes -1.0 to +7.0 V 1 VCC Power Supply Voltage VIN Input Voltage -0.5 to min (VCC + 0.5, 7.0) V 1 VOUT Output Voltage -0.5 to min (VCC + 0.5, 7.0) V 1 TOPR Operating Temperature 0 to +70 °C 1 TSTG Storage Temperature -55 to +125 °C 1 3.74 (16MB) 7.5 (32MB) W 1, 2 50 mA 1 PD Power Dissipation IOUT Short Circuit Output Current 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power occurs when all banks are active (refresh cycle). Recommended DC Operating Conditions Symbol Parameter (TA = 0 to 70°C) Min Typ Max Units Notes VCC Supply Voltage 4.5 5.0 5.5 V 1 VIH Input High Voltage 2.4 - VCC + 0.5 V 1, 2 VIL Input Low Voltage -0.5 - 0.8 V 1, 2 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 2.0V for pulse widths of 4.0ns (or VCC + 1.0V for 8.0ns). Additionally, VIL may undershoot to -2.0V for pulse widths 4.0ns (or -1.0V for 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA = 0 to +70°C, VCC = 5.0V ± 0.5V) Symbol Parameter 4M x 32 8M x 32 Max Max Units CI1 Input Capacitance (A0-A10 A0-A10) 55 98 pF CI2 Input Capacitance (16MB: RAS0, 32MB: RAS0, 1) 40 40 pF CI3 Input Capacitance (16MB: RAS2, 32MB: RAS2, 3) 40 40 pF CI4 Input Capacitance (CAS) 25 40 pF CI5 Input Capacitance (WE) 66 127 pF CI/O Output Capacitance (DQ0 - DQ34) 13 25 Notes pF 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module DC Electrical Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V) 4M x 32 Symbol 8M x 32 Parameter Units ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) Max Min - 680 - 696 -70 - 600 - 616 - 16 - 32 1, 2, 3 Max -60 Notes mA Min ICC2 Standby Current (TTL) Power Supply Standby Current (RAS = CAS VIH) RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS VIH: tRC = tRC min) -60 - 680 - 696 ICC3 -70 - 600 - 616 EDO Mode Current Average Power Supply Current, EDO Mode (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) -60 - 520 - 536 -70 - 440 - 450 - 8 - 16 -60 - 680 - 696 -70 - 600 - 616 RAS -40 +40 -40 +40 CAS -20 +20 -40 +40 All others -80 +80 -160 +160 ICC4 ICC5 CAS Before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) mA II(L) Input Leakage Current Input Leakage Current, any input (0.0 VIN (VCC < 6.0V) All Other Pins Not Under Test = 0V 1, 3, 4 mA Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) ICC6 mA 1, 2, 3 mA mA 1, 3, 4 µA IO(L) Output Leakage Current (DOUT is disabled, 0.0 VOUT VCC) -10 +10 -20 +20 µA VOH Output High Level Output "H" Level Voltage (IOUT = -5mA) 2.4 - 2.4 - V VOL Output Low Level Output "L" Level Voltage (IOUT = +4.2mA) - 0.4 - 0.4 V 1. 2. 3. 4. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH Refresh current is specified for 1 bank active and 1 bank standby. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module AC Characteristics (TA = 0 to +70°C, VCC = 5 ± 0.5V) 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required. 3. AC measurements assume tT = 2ns. 4. Valid column addresses are A0 through A10. Read, Write, and Refresh Cycles (Common Parameters) -60 Symbol -70 Parameter Units Min Max Min Notes Max tRC Random Read or Write Cycle Time 104 - 124 - ns tRP RAS Precharge Time 40 - 50 - ns tCP CAS Precharge Time 10 - 10 - ns tRAS RAS Pulse Width 60 10K 70 16K ns tCAS CAS Pulse Width 10 10K 12 10K ns tASR Row Address Setup Time 0 - 0 - ns tRAH Row Address Hold Time 10 - 10 - ns tASC Column Address Setup Time 0 - 0 - ns tCAH Column Address Hold Time 10 - 10 - ns tRCD RAS to CAS Delay Time 14 45 14 50 ns 1 tRAD RAS to Column Address Delay Time 12 30 12 35 ns 2 tRSH RAS Hold Time 10 - 12 - ns tCSH CAS Hold Time 50 - 55 - ns tCRP CAS to RAS Precharge Time 5 - 5 - ns tDZC CAS Delay Time from DIN 0 - 0 - ns tAR Column Address Hold Time referenced to RAS - - - - ns tT Transition Time (Rise and Fall) 2 30 2 30 ns 3 1. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: if tRCD is greater than the specified tRCD (max) limit, then access time is controlled by tCAC. 2. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 3. This parameter is not applicable to this product, but applies to a related product in this family. 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Write Cycle -60 Symbol Parameter -70 Min Max Min Max Units tWCS Write Command Set Up Time 0 - 0 - ns tWCH Write Command Hold Time 10 - 12 - ns tWP Write Command Pulse Width 10 - 12 - ns tDS DIN Setup Time 0 - 0 - ns tDH DIN Hold Time 10 - 12 - Notes ns Read Cycle -60 Symbol -70 Parameter Units Min Max Min Notes Max tRAC Access Time from RAS - 60 - 70 ns 1, 2 tCAC Access Time from CAS - 15 - 20 ns 1, 2 tAA Access Time from Address - 30 - 35 ns 1, 2 tRCS Read Command Setup Time 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - ns 3 tRRH Read Command Hold Time to RAS 0 - 0 - ns 3 tRAL Column Address to RAS Lead Time 30 - 35 - ns tCLZ CAS to Output in Low-Z 0 - 0 - ns tCDD CAS to DIN Delay Time 15 - 15 - ns tOFF Output Buffer Turn-off Delay - 15 - 15 ns 1. 2. 3. 4. 4 Measured with the specified current load and 100pF. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA. Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Hyper Page Mode (Extended Data Out) Cycle -60 Symbol -70 Parameter Units Min. Max. Min. Notes Max. tHCAS CAS Pulse Width (EDO Mode) 10 10K 12 10K ns tHPC EDO Mode Cycle Time (Read/Write) 25 - 30 - ns tDOH Data-out Hold Time from CAS 5 - 5 - ns tWHZ Output buffer Turn-Off Delay from WE 0 10 0 15 ns tWPZ WE Pulse Width to Output Disable at CAS High 10 - 10 - ns tCPRH RAS Hold Time from CAS Precharge 35 - 40 - ns tCPA Access Time from CAS Precharge - 35 - 40 ns tRASP EDO Mode RAS Pulse Width 60 125K 70 125K ns 1, 2 1. Access time assumes a load of 100pF at VOL = 0.8V and VOH = 2V. 2. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA. Refresh Cycle -60 Symbol -70 Parameter Units Min Max Min Notes Max tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 5 - 5 - ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tWRH WE Hold Time (CAS before RAS Refresh Cycle) 10 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - ns tREF Refresh Period - 32 - 32 ms 1 1. 2048 refreshes are required every 32ms. 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Read Cycle tRC tRAS tRP VIH RAS tAR VIL tCSH tRCD tRSH VIH tCRP tCAS CAS VIL tRAD tRAL tASR tRAH tASC tCAH VIH Address VIL Row Column tWRP tWRH tRCH tRRH tRCS VIH NOTE 1 WE VIL tAA tDZC tCDD VIH DIN Hi-Z VIL tCAC tOFF tCLZ VOH DOUT Hi-Z VOL Valid Data Out Hi-Z tRAC : "H" or "L" NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH VIH CAS tCRP tCAS VIL tRAD tASR tASC tRAH tCAH VIH Address VIL Row tWRP tWRH Column tWCS VIH WE VIL tWCH tWP NOTE 1 tDS tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : "H" or "L" 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Extended Data Out Mode Read Cycle tRP tRASP VIH RAS tAR tCPRH VIL tCRP tHPC tRCD CAS tHCAS tCP tCP tHCAS VIH tRSH tHCAS VIL tCSH tASR Address tRAH tASC tRAL tCAH tASC tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tRCH tRRH tWRP tWRH tRCS VIH WE VIL NOTE 1 tCAC tCAC tCPA tCPA tDOH tCAC tOFF tAA tAA tRAC tAA tWP tDOH tCLZ DOUT VOH VOL Hi-Z : "H" or "L" Data Out 1 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 21 Data Out 2 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Extended Data Out Mode Read Cycle (WE Control) tRP tRASP VIH tAR RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tRSH tHCAS tHCAS VIH CAS VIL tCSH tASR Address tRAH tRAL tASC tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 tRCH tWRP tWRH tRCS tRCH tRRH tCAC tRCS tRCH tOFF tRCS tWPZ VIH VIL Column N tAA tAA tRAD WE tASC tWPZ NOTE 1 tCAC tCPA tRAC tAA tCAC tWHZ tCPA tWHZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 Data Out 1 Data Out 2 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Extended Data Out Mode Early Write Cycle tRP tRASP VIH tAR RAS VIL tCRP tHPC tRCD tCP tCP tRSH tHCAS tHCAS VIH tHCAS CAS VIL tRAD tCSH tASR Address tRAH tASC tRAL tCAH tASC tCAH tASC tCAH VIH Row VIL Column 1 Column 2 Column N tCWL tWCS VIH WE VIL tRWL tWCH tWRP tWRH tWCS tWP tWCH tWCS tWP tWCH tWP NOTE 1 tDHR tDS DIN tDH tDS tDH tDS tDH VIH Data In 1 VIL : "H" or "L" Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 21 Data In 2 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP VIH VIL tASR tRAH VIH Address Row VIL VOH Hi-Z DOUT VOL : "H" or "L" Note: WE, DIN are "H" or "L" 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module CAS Before RAS Refresh Cycle tRC tRAS tRP VIH RAS VIL t RPC tRPC tCSR tCSR tCP tCHR VIH CAS VIL tWRH tWRH tWRP tWRP VIH WE VIL tCDD VOH DIN Hi-Z VOL tOFF DOUT VOH Hi-Z VOL : "H" or "L" NOTE: Address is "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRSH tRCD tCHR tCRP VIH CAS VIL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE VIL tAA tDZC tCDD VIH DIN Hi-Z VIL tCAC tOFF tCLZ VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : "H" or "L" 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP VIH CAS VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL t DS tDH VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : "H" or "L" ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Layout Drawing 107.95 4.25 101.190 3.983 Front 10.16 .400 6.35 .25 25.4 1.00 (2X) 0 3.1877 .1255 6.35 .250 2.03 .08 1.27 PITCH .050 44.45 1.75 1.00 WIDTH .039 95.25 3.75 REF. Side (16MB SOJ) Side (32MB) Side (16MB TSOP) .205 MAX. .104 MAX. .360 MAX. _ .1016 1.27 + .0762 _ .004 .050 + .003 5.848 .230 MIN. _ .1016 1.27 + .0762 _ .004 .050 + .003 _ .1016 1.27 + .0762 _ .004 .050 + .003 NOTE: All dimensions are typical unless otherwise stated. 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 5.848 .285 MIN. 9.14 7.239 .285 MIN. 2.65 5.848 .230 MIN. 5.2 MILLIMETERS INCHES ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 21 IBM11D4325B IBM11D4325B IBM11D8325B IBM11D8325B 4M/8M x 32 DRAM Module Revision Log Rev Contents of Modification Initial release of combined spec for 4M x 32, 8M x 32 3/96 Removed Gold-Tab versions CBR timing diagram changed to allow CAS to remain low for back-to-back CBR cycles (originally released as spec #'s 26H3207 26H3207 and 26H3208 26H3208) 5/96 Added 16Mb TSOP version ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 21 50H7996 50H7996 SA14-4341-01 SA14-4341-01 Revised 5/96 ® © International Business Machines Corp.1996 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant. SA14-4341-01 SA14-4341-01