IA186EM/IA188EM IA211050831-18 IA186EM IA188EM Am186EM/Am188EM Am186EM/188EM - Datasheet Archive

 

8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 ® IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet ®

 

IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 ® IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Copyright Data Sheet January 25, 2010 2010 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 AMD, Am186, and Am188 are trademarks of Advanced Micro Devices, Inc. MILESTM is a trademark of Innovasic Semiconductor, Inc. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 TABLE OF CONTENTS List of Figures .8 List of Tables .9 Conventions .12 Acronyms and Abbreviations .13 1. Introduction.14 1.1 General Description.14 1.2 Features .14 2. Packaging , Pin Descriptions, and Physical Dimensions .15 2.1 Packages and Pinouts .15 2.1.1 IA186EM IA186EM TQFP Package .16 2.1.2 IA188EM IA188EM TQFP Package .19 2.1.3 TQFP Physical Dimensions .22 2.1.4 IA186EM IA186EM PQFP Package .23 2.1.5 IA188EM IA188EM PQFP Package .26 2.1.6 PQFP Physical Dimensions .29 2.2 Pin Descriptions .30 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16­a0-Address Bus (synchronous outputs with tristate) .30 2.2.2 ad15­ad8 (IA186EM IA186EM)-Address/data bus (level-sensitive synchronous inouts with tristate) .30 2.2.3 ad7­ad0-Address/Data bus (level-sensitive synchronous inouts with tristate) .30 2.2.4 ao15­ao8 (IA188EM IA188EM)-Address-only bus (level-sensitive synchronous outputs with tristate) .30 2.2.5 ale-Address Latch Enable (synchronous output) .31 2.2.6 ardy-Asynchronous Ready (level-sensitive asynchronous input) .31 2.2.7 bhe_n/aden_n (IA186EM IA186EM)-Bus High Enable (synchronous output with tristate)/Address Enable (input with internal pull-up) .31 2.2.8 clkouta-Clock Output A (synchronous output) .32 2.2.9 clkoutb-Clock Output B (synchronous output) .32 2.2.10 den_n/pio5-Data Enable Strobe (synchronous output with tristate) .32 2.2.11 drq1/pio12­drq0/pio13-DMA Requests (synchronous level-sensitive inputs) .32 2.2.12 dt/r_n/pio4-Data Transmit or Receive (synchronous output with tristate) .32 2.2.13 gnd-Ground .32 2.2.14 hlda-Bus Hold Acknowledge (synchronous output) .33 2.2.15 hold-Bus Hold Request (synchronous level-sensitive input) .33 2.2.16 int0-Maskable Interrupt Request 0 (asynchronous input) .33 2.2.17 int1/select_n-Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs) .33 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.18 int2/inta0_n/pio31-Maskable Interrupt Request 2 (asynchronous input)/Interrupt Acknowledge 0 (synchronous output) .34 2.2.19 int3/inta1_n/irq-Maskable Interrupt Request 3 (asynchronous input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt Acknowledge (synchronous output) .34 2.2.20 int4/pio30-Maskable Interrupt Request 4 (asynchronous input).34 2.2.21 lcs_n/once0_n-Lower Memory Chip Select (synchronous output with internal pull-up)/ONCE Mode Request (input) .35 2.2.22 mcs2_n-mcs0_n (no pio, pio15, pio 14)-Midrange Memory Chip Selects (synchronous outputs with internal pull-up) .35 2.2.23 mcs3_n/rfsh_n (pio25)-Midrange Memory Chip Select (synchronous output with internal pull-up)/Automatic Refresh (synchronous output) .35 2.2.24 nmi-Nonmaskable Interrupt (synchronous edge-sensitive input) .35 2.2.25 pcs3_n­pcs0_n (pio19­pio16)-Peripheral Chip Selects 3­0 (synchronous outputs) .36 2.2.26 pcs5_n/a1-Peripheral Chip Select 5 (synchronous output)/Latched Address Bit 1 (synchronous output) .36 2.2.27 pcs6_n/a2-Peripheral Chip Select 6 (synchronous output)/latched Address Bit 2 (synchronous output) .36 2.2.28 pio31­pio0-Programmable I/O Pins (asynchronous input/output open-drain) .37 2.2.29 rd_n-Read strobe (synchronous output with tristate) .37 2.2.30 res_n-Reset (asynchronous level-sensitive input) .37 2.2.31 rfsh2_n/aden_n (IA188EM IA188EM)-Refresh 2 (synchronous output with tristate)/Address Enable (input with internal pull-up) .37 2.2.32 rxd/pio28-Receive Data (asynchronous input) .37 2.2.33 s2_n­s0_n-Bus Cycle Status (synchronous outputs with tristate) .38 2.2.34 s6/clkdiv2_n/pio29-Bus Cycle Status Bit 6 (synchronous output)/Clock Divide by 2 (input with internal pull-up) .38 2.2.35 sclk-Serial Clock (synchronous outputs with tristate) .38 2.2.36 sdata-Serial Data (synchronous inout) .39 2.2.37 sden1­sden0-Serial Data Enables (synchronous outputs with tristate) .39 2.2.38 srdy/pio6-Synchronous Ready (synchronous level-sensitive input) .39 2.2.39 tmrin0/pio11-Timer Input 0 (synchronous edge-sensitive input) .39 2.2.40 tmrin1/pio0-Timer Input 1 (synchronous edge-sensitive input) .39 2.2.41 tmrout0/pio10-Timer Output 0 (synchronous output) .39 2.2.42 tmrout1/pio1-Timer Output 1 (synchronous output) .39 2.2.43 txd/pio22-Transmit Data (asynchronous output) .39 2.2.44 ucs_n/once1_n-Upper Memory Chip Select (synchronous output)/ONCE Mode Request 1 (input with internal pull-up) .40 2.2.45 uzi_n/pio26-Upper Zero Indicate (synchronous output) .40 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 3. 4. 5. Data Sheet January 25, 2010 2.2.46 vcc-Power Supply (input).40 2.2.47 whb_n (IA186EM IA186EM)-Write High Byte (synchronous output with tristate) .40 2.2.48 wlb_n/wb_n-Write Low Byte (IA186EM IA186EM) (synchronous output with tristate)/Write Byte (IA188EM IA188EM) (synchronous output with tristate) .40 2.2.49 wr_n-Write Strobe (synchronous output) .41 2.2.50 x1-Crystal Input (input) .41 2.2.51 x2-Crystal Input (input) .41 2.3 Pins Used by Emulators .41 Maximum Ratings, Thermal Characteristics, and DC Parameters .42 Device Architecture .43 4.1 Bus Interface and Control .43 4.2 Clock and Power Management .45 4.3 System Clocks .45 4.4 Power-Save Mode .46 4.5 Initialization and Reset .46 4.6 Reset Configuration Register .46 4.7 Chip Selects .47 4.8 Chip-Select Timing .47 4.9 Ready- and Wait-State Programming.47 4.10 Chip Select Overlap .47 4.11 Upper Memory Chip Select.48 4.12 Low Memory Chip Select .49 4.13 Midrange Memory Chip Selects .49 4.14 Peripheral Chip Selects .49 4.15 Refresh Control .50 4.16 Interrupt Control .50 4.16.1 Interrupt Types.51 4.17 Timer Control .52 4.18 Direct Memory Access (DMA) .52 4.19 DMA Operation.53 4.20 DMA Channel Control Registers .53 4.21 DMA Priority .54 4.22 Asynchronous Serial Port .54 4.23 Synchronous Serial Port .55 4.24 Programmable I/O (PIO) .55 Peripheral Architecture .57 5.1 Control and Registers .57 5.1.1 RELREG (0feh) .59 5.1.2 RESCON (0f6h).59 5.1.3 PRL (0f4h) .59 5.1.4 PDCON (0f0h) .60 5.1.5 EDRAM (0e4h) .61 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 5.1.15 5.1.16 5.1.17 5.1.18 5.1.19 5.1.20 5.1.21 5.1.22 5.1.23 5.1.24 5.1.25 5.1.26 5.1.27 5.1.28 5.1.29 5.1.30 5.1.31 5.1.32 5.1.33 5.1.34 5.1.35 5.1.36 5.1.37 5.1.38 5.1.39 5.1.40 5.1.41 5.1.42 5.1.43 5.1.44 Data Sheet January 25, 2010 CDRAM (0e2h) .61 MDRAM (0e0h) .62 D1CON (0dah) and D0CON (0cah) .62 D1TC (0d8h) and D0TC (0c8h) .64 D1DSTH (0d6h) and D0DSTH (0c6h) .64 DIDSTL (0d4h) and D0DSTL (0c4h) .65 D1SRCH (0d2h) and D0SRCH (0c2h) .65 D1SRCL (0d0h) and D0SRCL (0c0h) .66 MPCS (0a8h) .66 MMCS (0a6h) .67 PACS (0a4h) .68 LMCS (0a2h) .70 UMCS (0a0h).71 SPBAUD (088h) .72 SPRD (086h).73 SPTD (084h) .74 SPSTS (082h) .74 SPCT (080h) .75 PDATA1 (07ah) and PDATA0 (074h) .77 PDIR1 (078h) and PDIR0 (072h) .79 PIOMODE1 (076h) and PIOMODE0 (070h) .79 T1CON (05eh) and T0CON (056h) .80 T2CON (066h) .81 T2COMPA (062h), T1COMPB (05ch), T1COMPA (05ah), T0COMPB (054h), and T0COMPA (052h) .82 T2CNT (060h), T1CNT (058h), and T0CNT (050h) .83 SPICON (044h) (Master Mode) .83 WDCON (044h) (Master Mode) .84 I4CON (040h) (Master Mode) .84 I3CON (03eh) and I2CON (03ch) (Master Mode) .85 I1CON (03ah) and I0CON (038h) (Master Mode) .85 TCUCON (032h) (Master Mode) .86 T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h) (Slave Mode) .87 DMA1CON/INT6CON (036h) and DMA0CON/INT5CON (034h) (Master Mode) .87 DMA1CON/INT6 (036h) and DMA0CON/INT5 (034h) (Slave Mode) .87 INTSTS (030h) (Master Mode) .88 INTSTS (030h) (Slave Mode) .88 REQST (02eh) (Master Mode) .89 REQST (02eh) (Slave Mode) .90 INSERV (02ch) (Master Mode) .90 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 6. 7. 8. 9. 10. 11. Data Sheet January 25, 2010 5.1.45 INSERV (02ch) (Slave Mode).91 5.1.46 PRIMSK (02ah) (Master and Slave Mode) .92 5.1.47 IMASK (028h) (Master Mode) .92 5.1.48 IMASK (028h) (Slave Mode) .93 5.1.49 POLLST (026h) (Master Mode) .94 5.1.50 POLL (024h) (Master Mode).94 5.1.51 EOI (022h) End-Of-Interrupt Register (Master Mode) .95 5.1.52 EOI (022h) Specific End-Of-Interrupt Register (Slave Mode) .95 5.1.53 INTVEC (020h) Interrupt Vector Register (Slave Mode) .96 5.1.54 SSR (018h).96 5.1.55 SSD0 (016h) and SSD0 (014h).96 5.1.56 SSC (012h).97 5.1.57 SSS (010h) .97 5.2 Reference Documents .98 AC Specifications .98 Instruction Set Summary Table .126 7.1 Key to Abbreviations Used in Instruction Set Summary Table .136 7.1.1 Operand Address Byte .136 7.1.2 Modifier Field .136 7.1.3 Auxiliary Field .137 7.1.4 r/m Field.137 7.1.5 Displacement .137 7.1.6 Immediate Bytes .137 7.1.7 Segment Override Prefix .137 7.1.8 Segment Register .138 7.2 Explanation of Notation Used in Instruction Set Summary Table .138 7.2.1 Opcode .139 7.2.2 Flags Affected After Instruction .139 Innovasic/AMD Part Number Cross-Reference Tables.140 Errata.142 9.1 Errata Summary.142 9.2 Errata Detail .142 Revision History .145 For Additional Information.146 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 LIST OF FIGURES Figure 1. IA186EM IA186EM TQFP Package Diagram .16 Figure 2. IA188EM IA188EM TQFP Package Diagram .19 Figure 3. TQFP Package Dimensions .22 Figure 4. IA186EM IA186EM PQFP Package Diagram .23 Figure 5. IA188EM IA188EM PQFP Package Diagram .26 Figure 6. PQFP Package Dimensions .29 Figure 7. Functional Block Diagram .44 Figure 8. Crystal Configuration .45 Figure 9. Organization of Clock .46 Figure 10. DMA Unit .54 Figure 11. Read Cycle.106 Figure 12. Multiple Read Cycles .107 Figure 13. Write Cycle .109 Figure 14. Multiple Write Cycles .110 Figure 15. PSRAM Read Cycle .112 Figure 16. PSRAM Write Cycle .114 Figure 17. PSRAM Refresh Cycle .116 Figure 18. Interrupt Acknowledge Cycle.117 Figure 19. Software Halt Cycle .119 Figure 20. Clock-Active Mode.120 Figure 21. Clock-Power-Save Mode .120 Figure 22. srdy-Synchronous Ready .121 Figure 23. ardy-Asynchronous Ready.122 Figure 24. Peripherals .122 Figure 25. Reset 1 .123 Figure 26. Reset 2 .123 Figure 27. Bus Hold Entering .124 Figure 28. Bus Hold Leaving .124 Figure 29. Synchronous Serial Interface .125 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 LIST OF TABLES Table 1. IA186EM IA186EM TQFP Numeric Pin Listing .17 Table 2. IA186EM IA186EM TQFP Alphabetic Pin Listing .18 Table 3. IA188EM IA188EM TQFP Numeric Pin Listing .20 Table 4. IA188EM IA188EM TQFP Alphabetic Pin Listing .21 Table 5. IA186EM IA186EM PQFP Numeric Pin Listing .24 Table 6. IA186EM IA186EM PQFP Alphabetic Pin Listing .25 Table 7. IA188EM IA188EM PQFP Numeric Pin Listing .27 Table 8. IA188EM IA188EM PQFP Alphabetic Pin Listing .28 Table 9. Bus Cycle Types for bhe_n and ad0 .31 Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n .38 Table 11. IA186EM IA186EM and IA188EM IA188EM Absolute Maximum Ratings .42 Table 12. IA186EM IA186EM and IA188EM IA188EM Thermal Characteristics .42 Table 13. DC Characteristics Over Commercial Operating Ranges .42 Table 14. Interrupt Types .51 Table 15. Default Status of PIO Pins at Reset .56 Table 16. Peripheral Control Registers .58 Table 17. Peripheral Control Block Relocation Register.59 Table 18. Reset Configuration Register .59 Table 19. Processor Release Level Register .60 Table 20. Power-Save Control Register.60 Table 21. Enable Dynamic RAM Refresh Control Register.61 Table 22. Count for Dynamic RAM Refresh Control Register .62 Table 23. Memory Partition for Dynamic RAM Refresh Control Register .62 Table 24. DMA Control Registers .62 Table 25. DMA Transfer Count Registers .64 Table 26. DMA Destination Address High Register .65 Table 27. DMA Destination Address Low Register .65 Table 28. DMA Source Address High Register.65 Table 29. DMA Source Address Low Register .66 Table 30. MCS and PCS Auxiliary Register .66 Table 31. Midrange Memory Chip Select Register .68 Table 32. Peripheral Chip Select Register .69 Table 33. Low-Memory Chip Select Register .70 Table 34. Upper-Memory Chip Select Register .72 Table 35. Baud Rates .73 Table 36. Serial Port Baud Rate Divisor Registers .73 Table 37. Serial Port Receive Data Register .74 Table 38. Serial Port Transmit Data Register .74 Table 39. Serial Port Status Register .74 Table 40. Serial Port Control Register .75 Table 41. PIO Pin Assignments .77 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Data Sheet January 25, 2010 PDATA 0 .78 PDATA 1 .78 PIO Mode and PIO Direction Settings .79 PDIR0 .79 PDIR1 .79 PIOMODE0 .79 PMODE1 .80 Timer 0 and Timer 1 Mode and Control Registers .80 Timer 2 Mode and Control Registers .81 Timer Maxcount Compare Registers .82 Timer Count Registers .83 Serial Port Interrupt Control Registers .83 Watchdog Timer Interrupt Control Register .84 INT4 Control Register .84 INT2/INT3 Control Register .85 INT0/INT1 Control Register .86 Timer Control Unit Interrupt Control Register .86 Timer Interrupt Control Register .87 DMA and Interrupt Control Register (Master Mode) .87 DMA and Interrupt Control Register (Slave Mode) .88 Interrupt Status Register (Master Mode) .88 Interrupt Status Register (Slave Mode) .89 Interrupt Request Register (Master Mode) .89 Interrupt Request Register (Slave Mode) .90 In-Service Register (Master Mode) .91 In-Service Register (Slave Mode).91 Priority Mask Register .92 Interrupt MASK Register (Master Mode) .93 Interrupt MASK Register (Slave Mode) .93 POLL Status Register .94 Poll Register .95 End-of-Interrupt Register .95 Specific End-of-Interrupt Register.95 Interrupt Vector Register .96 Synchronous Serial Receive Register .96 Synchronous Serial Transmit Registers .97 Synchronous Serial Control Registers .97 Synchronous Serial Status Registers.98 AC Characteristics Over Commercial Operating Ranges (40 MHz) .99 Alphabetic Key to Waveform Parameters .102 Numeric Key to Waveform Parameters .104 Read Cycle Timing .108 Write Cycle Timing .111 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Data Sheet January 25, 2010 PSRAM Read Cycle Timing.113 PSRAM Write Cycle Timing .115 PSRAM Refresh Cycle .116 Interrupt Acknowledge Cycle Timing .118 Software Halt Cycle Timing .119 Clock Timing .121 Ready and Peripheral Timing .123 Reset and Bus Hold Timing .125 Synchronous Serial Interface Timing .126 Instruction Set Summary .126 Innovasic/AMD Part Number Cross-Reference for the TQFP .140 Innovasic/AMD Part Number Cross-Reference for the PQFP .141 Summary of Errata .142 Revision History .145 ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 CONVENTIONS Arial Bold Designates headings, figure captions, and table captions. Blue Designates hyperlinks (PDF copy only). Italics Designates emphasis or caution related to nearby information. Italics is also used to designate variables, refer to related documents, and to differentiate terms from other common words (e.g., During refresh cycles, the a and ad busses may not have the same address during the address phase of the ad bus cycle. The hold latency time [time between the hold and hlda] depends on the current processor activity when the hold is received.). ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 ACRONYMS AND ABBREVIATIONS AMD BIC CDRAM CSC DA DMA EOI ISR LMCS MC MDRAM MILESTM MMCS NMI PCB PIO PLL POR PQFP PSRAM RCU RoHS SFNM TQFP UART UMCS Advanced Micro Devices Bus Interface and Control Count for Dynamic RAM Chip Selects and Control Disable Address Direct Memory Access End of Interrupt Interrupt Service Routine Low-Memory Chip Select Maximum Count Memory Partition for Dynamic RAM Managed IC Lifetime Extension System Midrange Memory Chip Select nonmaskable interrupt peripheral control block programmable I/O phase-lock-loop power-on reset Plastic Quad Flat Package Pseudo-Static RAM Refresh Control Unit Restriction of Hazardous Substances Special Fully Nested mode Thin Quad Flat Package Universal Asynchronous Receiver-Transmitter Upper Memory Chip Select ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 1. Data Sheet January 25, 2010 Introduction The IA186EM/IA188EM IA186EM/IA188EM is a form, fit, and function replacement for the original Advanced Micro Devices Am186EM/Am188EM Am186EM/Am188EM family of microcontrollers. Innovasic produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System cloning technology. This technology produces replacement ICs far more complex than emulation while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the undocumented features are duplicated. 1.1 General Description The IA186EM/IA188EM IA186EM/IA188EM family of microcontrollers replaces obsolete Am186EM/188EM Am186EM/188EM devices, allowing customers to retain existing board designs, software compilers/assemblers and emulation tools, thereby avoiding expensive redesign efforts. The IA186EM/IA188EM IA186EM/IA188EM microcontrollers are an upgrade for the 80C186/80C 80C186/80C 188 microcontroller designs, with integrated peripherals to provide increased functionality and reduce system costs. The Innovasic devices are created to satisfy requirements of embedded products designed for telecommunications, office automation and storage, and industrial controls. 1.2 Features Pin-for-pin compatible with Am186EM/Am188EM Am186EM/Am188EM devices All features are retained, including: ­ A phase-lock loop (PLL) allowing same crystal/system clock frequency ­ 8086/8088 instruction set with additional 186 instruction set extensions ­ Programmable interrupt controller ­ Two Direct Memory Access (DMA) channels ­ Three 16-bit timers ­ Programmable chip select logic and wait-state generator ­ Dedicated watchdog timer ­ Two independent asynchronous serial ports (UARTs) o DMA capability o Hardware flow control o 7-, 8-, or 9-bit data capability Pulse Width Demodulator feature Up to 32 programmable I/O pins (PIO) Pseudo-static/dynamic RAM controller Fully static CMOS design 40-MHz operation at industrial operating conditions +5 VDC power supply ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2. Data Sheet January 25, 2010 Packaging , Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the IA186EM IA186EM and the IA188EM IA188EM is provided separately. Refer to sections, figures, and tables for information on the device of interest. 2.1 Packages and Pinouts The Innovasic Semiconductor IA186EM IA186EM and IA188EM IA188EM microcontroller is available in the following packages: 100-Pin Thin Quad Flat Package (TQFP), equivalent to original SQFP package 100-Plastic Quad Flat Package (PQFP), equivalent to original PQFP package ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.1 Data Sheet January 25, 2010 IA186EM IA186EM TQFP Package drq0/pio12 drq1/pio13 tmrin0/pio11 tmrout0/pio10 tmrout1/pio1 tmrin1/pio0 res_n gnd mcs3_n/rfsh_n/pio25 mcs2_n/pio24 vcc pcs0_n/pio16 pcs1_n/pio17 gnd pcs2_n/pio18 pcs3_n/pio19 vcc pcs5_n/a1/pio3 pcs6_n/a2/pio2 lcs_n/once0_n ucs_n/once1_n int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq The pinout for the IA186EM IA186EM TQFP package is as shown in Figure 1. The corresponding pinout is provided in Tables 1 and 2. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 gnd ad13 ad6 vcc ad14 ad7 ad15 s6/clkdiv2/pio29 uzi_n/pio26 txd rxd sdata/pio21 sden1/pio23 sden0/pio2 int4/pio30 mcs1_n/pio15 mcs0_n/pio14 den_n/pio5 dt/r_n/pio4 nmi srdy/pio6 hold hlda wlb_n whb_n gnd a0 a1 vcc a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ® sclk/pio20 bhe_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 IA186EM IA186EM TQFP Figure 1. IA186EM IA186EM TQFP Package Diagram ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 1. IA186EM IA186EM TQFP Numeric Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 gnd ad13 ad6 vcc ad14 ad7 ad15 s6/clkdiv2/pio29 uzi_n/pio26 txd rxd sdata/pio21 sden1/pio23 sden0/pio22 sclk/pio20 bhe_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n ® Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Name gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 vcc a1 a0 gnd whb_n wlb_n hlda Pin 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 146 Name hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 mcs1_n/pio15 int4/pio30 int3/inta1_n/irq int2/inta0_n/pio31 int1/select_n int0 ucs_n/once1_n lcs_n/once0_n pcs6_n/a2/pio2 pcs5_n/a1/pio3 vcc pcs3_n/pio19 pcs2_n/pio18 gnd pcs1_n/pio17 pcs0_n/pio16 vcc mcs2_n/pio24 mcs3_n/rfsh_n/pio25 gnd res_n tmrin1/pio0 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/pio13 drq0/pio12 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 2. IA186EM IA186EM TQFP Alphabetic Pin Listing Name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17/pio7 a18/pio8 a19/pio9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 Pin 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 1 3 5 7 9 11 14 17 2 4 6 8 10 13 ® Name ad14 ad15 ale ardy bhe_n/aden_n clkouta clkoutb den_n/pio5 drq0/pio12 drq1/pio13 dt/r_n/pio4 gnd gnd gnd gnd gnd gnd hlda hold int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq int4/pio30 lcs_n/once0_n mcs0_n/pio14 mcs1_n/pio15 mcs2_n/pio24 mcs3_n/rfsh_n/pio25 nmi pcs0_n/pio16 pcs1_npio pcs2_n/pio18 Pin 16 18 30 30 27 39 40 72 100 99 71 12 36 41 64 87 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 Name pcs3_n/pio19 pcs5_n/a1/pio3 pcs6_n/a2/pio2 rd_n res_n rxd/pio23 s0_n s1_n s2_n s6/clkdiv2/pio29 sclk/pio20 sdata/pio21 sden0/pio22 sden1/pio23 srdy/pio6 tmrin0/pio11 tmrin1/pio0 tmrout0/pio10 tmrout1/pio1 txd/pio27 ucs_n/once1_n uzi_n/pio26 vcc vcc vcc vcc vcc vcc whb_n wlb_n wr_n x1 x2 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 146 Pin 85 83 82 29 94 24 34 33 32 19 26 23 25 24 69 98 95 97 96 21 80 20 15 38 44 61 84 90 65 66 28 36 37 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.2 Data Sheet January 25, 2010 IA188EM IA188EM TQFP Package drq0/pio12 drq1/pio13 tmrin0/pio11 tmrout0/pio10 tmrout1/pio1 tmrin1/pio0 res_n gnd mcs3_n/rfsh_n/pio25 mcs2_n/pio24 vcc pcs0_n/pio16 pcs1_n/pio17 gnd pcs2_n/pio18 pcs3_n/pio19 vcc pcs5_n/a1/pio3 pcs6_n/a2/pio2 lcs_n/once0_n ucs_n/once1_n int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq The pinout for the IA188EM IA188EM TQFP package is as shown in Figure 2. The corresponding pinout is provided in Tables 3 and 4. ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 s6/clkdiv2/pio29 uzi_n/pio26 txd/pio27 rxd/pio28 sdata/pio21 sden1/pio23 sden0/pio22 ® sclk/pio20 rfsh2_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 IA188EM IA188EM TQFP int4/pio30 mcs1_n/pio15 mcs0_n/pio14 den_n/pio5 dt/r_n/pio4 nmi srdy/pio6 hold hlda wb_n gnd gnd a0 a1 vcc a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 Figure 2. IA188EM IA188EM TQFP Package Diagram ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 3. IA188EM IA188EM TQFP Numeric Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 s6/clkdiv2/pio29 uzi_n/pio26 txd/pio27 rxd/pio28 sdata/pio21 sden1/pio23 sden0/pio22 sclk/pio20 rfsh2_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n ® Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Name gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 vcc a1 a0 gnd gnd wb_n hlda Pin 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 146 Name hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 mcs1_n/pio15 int4/pio30 int3/inta1_n/irq int2/inta0_n/pio31 int1/select_n int0 ucs_n/once1_n lcs_n/once0_n pcs6_n/a2/pio2 pcs5_n/a1/pio3 vcc pcs3_n/pio19 pcs2_n/pio18 gnd pcs1_n/pio17 pcs0_n/pio16 vcc mcs2_n/pio24 mcs3_n/rfsh_n/pio25 gnd res_n tmrin1/pio0 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/pio13 drq0/pio12 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 4. IA188EM IA188EM TQFP Alphabetic Pin Listing Name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17/pio7 a18/pio8 a19/pio9 ale ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ao8 ao9 ao10 ao11 ao12 Pin 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 30 1 3 5 7 9 11 14 17 2 4 6 8 10 ® Name ao13 ao14 ao15 ardy clkouta clkoutb den_n/pio5 drq0/pio12 drq1/pio13 dt/r_n/pio4 gnd gnd gnd gnd gnd gnd gnd hlda hold int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq int4/pio30 lcs_n/once0_n mcs0_n/pio14 mcs1_n/pio15 mcs2_n/pio24 mcs3_n/rfsh_n/pio25 nmi pcs0_n/pio16 pcs1_n/pio17 pcs2_n/pio18 Pin 13 16 18 30 39 40 72 100 99 71 12 35 41 64 65 87 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 Name pcs3_n/pio19 pcs5_n/a1/pio3 pcs6_n/a2/pio2 rd_n res_n rfsh2_n/aden_n rxd/pio28 s0_n s1_n s2_n s6/lock_n/clkdiv2/pio29 sclk/pio20 sdata/pio21 sden0/pio22 sden1/pio23 srdy/pio6 tmrin0/pio11 tmrin1/pio0 tmrout0/pio10 tmrout1/pio1 txd/pio27 ucs_n/once1_n uzi_n/pio26 vcc vcc vcc vcc vcc vcc wb_n wr_n x1 x2 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 146 Pin 85 83 82 29 94 27 22 34 33 32 19 26 23 25 24 69 98 95 97 96 21 80 20 15 38 44 61 84 90 66 28 36 37 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.3 Data Sheet January 25, 2010 TQFP Physical Dimensions The physical dimensions for the TQFP are as shown in Figure 3. Legend: Seating Plane Millimeter Inch Symbol Min Nom Max Min Nom Max A ­ ­ 1.20 ­ ­ 0.047 A1 0.05 ­ 0.15 0.002 ­ 0.006 A2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.17 0.20 0.27 0.007 0.008 0.011 c 0.09 ­ 0.20 0.004 ­ 0.008 D 16.00 BSC. 0.630 BSC. D1 14.00 BSC. 0.551 BSC. D2 12.00 0.472 e 0.50 BSC. 0.02 BSC. E 16.00 BSC. 0.630 BSC. E1 14.00 BSC. 0.551 BSC. E2 12.00 0.472 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF R1 0.08 ­ ­ 0.003 ­ ­ R2 0.08 ­ 0.20 0.003 ­ 0.008 S 0.20 ­ ­ 0.008 ­ ­ 0° 3.5° 7° 0° 3.5° 7° 0° ­ ­ 0° ­ ­ 1 11° 12° 13° 11° 12° 13° 2 11° 12° 13° 11° 12° 13° 3 Tolerances of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 Note: Control dimensions are in millimeters. Figure 3. TQFP Package Dimensions ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.4 Data Sheet January 25, 2010 IA186EM IA186EM PQFP Package sdata/pio21 rxd/pio28 txd/pio27 uzi_n/pio26 s6/clkdiv2_n/pio29 ad15 ad7 ad14 vcc ad6 ad13 gnd ad5 ad12 ad4 ad11 ad3 ad10 ad2 ad9 The pinout for the IA186EM IA186EM PQFP package is as shown in Figure 4. The corresponding pinout is provided in Tables 5 and 6. sden1/pio23 sden0/pio22 sclk/pio20 bhe_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio29 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 ® ® a8 a7 a6 a5 a4 a3 a2 vcc a1 a0 gnd whb_n wlb_n hlda hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 IA186EM IA186EM IA186ES IA186ES PQFP TQFP ad1 ad8 ad0 drq0/pio12 drq1/pio13 tmrin0/pio11 tmrout0/pio10 tmrout1/pio1 tmrin1/pio25 res_n gnd mcs3_n/rfsh_n/pio25 mcs2_n/pio24 vcc pcs0_n/pio16 pcs1_n/pio17 gnd pcs2_n/pio18 pcs3_n/pio19 vcc pcs5_n/a1/pio3 pcs6_n/a2/pio2 lcs_n/once0_n ucs_n/once1_n int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq int4/pio30 mcs1_n/pio15 Figure 4. IA186EM IA186EM PQFP Package Diagram ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 23 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 5. IA186EM IA186EM PQFP Numeric Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name sden1/pio23 sden0/pio22 sclk/pio20 bhe_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio29 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 ® Name a4 a3 a2 vcc a1 a0 gnd whb_n wlb_n hlda hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 mcs1_n/pio15 int4/pio30 int3/inta1_n/irq int2/inta0_n/pio31 int1/select_n int0 ucs_n/once1_n lcs_n/once0_n pcs6_n/a2/pio2 pcs5_n/a1/pio3 vcc pcs3_n/pio19 pcs2_n/pio18 gnd pcs1_n/pio17 pcs0_n/pio16 vcc Pin 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 24 of 146 Name mcs2_n/pio24 mcs3_n/rfsh_n/pio25 gnd res_n tmrin1/pio25 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/pio13 drq0/pio12 ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 gnd ad13 ad6 vcc ad14 ad7 ad15 s6/clkdiv2_n/pio29 uzi_n/pio26 txd/pio27 rxd/pio28 sdata/pio21 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 6. IA186EM IA186EM PQFP Alphabetic Pin Listing Name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17/pio7 a18/pio8 a19/pio9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 Pin 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 88 91 94 79 81 83 85 87 90 ® Name ad14 ad15 ale ardy bhe_n/aden_n clkouta clkoutb den_n/pio5 drq0/pio12 drq1/pio13 dt/r_n/pio4 gnd gnd gnd gnd gnd gnd hlda hold int0 int1/select_n int2/inta0_n/pio31 int3/inta1_n/irq int4/pio30 lcs_n/once0_n mcs0_n/pio14 mcs1_n/pio15 mcs2_n/pio24 mcs3_n/rfsh_n/pio25 nmi pcs0_n/pio16 pcs1_n/pio17 pcs2_n/pio18 Pin 93 95 7 8 4 16 17 49 77 76 48 12 18 41 64 70 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 Name pcs3_n/pio19 pcs5_n/a1/pio3 pcs6_n/a2/pio2 rd_n res_n rxd/pio28 s0_n s1_n s2_n s6/clkdiv2/pio29 sclk/pio20 sdata/pio21 sden0/pio22 sden1/pio23 srdy/pio6 tmrin0/pio11 tmrin1/pio0 tmrout0/pio10 tmrout1/pio1 txd/pio27 ucs_n/once1_n uzi_n/pio26 vcc vcc vcc vcc vcc vcc whb_n wlb_n wr_n x1 x2 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 25 of 146 Pin 62 60 59 6 71 99 11 10 9 96 3 100 2 1 46 75 72 74 73 98 57 97 15 21 38 61 67 92 42 43 5 13 14 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.5 Data Sheet January 25, 2010 IA188EM IA188EM PQFP Package sdata/pio21 rxd/pio28 txd/pio27 uzi_n/pio26 s6/clkdiv2_n/pio29 ao15 ad7 ao14 vcc ad6 ao13 gnd ad5 ao12 ad4 ao11 ad3 ao10 ad2 ao9 The pinout for the IA188EM IA188EM PQFP package is as shown in Figure 5. The corresponding pinout is provided in Tables 7 and 8. sden1/pio23 sden0/pio22 sclk/pio20 rfsh2_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio29 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 ® a8 a7 a6 a5 a4 a3 a2 vcc a1 a0 gnd gnd wb_n hlda hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 IA188EM IA188EM IA186ES IA186ES PQFP TQFP ad1 ao8 ad0 drq0/pio12 drq1/pio13 tmrin0/pio11 tmrout0/pio10 tmrout1/pio1 tmrin1/pio25 res_n gnd mcs3_n/rfsh_n/pio25 mcs2_n/pio24 vcc pcs0_n/pio16 pcs1_n/pio17 gnd pcs2_n/pio18 pcs3_n/pio19 vcc pcs5_n/a1/pio3 pcs6_n/a2/pio2 lcs_n/once0_n ucs_n/once1_n int0 int1/select_n int2/inta0_n/pwd/pio31 int3/inta1_n/irq int4/pio30 mcs1_n/pio15 Figure 5. IA188EM IA188EM PQFP Package Diagram ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 26 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 7. IA188EM IA188EM PQFP Numeric Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name sden1/pio23 sden0/pio22 sclk/pio20 rfsh2_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd x1 x2 vcc clkouta clkoutb gnd a19/pio29 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 ® Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Name a4 a3 a2 vcc a1 a0 gnd gnd wb_n hlda hold srdy/pio6 nmi dt/r_n/pio4 den_n/pio5 mcs0_n/pio14 mcs1_n/pio15 int4/pio30 int3/inta1_n/irq int2/inta0_n/pwd/pio31 int1/select_n int0 ucs_n/once1_n lcs_n/once0_n pcs6_n/a2/pio2 pcs5_n/a1/pio3 vcc pcs3_n/pio19 pcs2_n/pio18 gnd pcs1_n/pio17 pcs0_n/pio16 vcc Pin 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 27 of 146 Name mcs2_n/pio24 mcs3_n/rfsh_n/pio25 gnd res_n tmrin1/pio25 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/pio13 drq0/pio12 ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 s6/clkdiv2_n/pio29 uzi_n/pio26 txd/pio27 rxd/pio28 sdata/pio21 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Table 8. IA188EM IA188EM PQFP Alphabetic Pin Listing Name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17/pio7 a18/pio8 a19/pio9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ale ao8 ao9 ao10 ao11 ao12 Pin 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 88 91 94 7 79 81 83 85 87 Name ao13 ao14 ao15 ardy clkouta clkoutb den_n/ds_n/pio5 drq0/pio12 drq1/pio13 dt/r_n/pio4 gnd gnd gnd gnd gnd gnd gnd hlda hold int0 int1/select_n int2/inta0_n/pwd/pio31 int3/inta1_n/irq int4/pio30 lcs_n/once0_n mcs0_n/pio14 mcs1_n/pio15 mcs2_n/pio24 mcs3_n/rfsh_n/pio25 nmi pcs0_n/pio16 pcs1_n/pio17 pcs2_n/cts1_n/enrx1_n/pio18 ® Pin 90 93 95 8 16 17 49 77 76 48 12 18 41 42 64 70 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 Name pcs3_n/rts1_n/rtr1_n/pio19 pcs5_n/a1/pio3 pcs6_n/a2/pio2 rd_n res_n rfsh2_n/aden_n rxd/pio28 s0_n s1_n s2_n s6/lock_n/clkdiv2/pio29 sclk/pio20 sdata/pio21 sden0/pio22 sden1/pio23 srdy/pio6 tmrin0/pio11 tmrin1/pio0 tmrout0/pio10 tmrout1/pio1 txd/pio27 ucs_n/once1_n uzi_n/pio26 vcc vcc vcc vcc vcc vcc wb_n wr_n x1 x2 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 28 of 146 Pin 62 60 59 6 71 4 99 11 10 9 96 3 100 2 1 46 75 72 74 73 98 57 97 15 21 38 61 67 92 42 5 13 14 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.1.6 Data Sheet January 25, 2010 PQFP Physical Dimensions The physical dimensions for the PQFP are as shown in Figure 6. Legend Millimeter Symbol Min Nom Max A ­ ­ 3.40 A1 0.25 ­ ­ A2 2.73 2.85 2.97 B 0.25 0.30 0.38 B1 0.22 0.30 0.33 C 0.13 0.15 0.23 C1 0.11 0.15 0.17 D 23.00 23.20 23.40 D1 19.90 20.00 20.10 E 17.00 17.20 17.40 E1 13.90 14.00 14.10 0.65 BSC. e L 0.73 0.88 1.03 L1 1.60 BSC. R1 0.13 ­ ­ R2 0.13 ­ 0.30 S 0.20 ­ ­ Y ­ ­ 0.10 ­ 0 7 1 ­ ­ 0 2 9 10 11 3 9 10 11 Pin 1 Indicator See Detail B See Detail A 9 9 10 10 Detail B Figure 6. PQFP Package Dimensions ® 11 11 Notes: 1. Dimensions D1 and E1 do not include mold protrusion, but mold mismatch is included. Allowable protrusion is 0.25mm/0.010 per side. 2. Dimension B does not include Dambar protrusion. Allowable protrusion is 0.08mm/0.003 total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 3. Controlling dimension: millimeter. PLATING Detail A Inch Min Nom Max ­ ­ 0.134 0.010 ­ ­ 0.107 0.112 0.117 0.010 0.012 0.015 0.009 0.012 0.013 0.005 0.006 0.009 0.004 0.006 0.007 0.906 0.913 0.921 0.783 0.787 0.791 0.669 0.677 0.685 0.547 0.551 0.555 0.026 BSC. 0.029 0.035 0.041 0.063 BSC. 0.005 ­ ­ 0.005 ­ 0.012 0.008 ­ ­ ­ ­ 0.004 ­ 0 7 ­ ­ 0 IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 29 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.2 2.2.1 Data Sheet January 25, 2010 Pin Descriptions a19/pio9, a18/pio8, a17/pio7, a16­a0-Address Bus (synchronous outputs with tristate) These pins are the system's source of non-multiplexed I/O or memory addresses and occur a half clkouta cycle before the multiplexed address/data bus (ad15­ad0 for the IA186EM IA186EM or ao15­ao8 and ad7­ad0 for the IA188EM IA188EM). The address bus is tristated during a bus hold or reset. 2.2.2 ad15­ad8 (IA186EM IA186EM)-Address/data bus (level-sensitive synchronous inouts with tristate) These pins are the system's source of time-multiplexed I/O or memory addresses and data. The address function of these pins can be disabled (see bhe_n/aden_n pin description). If the address function of these pins is enabled, the address will be present on this bus during t1 of the bus cycle and data will be present during t2, t3, and t4 of the same bus cycle. If whb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle. The address/data bus is tristated during a bus hold or reset. These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h) with configuration data during a power-on reset (POR). 2.2.3 ad7­ad0-Address/Data bus (level-sensitive synchronous inouts with tristate) These pins are the system's source of time-multiplexed low-order byte of the addresses for I/O or memory and 8-bit data. The low-order address byte will be present on this bus during t1 of the bus cycle and the 8-bit data will be present during t2, t3, and t4 of the same bus cycle. The address function of these pins can be disabled (see bhe_n/aden_n pin description). If wlb_n (IA186EM IA186EM) is not active, these pins are tristated during t2, t3, and t4 of the bus cycle. The address/data bus is tristated during a bus hold or reset. 2.2.4 ao15­ao8 (IA188EM IA188EM)-Address-only bus (level-sensitive synchronous outputs with tristate) The address-only bus will contain valid high-order address bits during the bus cycle (t1, t2, t3, and t4) if the bus is enabled. These pins are combined with ad7­ad0 to complete the multiplexed address bus and are tristated during a bus hold or reset condition. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 30 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 2.2.5 Data Sheet January 25, 2010 ale-Address Latch Enable (synchronous output) This signal indicates the presence of an address on the address bus (ad15­ad0 for the IA186EM IA186EM or ao15­ao8 and ad7­ad0 for the IA188EM IA188EM), which is guaranteed to be valid on the falling edge of ale. 2.2.6 ardy-Asynchronous Ready (level-sensitive asynchronous input) This asynchronous signal provides an indication to the microcontroller that the addressed I/O device or memory space will complete a data transfer. This active high signal is asynchronous with respect to clkouta and if the falling edge of ardy is not synchronized to clkouta, an additional clock cycle may be added Signal ardy should be tied high to maintain a permanent assertion of the ready condition. On the other hand, if the ardy signal is not used by the system it should be tied low, which passes control to the srdy signal. 2.2.7 bhe_n/aden_n (IA186EM IA186EM)-Bus High Enable (synchronous output with tristate)/Address Enable (input with internal pull-up) The bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower, or both) are involved in the current memory access bus cycle as shown Table 9. Table 9. Bus Cycle Types for bhe_n and ad0 bhe_n 0 0 1 1 ad0 0 1 0 1 Type of Bus Cycle Word Transfer High-Byte Transfer (Bits [15­8]) Low-Byte Transfer (Bits [7­0]) Refresh The bhe_n does not require latching and during bus hold and reset is tristated. It is asserted during t1 and remains so through t3 and tw. The high- and low-byte write enable functions of bhe_n and ad0 are performed by whb_n and wlb_n, respectively. When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0 both being high. During refresh cycles the a and ad busses may not have the same address during the address phase of the ad bus cycle necessitating the use of ad0 as a determinant for the refresh cycle rather than a0. An additional signal is used for Pseudo-Static RAM (PSRAM) refreshes (see mcs3_n/rfsh_n pin description). There is a weak internal pull-up on bhe_n/aden_n obviating the need for an external pull-up and reducing power consumption. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 31 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 Holding aden_n high or letting it float during POR passes control of the address function of the ad bus (ad15­ad0) during LCS and UCS bus cycles from aden_n to the Disable Address (DA) bit in Low-Memory Chip Select (LMCS) and Upper Memory Chip Select (UMCS) registers. When the address function is selected, the memory address is placed on the a19­a0 pins. Holding aden_n low during POR, both the address and data are driven onto the ad bus independently of the DA bit setting. This pin is normally sampled one clock cycle after the rising edge of res_n. 2.2.8 clkouta-Clock Output A (synchronous output) This pin is the internal clock output to the system. Bits [9­8] and Bits [2­0] of the Power-Save Control register (PDCON) control the output of this pin, which may be tristated, output the crystal input frequency (x1), or output the power save frequency (internal processor frequency after divisor). The clkouta can be used as a full-speed clock source in power-save mode. The AC timing specifications that are clock-related refer to clkouta, which remains active during reset and hold conditions. 2.2.9 clkoutb-Clock Output B (synchronous output) This pin is an additional clock output to the system. Bits [11­10] and [2­0] of the Power-Save Control register (PDCON) control the output of this pin, which may be tristated, output the PLL frequency, or may output the power-save frequency (internal processor frequency after divisor). The clkoutb remains active during reset and hold conditions. 2.2.10 den_n/pio5-Data Enable Strobe (synchronous output with tristate) This pin provides an output enable to an external bus data bus transmitter or receiver. This signal is asserted during I/O, memory, and interrupt acknowledge processes and is deasserted when dt/r_n undergoes a change of state. It is tristated for a bus hold or reset. 2.2.11 drq1/pio12­drq0/pio13-DMA Requests (synchronous level-sensitive inputs) An external device that is ready for DMA channel 1 or 0 to carry out a transfer indicates to the microcontroller this readiness on these pins. They are level triggered, internally synchronized, not latched, and must remain asserted until dealt with. 2.2.12 dt/r_n/pio4-Data Transmit or Receive (synchronous output with tristate) The microcontroller transmits data when dt/r_n is pulled high and receives data when this pin is pulled low. It floats during a reset or bus hold condition. 2.2.13 gnd-Ground Six or seven pins, depending on package, connect the microcontroller to the system ground. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 32 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.14 hlda-Bus Hold Acknowledge (synchronous output) This pin is pulled high to signal the system that the microcontroller has ceded control of the local bus, in response to a high on the hold signal by an external bus master, after the microcontroller has completed the current bus cycle. The assertion of hlda is accompanied by the tristating of den_n, rd_n, wr_n, s2_n­s0_n, ad15­ad0, s6, a19­a0, bhe_n, whb_n, wlb_n, and dt/r_n, followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n­mcs0_n, pcs6_n­pcs5_n, and pcs3_n­pcs0_n. The external bus master releases control of the local bus by the deassertion of hold that in turn induces the microcontroller to deassert the hlda. The microcontroller can take control of the bus if necessary (to execute a refresh for example), by deasserting hlda without the bus master first deasserting hold. This requires that the external bus master be able to deassert hold to permit the microcontroller to access the bus. 2.2.15 hold-Bus Hold Request (synchronous level-sensitive input) This pin is pulled high to signal the microcontroller that the system requires control of the local bus. The hold latency time (time between the hold and hlda) depends on the current processor activity when the hold is received. A hold request is second only to a DMA refresh request in priority of processor activity requests. If a hold request is received at the moment a DMA transfer starts, the hold latency can be up to 4 bus cycles. (This happens only on the IA186EM IA186EM when a word transfer is taking place from an odd to an odd address.) This means that the latency may be 16 clock cycles without wait states. Furthermore, if lock transfers are being performed, then the latency time is increased during the locked transfer. 2.2.16 int0-Maskable Interrupt Request 0 (asynchronous input) The int0 pin provides an indication that an interrupt request has occurred, and provided that int0 is not masked, program execution will continue at the location specified by the INT0 vector in the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. 2.2.17 int1/select_n-Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs) The int1 pin provides an indication that an interrupt request has occurred, and provided that int1 is not masked, program execution will continue at the location specified by the int1 vector in the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 33 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 The select_n pin provides an indication to the microcontroller that an interrupt type has been placed on the address/data bus when the internal Interrupt Control Unit is slaved to an external interrupt controller. Before this can occur, however, the int0 pin must have already indicated an interrupt request has occurred. 2.2.18 int2/inta0_n/pio31-Maskable Interrupt Request 2 (asynchronous input)/Interrupt Acknowledge 0 (synchronous output) The int2 pin provides an indication that an interrupt request has occurred, and provided that int2 is not masked, program execution will continue at the location specified by the int2 vector in the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. When int0 is configured to be in cascade mode, int2 changes its function to inta0_n. The inta0_n function indicates to the system that the microcontroller requires an interrupt type in response to the interrupt request int0 when the microcontroller's Interrupt Control Unit is in cascade mode. The peripheral device that issued the interrupt must provide the interrupt type. 2.2.19 int3/inta1_n/irq-Maskable Interrupt Request 3 (asynchronous input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt Acknowledge (synchronous output) The int3 pin provides an indication that an interrupt request has occurred. If int3 is not masked, program execution will continue at the location specified by the int3 vector in the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. When int1 is configured to be in cascade mode, int3 changes its function to inta1_n. The inta1_n function indicates to the system that the microcontroller requires an interrupt type in response to the interrupt request int1 when the microcontroller's Interrupt Control Unit is in cascade mode. The peripheral device that issued the interrupt must provide the interrupt type. The signal on irq allows the microcontroller to output an interrupt request to the external master interrupt controller when the Interrupt Control Unit of the microcontroller is in slave mode. 2.2.20 int4/pio30-Maskable Interrupt Request 4 (asynchronous input) The int4 pin provides an indication that an interrupt request has occurred, and provided that int4 is not masked, program execution will continue at the location specified by the int4 vector in the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 34 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.21 lcs_n/once0_n-Lower Memory Chip Select (synchronous output with internal pull-up)/ONCE Mode Request (input) The lcs_n pin provides an indication that a memory access is occurring to the lower memory block. The size of the Lower Memory Block and its base address are programmable, with the size adjustable up to 512 Kbytes. The lcs_n is held high during bus hold. The once0_n pin (ONCE ­ ON Circuit Emulation) and its companion pin, once1_n, define the microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode, all pins are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only present during reset. This pin is not tristated during bus hold. 2.2.22 mcs2_n-mcs0_n (no pio, pio15, pio 14)-Midrange Memory Chip Selects (synchronous outputs with internal pull-up) The mcs2_n and mcs0_n pins provide an indication that a memory access is in progress to the second or third midrange memory block. The size of the Midrange Memory Block and its base address are programmable. The mcs2_n ­ mcs0_n are held high during bus hold and have weak pull-ups that are only present during reset. 2.2.23 mcs3_n/rfsh_n (pio25)-Midrange Memory Chip Select (synchronous output with internal pull-up)/Automatic Refresh (synchronous output) The mcs3_n pin provides an indication that a memory access is in progress to the fourth region of the midrange memory block. The size of the Midrange Memory Block and its base address are programmable. The mcs3_n is held high during bus hold and has a weak pull-up that is present only during reset. The rfsh_n signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is output only when the PSRAM or DRAM mode bit is set (EDRAM register Bit [15]). This pulse is of 1.5 clock-pulse duration with the rest of the refresh cycle made up of a deassertion period such that the overall refresh time is met. This pin is not tristated during a bus hold. 2.2.24 nmi-Nonmaskable Interrupt (synchronous edge-sensitive input) Unlike int4 ­ int0, this is the highest priority interrupt signal and cannot be masked. Upon the assertion of this interrupt (transition from Low to High), program execution is transferred to the nonmaskable interrupt vector in the interrupt vector table and this interrupt is initiated at the next instruction boundary. For recognition to be assured, the nmi pin must be held high for at least a clkouta period so that the transition from low to high is latched and synchronized internally. The interrupt will begin at the next instruction boundary. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 35 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 The nmi is not involved in the priority resolution process that deals with the maskable interrupts and does not have an associated interrupt flag. This allows for a new nmi request to interrupt an nmi service routine that is already underway. When an interrupt is taken by the processor the interrupt flag IF is cleared, disabling the maskable interrupts. If the maskable interrupts are reenabled during the nmi service routine (e.g., by use of STI instruction), the priority resolution of maskable interrupts will be unaffected by the servicing of the non-maskable interrupt (NMI). Note: For this reason, it is strongly recommended that the NMI interrupt service routine does not enable the maskable interrupts. 2.2.25 pcs3_n­pcs0_n (pio19­pio16)-Peripheral Chip Selects 3­0 (synchronous outputs) The pcs3_n­pcs0_n pins provide an indication that a memory access is underway for the corresponding region of the peripheral memory block (I/O or memory address space). The base address of the peripheral memory block is programmable. The pins are held high during both bus hold and reset. These outputs are asserted with the ad address bus over a 256-byte range each. 2.2.26 pcs5_n/a1-Peripheral Chip Select 5 (synchronous output)/Latched Address Bit 1 (synchronous output) The pcs5_n signal provides an indication that a memory access is underway for the sixth region of the peripheral memory block (I/O or memory address space). The base address of the peripheral memory block is programmable. The pcs5_n is held high during both bus hold and reset. This output is asserted with the ad address bus over a 256-byte range. This a1 pin provides an internally latched address bit 1 to the system when the EX bit (Bit [7]) in the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus hold. 2.2.27 pcs6_n/a2-Peripheral Chip Select 6 (synchronous output)/latched Address Bit 2 (synchronous output) The pcs6_n signal provides an indication that a memory access is underway for the seventh region of the peripheral memory block (I/O or memory address space). The base address of the peripheral memory block is programmable. The pcs6_n is held high during both bus hold and reset. This output is asserted with the ad address bus over a 256-byte range. The a2 pin provides an internally latched address Bit [2] to the system when the EX bit (Bit [7]) in the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus hold. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 36 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.28 pio31­pio0-Programmable I/O Pins (asynchronous input/output open-drain) There are 32 individually programmable I/O pins provided (see Table 15, Default Status of PIO Pins at Reset). 2.2.29 rd_n-Read strobe (synchronous output with tristate) The rd_n pin provides an indication to the system that a memory or I/O read cycle is underway. It will not to be asserted before the ad bus is floated during the address to data transition. The rd_n is tristated during bus hold. 2.2.30 res_n-Reset (asynchronous level-sensitive input) The res_n pin forces a reset on the microcontroller. Its Schmitt trigger allows POR generation via an RC network. When this signal is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h. The res_n must be asserted for at least 1 ms. Because it is synchronized internally it may be asserted asynchronously to clkouta. Furthermore, vcc must be within specification and clkouta must be stable for more than four of its clock periods for the period that res_n is asserted. The microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of res_n. 2.2.31 rfsh2_n/aden_n (IA188EM IA188EM)-Refresh 2 (synchronous output with tristate)/Address Enable (input with internal pull-up) The rfsh2_n indicates that a DRAM refresh cycle is being performed when it is asserted low. However, this is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead. If the aden_n pin is held high during POR, the ad bus (ao15­ao8 and ad7­ad0 for the IA188EM IA188EM) is controlled during the address portion of the lcs and ucs bus cycles by the DA bit (Bit [7]) in the lcs and ucs registers. If the DA bit is 1, the address is accessed on the a19­a0 pins, reducing power consumption. The weak pull-up on this pin obviates the necessity of an external pull-up. If the aden_n pin is held low during POR, the ad bus is used for both addresses and data without regard for the setting of the DA bits. The rfsh2_n/aden_n is sampled one crystal clock cycle after the rising edge of res_n and is tristated during bus holds and ONCE mode. 2.2.32 rxd/pio28-Receive Data (asynchronous input) This signal connects asynchronous serial receive data from the system to the asynchronous serial port. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 37 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.33 s2_n­s0_n-Bus Cycle Status (synchronous outputs with tristate) These three signals inform the system of the type of bus cycle in progress. The s2_n may be used to indicate whether the current access is to memory or I/O, and s1_n may be used to indicate whether data is being transmitted or received. These signals are tristated during bus hold and hold acknowledge. The coding for these pins is presented in Table 10. Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n s2_n 0 0 0 0 1 1 1 1 s1_n 0 0 1 1 0 0 1 1 s0_n 0 1 0 1 0 1 0 1 Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory None (passive) 2.2.34 s6/clkdiv2_n/pio29-Bus Cycle Status Bit 6 (synchronous output)/Clock Divide by 2 (input with internal pull-up) The s6 signal is high during the second and remaining cycle periods (i.e., t2 ­ t4), indicating that a DMA-initiated bus cycle is underway. The s6 is tristated during bus hold or reset. If the clkdiv2_n signal is held low during power-on-reset, the microcontroller enters clock divide-by-2 mode. In this mode, the PLL is disabled and the processor receives the external clock divided by 2. Sampling of this pin occurs on the rising edge of res_n. Note: If this pin is used as pio29 and configured as an input, care should be taken that it is not driven low during POR. Because this pin has an internal pull-up, it is not necessary to drive the pin high even though it defaults to an input PIO. 2.2.35 sclk-Serial Clock (synchronous outputs with tristate) Because this pin provides a slave device with a synchronous serial clock it permits synchronization of the transmit and receive data exchanges between the slave and the microcontroller. The sclk is the result of dividing the internal clock by 2, 4, 8, or 16, depending on the contents of the Synchronous Serial Control (SSC) register Bits [5­4]. Accessing either the SSR or SSD registers activates the sclk for eight cycles. When sclk is not active, the microcontroller hold is high. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 38 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.36 sdata-Serial Data (synchronous inout) The sdata pin connects a slave device to synchronous serial transmit and receive data. The last value is retained on this pin when it is inactive. 2.2.37 sden1­sden0-Serial Data Enables (synchronous outputs with tristate) The sden1­sden0 pins facilitate the transfer of data on ports 1 and 0 of the Synchronous Serial Interface (SSI). Either sden1 or sden0 is asserted by the microcontroller at the start of the data transfer and is de-asserted when the transfer is completed. These pins are held low by the microcontroller when they are inactive. 2.2.38 srdy/pio6-Synchronous Ready (synchronous level-sensitive input) This signal is an active high input synchronized to clkouta and indicates to the microcontroller that a data transfer will be completed by the addressed memory space or I/O device. In contrast to the Asynchronous Ready (ardy), which requires internal synchronization, srdy permits easier system timing because it already synchronized. Tying srdy high will always assert this ready condition. Tying it low will give control to ardy. 2.2.39 tmrin0/pio11-Timer Input 0 (synchronous edge-sensitive input) This signal may be either a clock or control signal for the internal Timer 0. The timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin0. When not used, tmrin0 must be tied high, or when used as pio11, it is pulled up internally. 2.2.40 tmrin1/pio0-Timer Input 1 (synchronous edge-sensitive input) This signal may be either a clock or control signal for the internal Timer 1. The timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin1. When not used, tmrin1 must be tied high, or when used as pio0, it is pulled up internally. 2.2.41 tmrout0/pio10-Timer Output 0 (synchronous output) This signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. It is tristated during a bus hold or reset. 2.2.42 tmrout1/pio1-Timer Output 1 (synchronous output) This signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. It is tristated during a bus hold or reset. 2.2.43 txd/pio22-Transmit Data (asynchronous output) This pin provides the system with asynchronous serial transmit data from the serial port. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 39 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 2.2.44 ucs_n/once1_n-Upper Memory Chip Select (synchronous output)/ONCE Mode Request 1 (input with internal pull-up) The ucs_n pin provides an indication that a memory access is in progress to the upper memory block. The size of the Upper Memory Block and its base address are programmable, with the size adjustable to 512 Kbytes. The ucs_n is held high during bus hold. After power-on-reset, ucs_n is active low and program execution begins at FFFF0h. Its default configuration is a 64-Kbyte memory range from F0000h to FFFFFh. The once0_n pin (ONCE ­ ON Circuit Emulation) and its companion pin, once1_n, define the microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode, all pins are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only present during reset. This pin is not tristated during bus hold. 2.2.45 uzi_n/pio26-Upper Zero Indicate (synchronous output) This pin allows the designer to determine if an access to the interrupt vector table is in progress by ORing it with Bits [15­10] of the address and data bus (ad15­ad10 on the IA186EM IA186EM and ao15­ao10 on the IA188EM IA188EM). The uzi_n is the logical OR of the inverted a19­a16 bits. It asserts in the first period of a bus cycle and is held throughout the cycle. At reset, uzi_n should be pulled high or allowed to float. If this pin is pulled low at reset, the microcontroller enters a reserved clock test mode. 2.2.46 vcc-Power Supply (input) These pins supply power (+5V) to the microcontroller. 2.2.47 whb_n (IA186EM IA186EM)-Write High Byte (synchronous output with tristate) The whb_n and wlb_n pins indicate to the system which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. The whb_n is asserted with ad15­ad8 and is the logical OR of bhe_n and wr_n. It is tristated during reset. 2.2.48 wlb_n/wb_n-Write Low Byte (IA186EM IA186EM) (synchronous output with tristate)/Write Byte (IA188EM IA188EM) (synchronous output with tristate) The wlb_n and whb_n pins indicate to the system which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. The wlb_n is asserted with ad7­ad0 and is the logical OR of ad0 and wr_n. It is tristated during reset. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 40 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers Data Sheet January 25, 2010 On the IA188EM IA188EM microcontroller, wb_n provides an indication that a write to the bus is occurring. It shares the same early timing as that of the non-multiplexed address bus, and is associated with ad7­ad0. It is tristated during reset. 2.2.49 wr_n-Write Strobe (synchronous output) The wr_n pin indicates to the system that the data currently on the bus is to be written to a memory or I/O device. It is tristated during a bus hold or reset. 2.2.50 x1-Crystal Input (input) The x1 and x2 pins are the connections for a fundamental-mode or third-overtone, parallelresonant crystal used by the internal oscillator circuit. An external clock source for the microcontroller is connected to x1. The x2 is left unconnected. 2.2.51 x2-Crystal Input (input) The x1 and x2 pins are the connections for a fundamental-mode or third-overtone, parallelresonant crystal used by the internal oscillator circuit. An external clock source for the microcontroller is connected to x1. The x2 is left unconnected. 2.3 Pins Used by Emulators The following pins are used by emulators: a19­a0 ao15­ao8 (on the IA188EM IA188EM) ad7­ad0 ale bhe_n/aden_n (on the IA186EM IA186EM) clkouta rfsh2_n/aden_n (on the IA188EM IA188EM) rd_n s2_n­s0_n s6/lock_n/clkdiv2_n uzi_n Emulators require that s6/lock_n/clkdiv2_n and uzi_n be configured as their normal functions (i.e., as s6 and uzi_n, respectively). Holding bhe_n/aden_n (IA186EM IA186EM) or rfsh_n/aden_n (IA188EM IA188EM) low during the rising edge of res_n, will cause s6 and uzi_n to be configured in their normal functions at reset instead of as PIOs. ® IA211050831-18 IA211050831-18 UNCONTROLLED WHEN PRINTED OR COPIED Page 41 of 146 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186EM/IA188EM IA186EM/IA188EM 8-Bit/16-Bit Microcontrollers 3. Data Sheet January 25, 2010 Maximum Ratings, Thermal Characteristics, and DC Parameters The absolute maximum ratings, thermal characteristics, and DC parameters are provided in Tables 11 through 13, respectively. Table 11. IA186EM IA186EM and IA188EM IA188EM Absolute Maximum Ratings Parameter Storage Temperature Voltage on any Pin with Respect to vss Rating -65°C to +125°C -0.5V to +(vcc + 0.5) V Table 12. IA186EM IA186EM and IA188EM IA188EM Thermal Characteristics Symbol TA Characteristic Ambient Temperature Value -40°C to 85°C Table 13. DC Characteristics Over Commercial Operating Ranges Symbol VCC VIL VIL1 VIH VIH1 VIH2 VOL Parameter Description Supply Voltage (@ 5V Operation) Input Low Voltage (Except x1) Clock Input Low Voltage (x1) Input High Voltage (Except res_n and x1) Input High Voltage (res_n) Clock Input High Voltage (x1) Output Low Voltages VOH Output High Voltagesa ICC Power Supply Current @ 0 C ILI Input Leakage Current @ 0.5 MHz Output Leakage Current @ 0.5 MHz Clock Output Low Clock Output High ILO VCLO VCHO Test Conditions ­ ­ ­ Min 4.5 -0.5 -0.5 2.0 ­ 2.4 ­ vcc­0.8 IOL = 2.5 mA (s2_n­s0_n) ­ IOL = 2.0 mA (other) ­ IOH = -2.4 mA @ 2.4 V 2.4 IOH = -200 A @ vcc -0.5 vcc -0.5 ­ vcc = 5.5 Vb 0.45 V VIN 0.45 V vcc VOUT vcc c ICLO = 4.0 mA ICHO = -500 A Max 5.5 0.8 0.8 vcc +0.5 Unit V V V V vcc +0.5 vcc +0.5 0.45 0.45 vcc +0.5 vcc 5.9 ­ 10 V V V V V V mA/ MHz A ­ 10 A ­ vcc -0.5 0.45 ­ V V aThe lcs_n/once0_n, mcs3_n­mcs0_n, ucs_n/once1_n, and rd_n pins have weak internal pullup resistors. Loading the lcs_n/once0_n and ucs_n/once1_n pins in excess of IOH = -200 A during reset can cause the device to go into ONCE mode. bCurrent is measured with the device in reset with the x1 and x2 driven and all other non-power pins open but held high or low. cTesting is performed with th