NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: _COMPARATOR. MONOI TTHIC SILICON SIZE I CODE IDENT. NO. a 14933 DWG NO. 5962-87516 REV PAGE OF T , as specified in MIL-M-38510 MIL-M-38510 and herein. 3.2.1 Terminal connections. The terminal connections shall , DESC FORM 193A FEB 86 This Material Copyrighted By Its Respective Manufacturer TAULE I. Electrical , -4.5 V TA = +25 C XT 7.5 "IT I IB V+ = +5.5 V V- = -5.5 V TA = +25°C XT 20 TO" mV mr nA , +4.5 V V- = -4.5 V 1. 2, 3 2.0 Input current high 1G or 2G strobe Common strobe S IlH V+ = +5.5 V ... | OCR Scan |
9 pages, |
5962-8751601 521/BCA 5962-8751601dx 5962-8751601CX datasheet abstract |
|
|||
| Abstract: 47 470 560 561 1.800 182 ±20% M Capacitance tolerance M=±20% K=±10% 400V 2G Rated voltage Example: Terminal type 22 0X3OL 2230 Case size Ì Example: WV Symbol 200 2D 250 2E 400 2G 0D*L Code , Current (at 20*0 I = 0.02CV or 1.5 ìnA whichever is smaller (after 5 minutes) Where. C ~ rated , *35 2.90 1.000 25*50 2.96 30*35 3.00 35*30 2.96 30*45 3.31 35*35 3.21 1,200 30*40 3.44 35 , jiF 400 (2G) 450V (2W) 220 250 300 350 220 250 300 350 47 22*25 0.62 ... | OCR Scan |
2 pages, |
datasheet abstract |
|
|||
| Abstract: otherwise specified 1- I IB" . 0.0 V I 2G « 3.0 V Data . 3.0 V Group A subgroups Limits "Min" "flax" Unit Supply current !CCH VCC - +5.5 V !CCL rCCZ 1. 2. 3 T I IE » 0.0 V I 2G . 3.0 V I Data . 0.0 V 1. 2, 3 I 15 » 3.0 V I 2G . 0.0 V I Data . 0.0 V 1. 2, 3 65 105 120 mA mA Functional , Oafana« TITLE: MICROCIRCUIT, DIGITAL, BIPOLAR, OCTAL BUFFER, MONOLITHIC SILICON SIZE I COOK IDENT. NO. , following example: 5962-86725 01 R X I Drawing number I Device type (1.2.1) I case outline (1.2.2 ... | OCR Scan |
12 pages, |
5962-8672501RX datasheet abstract |
|
|||
| Abstract: (at 20) Performance -40 ~ +85 ±20% (at 120Hz, 20) I = 3 CV or 1.5 mA whichever is smaller , 2.58 35Ã-30 2.54 30Ã-40 2.92 35Ã-35 2.90 30Ã-45 3.31 35Ã-35 3.21 2.62 , DC 400 (2G) D uF 25 22Ã-20 22Ã-25 180 220 LS2 22 25 450V (2W) 30 35 , 101 M 2G Series name Capacitance Capacitance tolerance Example: Cap. Symbol 56 , voltage Terminal type Terminal length Case size Example: WV Symbol 400 2G 450 2W ... | Original |
2 pages, |
datasheet abstract |
|
|||
| Abstract: ) 600ms, 30ms, 20ms/230VAC; 1.2s, 30ms, 20ms/115VAC PF>0.95/230VAC 95/230VAC, PF>0.98/115VAC 98/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG , PFC Circuit EMI Filter & Rectifiers I/P FG Power Switching O.L.P. Rectifiers & , 52±0.5 62±1 CN2 CN1 FG AC/N AC/L F4A/250V F4A/250V 1 +V Adj. 8 4- ¿3 ... | Original |
2 pages, |
svh-21t-1.1 VLPP-100-13 VLPP-100-13 abstract |
|
|||
| Abstract: ) 600ms, 30ms, 20ms/230VAC; 1.2s, 30ms, 20ms/115VAC PF>0.95/230VAC 95/230VAC, PF>0.98/115VAC 98/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG , Circuit EMI Filter & Rectifiers I/P FG Power Switching O.L.P. Rectifiers & Filter , CN1 FG AC/N AC/L F4A/250V F4A/250V 1 +V Adj. 8 4- ¿3 ... | Original |
2 pages, |
VLPP-100-15 svh-21t-1.1 VLPP-100-15 abstract |
|
|||
| Abstract: -±0.05% / °C (0~50°C) 800ms, 50ms, 20ms/230VAC 1.2s, 50ms, 20ms/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG, O/P-FG , Single Output with PFC Function Block Diagram 115/230VAC 115/230VAC Auto Switch EMI Filter I/P , ¿3 32±1 ... | Original |
2 pages, |
VLPS-100-24 VLPS-100-24 abstract |
|
|||
| Abstract: ) 800ms, 50ms, 20ms/230VAC 1.2s, 50ms, 20ms/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG, O/P-FG:500VDC 500VDC / 100M Ohms , Single Output with PFC Function Block Diagram 115/230VAC 115/230VAC Auto Switch EMI Filter I/P , ¿3 32±1 ... | Original |
2 pages, |
VLPS-100-48 VLPS-100-48 abstract |
|
|||
| Abstract: (0~50°C) 800ms, 50ms, 20ms/230VAC 1.2s, 50ms, 20ms/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG, O/P-FG:500VDC 500VDC , Single Output with PFC Function Block Diagram 115/230VAC 115/230VAC Auto Switch EMI Filter I/P , ¿3 32±1 ... | Original |
2 pages, |
VLPS-100-3 VLPS-100-3 abstract |
|
|||
| Abstract: ) 600ms, 30ms, 20ms/230VAC; 1.2s, 30ms, 20ms/115VAC PF>0.95/230VAC 95/230VAC, PF>0.98/115VAC 98/115VAC 10~500Hz, 2G 10min./1cycle (1 hour each axes) I/P-O/P: 3KVAC, I/P-FG: 1.5KVAC, O/P-FG: 0.5KVAC, for 1 min. I/P-O/P, I/P-FG , Circuit EMI Filter & Rectifiers I/P FG Power Switching O.L.P. Rectifiers & Filter , CN1 FG AC/N AC/L F4A/250V F4A/250V 1 +V Adj. 8 4- ¿3 ... | Original |
2 pages, |
VLPP-100-5 VLPP-100-5 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| Editblk NC Base FG Config F4:F4I G2: G3: CIN: COUT: X: Y: XQ: YQ:QY FFX:RESET FFY:K:SR:SET DX: DY 327 Editblk NB Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F Editblk ND Base FG Config F4: G2:G2I G3:G3I CIN: COUT: X:F Y: XQ:QX YQ: FFX:K:SR:RESET FFY:RESET DX:H DY : Equate F = (F2*~F3*F1) Endblk Nameblk MC n325 Editblk MC Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y +~(F2*F1)+F4) Endblk Nameblk LD n323 Editblk LD Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/state_ma/binary.odf |
Xilinx | 01/06/1995 | 9.66 Kb | ODF | binary.odf |
| Editblk NC Base FG Config F4:F4I G2: G3: CIN: COUT: X: Y: XQ: YQ:QY FFX:RESET FFY:K:SR:SET DX: DY 327 Editblk NB Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F Editblk ND Base FG Config F4: G2:G2I G3:G3I CIN: COUT: X:F Y: XQ:QX YQ: FFX:K:SR:RESET FFY:RESET DX:H DY : Equate F = (F2*~F3*F1) Endblk Nameblk MC n325 Editblk MC Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y +~(F2*F1)+F4) Endblk Nameblk LD n323 Editblk LD Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ www.datasheetarchive.com/download/61635476-996530ZC/xsi_vhdl.tar |
Xilinx | 09/04/1997 | 12384 Kb | TAR | xsi_vhdl.tar |
| Editblk NC Base FG Config F4:F4I G2: G3: CIN: COUT: X: Y: XQ: YQ:QY FFX:RESET FFY:K:SR:SET DX: DY 327 Editblk NB Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F Editblk ND Base FG Config F4: G2:G2I G3:G3I CIN: COUT: X:F Y: XQ:QX YQ: FFX:K:SR:RESET FFY:RESET DX:H DY : Equate F = (F2*~F3*F1) Endblk Nameblk MC n325 Editblk MC Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y +~(F2*F1)+F4) Endblk Nameblk LD n323 Editblk LD Base FG Config F4:F4I G2: G3: CIN: COUT: X:F Y: XQ: YQ www.datasheetarchive.com/download/78754389-996537ZC/xsivnowk.tar |
Xilinx | 20/01/1997 | 9960 Kb | TAR | xsivnowk.tar |
| F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F2:F4 G: H: H1: DIN: SR: EC: RAM ) Endblk Editblk HH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F4:F3:F2:F1 *~ ) Endblk Editblk GG Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4:F2 G: H: H1: DIN: SR: EC: RAM: CARRY: CIN 1)+(F2*F4*F3*~F1)+(F2*F4*F3*F1) Endblk Editblk GH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX www.datasheetarchive.com/download/16518039-958264ZC/synopsys.tar |
Xilinx | 24/09/1996 | 10168 Kb | TAR | synopsys.tar |
| F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F2:F4 G: H: H1: DIN: SR: EC: RAM: CARRY: CIN: COUT: CDIR: Equate F = (F1*~F1*F3*F2*F4) Endblk Editblk HH Base FG Config F4:F4I G2: G3: X : CDIR: Equate F = (F4*~F4*F3*F2*F1) Endblk Editblk GG Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4:F2 G: H: H1: DIN: SR: EC: RAM: CARRY: CIN: COUT: CDIR: Equate F = (F1*~F1*F3*F4*F2) Endblk Editblk GH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX www.datasheetarchive.com/download/16518039-958264ZC/synopsys.tar |
Xilinx | 24/09/1996 | 10168 Kb | TAR | synopsys.tar |
| F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F2:F4 G: H: H1: DIN: SR: EC: RAM ) Endblk Editblk HH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F4:F3:F2:F1 *~ ) Endblk Editblk GG Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4:F2 G: H: H1: DIN: SR: EC: RAM: CARRY: CIN 1)+(F2*F4*F3*~F1)+(F2*F4*F3*F1) Endblk Editblk GH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX www.datasheetarchive.com/download/16518039-958264ZC/synopsys.tar |
Xilinx | 24/09/1996 | 10168 Kb | TAR | synopsys.tar |
| F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F2:F4 G: H: H1: DIN: SR: EC: RAM ) Endblk Editblk HH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F4:F3:F2:F1 *~ ) Endblk Editblk GG Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4:F2 G: H: H1: DIN: SR: EC: RAM: CARRY: CIN 1)+(F2*F4*F3*~F1)+(F2*F4*F3*F1) Endblk Editblk GH Base FG Config F4:F4I G2: G3: X:F Y: XQ: YQ: FFX www.datasheetarchive.com/download/16518039-958264ZC/synopsys.tar |
Xilinx | 24/09/1996 | 10168 Kb | TAR | synopsys.tar |
| _1 Pathnet n39_2 Endpath Editblk CL Base FG Config F4: G2: G3: X: Y: XQ: YQ:EC FFX:RESET FFY:RESET DX: DY: F: G: H: H1: DIN: SR: EC:C3 RAM: CARRY: CIN: COUT: CDIR: Endblk Editblk BL Base FG Config F4: G2:G2I G3:G3I X: Y:G XQ:QX YQ: FFX:K:NOT:EC:RESET FFY:RESET DX:DIN DY: F: G:G3:G2:G1 H: H1: DIN:C1 SR: EC:C4 RAM: CARRY: CIN: COUT: CDIR: Equate G = (G2*G3*G1) Endblk Editblk PAD85 PAD85 PAD85 PAD85 Base IO Config INFF: I1: I2 APC84 APC84 APC84 APC84 4 0 Speed -5 Addnet CLK i_bufgs_bl.I bufgs_bl.I Netdelay CLK bufgs_bl.I 3.6 Program CLK {16G18 16G18 16G18 16G18 www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/gate_clo/gate_cl0.lca |
Xilinx | 31/05/1995 | 3.03 Kb | LCA | gate_cl0.lca |
| _1 Pathnet n39_2 Endpath Editblk CL Base FG Config F4: G2: G3: X: Y: XQ: YQ:EC FFX:RESET FFY:RESET DX: DY: F: G: H: H1: DIN: SR: EC:C3 RAM: CARRY: CIN: COUT: CDIR: Endblk Editblk BL Base FG Config F4: G2:G2I G3:G3I X: Y:G XQ:QX YQ: FFX:K:NOT:EC:RESET FFY:RESET DX:DIN DY: F: G:G3:G2:G1 H: H1: DIN:C1 SR: EC:C4 RAM: CARRY: CIN: COUT: CDIR: Equate G = (G2*G3*G1) Endblk Editblk PAD85 PAD85 PAD85 PAD85 Base IO Config INFF: I1: I2 APC84 APC84 APC84 APC84 4 0 Speed -5 Addnet CLK i_bufgs_bl.I bufgs_bl.I Netdelay CLK bufgs_bl.I 3.6 Program CLK {16G18 16G18 16G18 16G18 www.datasheetarchive.com/download/61635476-996530ZC/xsi_vhdl.tar |
Xilinx | 09/04/1997 | 12384 Kb | TAR | xsi_vhdl.tar |
| _1 Pathnet n39_2 Endpath Editblk CL Base FG Config F4: G2: G3: X: Y: XQ: YQ:EC FFX:RESET FFY:RESET DX: DY: F: G: H: H1: DIN: SR: EC:C3 RAM: CARRY: CIN: COUT: CDIR: Endblk Editblk BL Base FG Config F4: G2:G2I G3:G3I X: Y:G XQ:QX YQ: FFX:K:NOT:EC:RESET FFY:RESET DX:DIN DY: F: G:G3:G2:G1 H: H1: DIN:C1 SR: EC:C4 RAM: CARRY: CIN: COUT: CDIR: Equate G = (G2*G3*G1) Endblk Editblk PAD85 PAD85 PAD85 PAD85 Base IO Config INFF: I1: I2 APC84 APC84 APC84 APC84 4 0 Speed -5 Addnet CLK i_bufgs_bl.I bufgs_bl.I Netdelay CLK bufgs_bl.I 3.6 Program CLK {16G18 16G18 16G18 16G18 www.datasheetarchive.com/download/78754389-996537ZC/xsivnowk.tar |
Xilinx | 20/01/1997 | 9960 Kb | TAR | xsivnowk.tar |