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I/O72

Catalog Datasheet MFG & Type PDF Document Tags

m37632mct

Abstract: M37632MFT I/O.72 ports 2. Acceptance filter support unit (ASU).1 channel 3. UART.2 channels 4. Timer , 7630 Group Introduction STCAN: M37630E4-XXXFP, M37630M4T-XXXFP FEATURES MITSUBISHI BASIC-CAN SPECIFICATION · Shortest instruction execution time 200 ns (f(XIN)=10M Hz) · Timer 16-bit x 2 (Bi-phase, timer, PWM, palse width measurement mode, etc.) 8-bit x 3 · UART 1 channel · Serial I/O 1 channel , sources · Programmable I/O port 36 ports · Package 44-pin QFP (0.8 mm pitch) · Operating temperature
Mitsubishi
Original
M37632EF-XXXFP M37632MFT-XXXFP m37632mct M37632MFT m37632 m37632mct-xxxfp M37632MCT-XXXFP
Abstract: I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I , I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 , VCC TDO I/O132 I/O133 I/O134 VCC M I/O63 I/O62 I/O61 I/O72 I/O77 I , - 3.3V ISR - 5V tolerant · Up to 192 I/Os - Plus 5 dedicated inputs including 4 clock inputs · Cypress Semiconductor
Original
CY37256V 256-M 160-L 208-L 256-L CY37256
Abstract: 1.5A Single Phase Bridges Standard and Fast Recovery 673-1 to 6 7 3 - 6 and 676-1 to 6 7 6 - 6 673, 676 Series-G Body .0285 Dia. _ 0 .72 mm Tinned Copper Lead 673, 676 Series-S Body .440 Max. 11.17 m m ' .187 Max. 4 .75 mm 1 I- .4 40 Max. 11.17 mm 1.25 Min. 31.8 mm 0.15 Max. 3.85 mm When specifing "G" body add suffix "G" i.e. 6 7 3 - 1 G .100 Typ. 2 .54 mm 0.55 14 mm r -r I I o.72 mm Tinned Copper Lead 0285 Dia-_IL_ When specifing "S" body add suffix "S" i.e. 6 -
OCR Scan

ultraISR CABLE

Abstract: /Os I/O36 -I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48 -I/O59 12 I/Os I/O60 -I/O71 12 I/Os I/O72 , I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC GND VCC I/O80 I/O81 I/O82 I/O83 I/O84 I , /O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I , standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 192 I/Os - Plus 5 dedicated inputs including 4 , individual I/Os Low-power option on individual logic block basis User-Programmable Bus Hold capabilities on
Cypress Semiconductor
Original
ultraISR CABLE CY37384V 384-M CY37384 CY37256/37256V CY37512/37512V 37384VP256-83BGC

CY37256P160-125UMB

Abstract: CY37256P160-83UMB /O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /TDO I , /O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , changes · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed - fMAX = , Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low
Cypress Semiconductor
Original
CY37256P160-125UMB CY37256P160-83UMB CY37256P160-125AI CY37256-125 CY37128/37128V CY37192/37192V CY37384/37384V CY7C375 I/O0-I/O11 I/O12-I/O23

ULTRA37000

Abstract: /O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 , I/O78 I/O79 VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I , GND I/O76 /SDO I/O72 I/O50 I/O47 I/O44 I/O41 B I/O80 I/O79 I/O77 I , Features · 3.3V or 5.0V I/O operation · Available in 160-pin TQFP, CQFP, and PGA packages · 128 macrocells in eight logic blocks · 128 I/O pins Functional Description · Five dedicated inputs
Cypress Semiconductor
Original
ULTRA37000 ULTRA37000TM 128-M FLASH370 22V10
Abstract: /O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCCIO GND I/O52 , /O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND VCC I/O52 /SMODE I/O53 I/O54 I/O55 GND I , I/O76 /SDO I/O72 I/O50 I/O47 I/O44 I/O41 B I/O80 I/O79 I/O77 I/O73 , Description · · · · 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including , capabilities on all I/Os and dedicated inputs · No hidden delays · High speed - fMAX = 125 MHz The Cypress Semiconductor
Original
LASH370 160-P

208-Lead

Abstract: CY37512 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , /O172 V I/O94 I/O93 I/O92 VCC VCC I/O171 I/O170 I/O169 W I/O95 I/O72 I , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable
Cypress Semiconductor
Original
CY37512V CY37512 208-Lead CY37512VP208-66NI 512-M CA95134 I/O24-I/O35 I/O36-I/O47

ultraISR CABLE

Abstract: CY37256 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I/O79 VCCO GND I/O16 I , I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold
Cypress Semiconductor
Original
I/O48-I/O59 I/O60-I/O71 I/O72-I/O83 I/O84-I/O95 256-P 38-00474-E
Abstract: /O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCCIO GND I/O48 I/O49 I/O50 I/O51 GND , I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND I/O48 I/O49 I/O50 I/O51 Document #: 38-03029 Rev , /O40 I/O38 C I/O83 I/O81 GND I/O72 GND I/O66 I2 I/O60 I/O50 I/O47 , · 128 I/O pins · Five dedicated inputs including 4 clock pins · In-System Reprogrammable (ISRTM) Flash technology - JTAG Interface · Bus Hold capabilities on all I/Os and dedicated inputs · No hidden Cypress Semiconductor
Original
Abstract: VCCINT I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 , /O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCC 1 3 GND , I/O72 I/O50 I/O47 I/O44 I/O41 B I/O80 I/O79 I/O77 I/O73 I/O52/ I/O49 , 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology - JTAG Interface · Bus Hold capabilities on all I/Os Cypress Semiconductor
Original

U208

Abstract: TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , /O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 I/O95 I/O96 I/O100 I , /O38 I/O40 TCK I/O44 I/O47 I/O50 I/O53 I/O56 I/O59 I/O60 VCC I/O66 I/O69 I/O84 I/O87 I/O90 I/O93 I/O72 , VCC I/O91 I/O90 I/O72 VCC I/O128 I/O127 I/O133 I/O162 VCC TDO I/O180 I/O168 , standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - Plus 5 dedicated inputs including 4
Cypress Semiconductor
Original
U208 352-L 400-L BG256 BG352 51-85069-B
Abstract: I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCCIO GND GND I/O48 I/O49 , /O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 , /O73 VCC GND VCC VCC I/O43 I/O40 I/O38 C I/O83 I/O81 GND I/O72 , 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology - JTAG Interface · Bus Hold capabilities on all I/Os and dedicated inputs · No hidden delays · Cypress Semiconductor
Original

CY37512

Abstract: CY37512V I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , /O172 V I/O94 I/O93 I/O92 VCC VCC I/O171 I/O170 I/O169 W I/O95 I/O72 I , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable
Cypress Semiconductor
Original
2VP208-66NI 208-P CY37512VP256-66BGI CY37512VP352-66BGI 352-P CY37512VP208-66UMB

CY37256

Abstract: CY37256V /O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I , I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 , 3.3V ISR - 5V tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High , Programmable slew rate control on individual I/Os Low power option on individual logic block basis
Cypress Semiconductor
Original
O116 38-00606-C

tea 1601 t

Abstract: Programmable pull-up or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - , on all major programmers including Data I/O, BP Microsystems, Advin, and System General , 3.3 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant 5 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz , Commercial, C C C -5 C C C C C C C C -55 -6 -65 -7 C, I C, I C, I C, I C, I C, I C, I C C -10 C, I C, I C, I
Lattice Semiconductor
Original
tea 1601 t 182MH M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64

37256p

Abstract: CY37256-125 /O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /TDO I/O77 I/O78 I/O79 VCCO 41 42 43 44 45 46 47 , I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC0 GND VCC , /O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I , don't cause pinout changes - Design changes don't cause timing changes · Up to 192 I/Os - Plus 5 , slew rate control on individual I/Os Low-power option on individual logic block basis 5V and 3.3V I/O
Cypress Semiconductor
Original
37256p IEEE 1149.1 JTAG I/O180-I/O191 I/O168-I/O179 I/O156-I/O167 I/O144-I/O155 I/O132-I/O143 I/O120-I/O131

ULTRA37000

Abstract: 160-Lead I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND I , I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND , VCC I/O43 I/O40 I/O38 C I/O83 I/O81 GND I/O76 /SDO I/O72 I/O50 I/O47 , Features · 3.3V or 5.0V I/O operation · Available in 160-pin TQFP, CQFP, and PGA packages · 128 macrocells in eight logic blocks · 128 I/O pins Functional Description · Five dedicated inputs
Cypress Semiconductor
Original
160-Lead
Abstract: or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - Individual , Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# ISPM4A Amendment/0 Rev: I Issue Date: May 2001 Table 1. ispMACH 4A Device Features 3.3 , -384 M4A3-512 Macrocells 32 64 96 128 192 256 384 512 User I/O options 32 , User I/O options 32 32 48 64 96 128 tPD (ns) 5.0 5.5 5.5 5.5 6.0 -
Original
M4A3-192/96 M4A3-256/128 M4A3-256/160 M4A3-256/192 M4A3-384/160 M4A3-384/192

tea 1601 t

Abstract: tea 1601 or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - Individual , Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General , 3.3 V Devices Feature Macrocells User I/O options M4A3-322 M4A3-642 M4A3-962 M4A3 , -962 M4A5-1282 M4A5-1921 M4A5-2562 Macrocells 32 64 96 128 192 256 User I/O , -5 M4A3-323 M4A5-323 -55 -6 -65 -10 -12 C, I C -7 C, I I M4A3
Lattice Semiconductor
Original
tea 1601 O2-A2 160 e7 led matrix circuits ISPMACH ispMACH 4A Family M4A3-256/1601 M4A3-256/1921 M4A3-512/160 M4A3-512/192 M4A3-512/256 M4A5-32/32

pasic 3

Abstract: QL3004-1PL68C GOE1 I/O72 I/O76 I/O78 I/O81 GND I/O85 B I/O53 I/O57 I/O60 I/O63 I
QuickLogic
Original
pasic 3 QL3004-1PL68C QL3004 QL3012-1PF144C QL3004E Military Plastic pASIC 3 Family

QL3004

Abstract: QL3004-1PL68C I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I , I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 , VCC TDO I/O132 I/O133 I/O134 VCC M I/O63 I/O62 I/O61 I/O72 I/O77 I
QuickLogic
Original
QL3004-1PL84C QL3006 QL3025 QL3040 QL3060 QL3012

b1624

Abstract: GOE1 I/O72 I/O76 I/O78 I/O81 GND I/O85 B U C SE O is M p M L ER SI C 10
Lattice Semiconductor
Original
b1624 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 M4A3256/128-7YC-10YI

tea 1601 t

Abstract: O2-A2 I/O80 I/O83 A GND I/O62 I/O65 I/O68 I/O71 GND GOE1 I/O72 I/O76 I
Lattice Semiconductor
Original
512256
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