NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: protection diodes, < 5pF typical · TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines · , to VAUX) for HSYNC & VSYNC inputs · Pull-up resistors (1.8K nominal to VCC) for DDC_CLK and , included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These , HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high , B DDC_DATA HSYNC VSYNC HSYNC_OUT C1780401 C1780401 © 2001 California Micro Devices Corp. All ... | Original |
4 pages, |
PACVGA105 IEC-1000-4-2 PACVGA105Q TTL sync video to vga Hsync Vsync RGB VSYNC HSYNC DDC_CLOCK DDC_DATA ttl input convert to vga output Hsync Vsync separate rgb to hsync vsync Hsync Vsync analog to digital convert Hsync Vsync VGA Hsync Vsync convert PACVGA105 abstract |
|
|||
| Abstract: typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply , impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC , Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from , the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The , 1.8k 50k 50k VSYNC_OUT DDC_CLK G B GNDD GNDA DDC_DATA HSYNC VSYNC HSYNC_OUT ... | Original |
6 pages, |
VSYNC HSYNC DDC_CLOCK DDC_DATA IEC-1000-4-2 IEC-61000-4-2 Non VGA Video Controller IC PACVGA105 PACVGA105Q PACVGA105QR rgb to hsync vsync schematic diagram video to vga ttl input convert to vga output Hsync Vsync RGB Hsync Vsync separate PACVGA105 abstract |
|
|||
| Abstract: in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers , Diodes at Less than 5 pF Typical TTL to CMOS Level-Translating Buffers for the HSYNC and VSYNC Lines , Controller ICs High impedance Pull-Ups (50 kW Nominal to VAUX) for HSYNC and VSYNC Inputs Pull-Up Resistors , 1.8 kW R G B DDC_CLK 1.8 kW 50 kW 50 kW VSYNC_OUT VAUX GNDA DDC_DATA HSYNC VSYNC GNDD , to the HSYNC and VSYNC buffer inputs. Vertical sync signal buffer input. Connects to the VGA ... | Original |
6 pages, |
Hsync Vsync convert PACVGA105 IEC-1000-4-2 PACVGA105 abstract |
|
|||
| Abstract: 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent , impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC , buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics , impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers , 1.8k R 1.8k 50k 50k VSYNC_OUT DDC_CLK G B GNDA DDC_DA TA HSYNC VSYNC ... | Original |
9 pages, |
VSYNC HSYNC DDC_CLOCK DDC_DATA IEC-1000-4-2 IEC-61000-4-2 IEC1000-4-2 Non VGA Video Controller IC PACVGA105 PACVGA105Q PACVGA105QR schematic diagram video to vga Hsync Vsync VGA Hsync Vsync convert Hsync Vsync analog to digital convert PACVGA105 abstract |
|
|||
| Abstract: Voltage VISP Source Resistance Rg=75 100 140 180 mV H-Sync. High Level VHH1 RL=100k Pin 3 (13) 4.0 - - V H-Sync. High Level VHH2 RL=2.2k Pin 3 (13) 3.6 4.1 - V H-Sync. Low Level VHL RL=2.2k Pin 3 (13) - - 0.1 V H-Sync. High Level VHH ¯ RL=100k Pin 4 (14) 4.9 - - V H-Sync. Low Level VHL ¯ RL=100k Pin 4 (14) - - 0.3 V V-Sync. High Level VVH1 RL=100k Pin 7 (2) 4.0 - - V ... | Original |
6 pages, |
ZIP16 NJM2207S NJM2207M NJM2207D NJM2207 DMP14 Hsync Vsync convert DIP-14 DMP-14 ZIP-16 NJM2207 abstract |
|
|||
| Abstract: Input Threshold Voltage VISP Source Resistance Rg=75 100 140 180 mV H-Sync. High Level VHH1 RL=100k Pin 3 (13) 4.0 - - V H-Sync. High Level VHH2 RL=2.2k Pin 3 (13) 3.6 4.1 - V H-Sync. Low Level VHL RL=2.2k Pin 3 (13) - - 0.1 V H-Sync. High Level VHH ¯ RL=100k Pin 4 (14) 4.9 - - V H-Sync. Low Level VHL ¯ RL=100k Pin 4 (14) - - 0.3 V V-Sync. High Level VVH1 RL=100k Pin 7 (2) 4.0 - ... | Original |
6 pages, |
ZIP16 DMP14 DMP14 Package Hsync Vsync convert NJM2207 NJM2207D NJM2207M NJM2207S "Video Switches" TV vertical section DIP14 NJM2207 abstract |
|
|||
| Abstract: NTSC standard video through A4, Video In. The EL4583 EL4583 separates H-sync and sends it through jumper R10 to the EL4584 EL4584. H-sync can be monitored at A1, H-sync. On the board settings, the internal divider , clock pulse of the same H-sync input frequency from the oscillator and adjusts the on-board LC VCO to , A2, EXT DIV. The full clock frequency (which should equal to H-sync (15.734kHz)*divider (910) = , EXT DIV locks to the H-sync. SW1 has 3 positions. LEFT grounds COAST and puts the EL4584 EL4584 into normal ... | Original |
3 pages, |
Hsync Vsync convert EL4585 EL4584 EL4583CS EL4583 SMV1212-001 CRYSTAL 14.318MHZ TB430 EL4583 abstract |
|
|||
| Abstract: . 12 3 Mar. 2002 ZC0301 ZC0301 VGA & CIF USB PC Camera Controller 1. Features VSYNC HSYNC , CS_ENB HSYNC VSYNC ZC0301 ZC0301 Figure 3 28-Pin PLCC Package 3.2. Pin Description Table 1 Sensor Interface (15 Pins) Signal CS_D[5] CS_D[6] CS_D[7] CS_RESET# CS_ENB HSYNC VSYNC CS_D[0 , MCLK TO HSYNC / VSYNC Timing FIGURE 8.1-1 MCLK TO HSYNC/VSYNC TIMING DIAGRAM T1: MCLK RISING TO HSYNC/VSYNC valid maximum Time: 18ns [output load: 60pF] T2: HSYNC/VSYNC valid Time: minimum 1 clock ... | Original |
15 pages, |
cmos IMAGE SENSOR I2C interface vga ZC030 camera SENSOR 24 pin HV7131B pc camera controller 8x8 rgb led driver usb to VGA 018EH VGA to VGA connection DIAGRAM VGA to vga CABLE CONNECTION DIAGRAM vga encoder VGA decoder circuit ZC0301 ZC0301 ZC0301 abstract |
|
|||
| Abstract: Sync. Sepa. Input Threshold Voltage V,sp Source Resistance Rg=75ii HM) 140 180 mV H-Sync. High Level V„h, R, = I(IOkn Pin 3 (13) 4.(1 - - V H-Sync. High Level V„h: Ri =2.2k!i Pin 3 (13) 3.(i 4.1 - V H-Sync. Low Level v,„ Ri =2.2kO Pin 3 (13) - - 0.1 V H-Sync. High Level Vïïh R, = l(H)ki! Pin 4 (14) 4.9 - - V H-Sync. Low Level Vn, R, = l(K)kn Pin 4 (14) - - 0.3 V V-Sync.High Level V\h, Ri - l(H)kli Pin 7 (2) 4.(1 - - V V-Sync. High Level Vv„: Ri = Kikii Pin 7 (2) 3.6 4.1 - V V-Sync. Low Level Vv,. ... | OCR Scan |
5 pages, |
NJM2207 IJM27070 Hsync Vsync convert D1P-14 crt tube 14 pin NJM22Q7 NJM22Q7 abstract |
|
|||
| Abstract: (ITU-R BT.601 in 8-bit with embedded timing) - 8-bit or 16-bit ITU-R BT.601 with additional HSync and n VSync - 24-bit RGB with additional HSync and VSync n n Support square pixel input format n , built-in n Brightness, contrast, saturation, 10-bit DAC convert digital video and hue control output to , Detect/Convert: configuration pin setting. Performs optional 50-to-60 Hz Generates required timing ... | Original |
2 pages, |
YUV422 deinterlacer film mode detection PAL to ITU-R BT.601/656 Decoder ITU-R BT 601 Hsync Vsync convert Hsync Vsync analog to digital convert Hsync Vsync decoder timing diagram for rgb bt.656 to RGB deinterlacer deinterlace ITU-R BT.601 to 656 Decoder VX1511 VX1511 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| available vertical (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD722 AD722 AD722 AD722 will also accept a standard CSYNC signal by connecting VSYNC to +5 V and applying CSYNC to HSYNC pin. The AD722 AD722 AD722 AD722 contains decoding logic to identify valid HSYNC pulses for Description= RGB to NTSC/PAL Encoder General Description The AD722 AD722 AD722 AD722 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their www.datasheetarchive.com/files/analog-devices/gendesc/488.htm |
Analog Devices | 05/06/2003 | 2.19 Kb | HTM | 488.htm |
| accepts the available vertical (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync VSYNC to +5 V and applying CSYNC to the HSYNC pin. The AD724 AD724 AD724 AD724 contains decoding logic to identify valid RGB to NTSC/PAL Encoder General Description The AD724 AD724 AD724 AD724 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL www.datasheetarchive.com/files/analog-devices/doc/productdescriptions/505.html |
Analog Devices | 2.08 Kb | HTML | 505.html | |
| on-chip logic Â"XNORÂ" accepts the available vertical (VSYNC) and horizontal sync (HSYNC) signals and CSYNC signal by connecting VSYNC to +5 V and applying CSYNC to the HSYNC pin. The AD724 AD724 AD724 AD724 contains Description= RGB to NTSC/PAL Encoder General Description The AD724 AD724 AD724 AD724 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) signals in accordance with either NTSC www.datasheetarchive.com/files/analog-devices/gendesc/496.htm |
Analog Devices | 05/06/2003 | 2.14 Kb | HTM | 496.htm |
| -Row Clock P11-7 P11-7 P11-7 P11-7 HSYNC 12 S-Scan Start P11-9 P11-9 P11-9 P11-9 VSYNC -> 9 DF Switch Signal to Convert LCD Drive waveform into AC P11-7 P11-7 P11-7 P11-7 HSYNC -> 7 -> 6 VSS Ground P11-7 P11-7 P11-7 P11-7 HSYNC -> 2 CP1 Horizontal Sync (42us) P11-9 P11-9 P11-9 P11-9 VSYNC -> 6 Hsync HORIZONTAL SYNCHRONOUS SIGNAL P11-9 P11-9 P11-9 P11-9 VSYNC -> 4 Vsync VERTICAL Data clock (6mhz) P11-6 P11-6 P11-6 P11-6 GND -> 6 VSS Ground P11-7 P11-7 P11-7 P11-7 HSYNC -> 2 CL1 www.datasheetarchive.com/download/22743547-483219ZC/pc821lcd.zip (README) |
Motorola | 13/09/1996 | 45.15 Kb | ZIP | pc821lcd.zip |
| converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 DS90CF366 DS90CF366 DS90CF366 that converts the three LVDS data streams (Up to 1.785 Gbps throughput or 223 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe www.datasheetarchive.com/files/national/htm/nsc02293-v1.htm |
National | 13/08/1999 | 10.31 Kb | HTM | nsc02293-v1.htm |
| receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 DS90CF366 DS90CF366 DS90CF366 that converts the three LVDS data streams (Up to 1.785 Gbps throughput bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling www.datasheetarchive.com/files/national/htm/nsc02288-v1.htm |
National | 13/08/1999 | 10.35 Kb | HTM | nsc02288-v1.htm |
| CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A DS90CF364A DS90CF364A DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE , Models, Samples & Pricing General Description The DS90CF384A DS90CF384A DS90CF384A DS90CF384A receiver converts the four LVDS www.datasheetarchive.com/files/national/htm/nsc02996-v4.htm |
National | 16/09/1998 | 8 Kb | HTM | nsc02996-v4.htm |
| converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A DS90CF364A DS90CF364A DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe www.datasheetarchive.com/files/national/htm/nsc05459.htm |
National | 18/12/1998 | 8.85 Kb | HTM | nsc05459.htm |
| CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A DS90CF364A DS90CF364A DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE , Models, Samples & Pricing General Description The DS90CF384A DS90CF384A DS90CF384A DS90CF384A receiver converts the four LVDS www.datasheetarchive.com/files/national/htm/nsc02992-v4.htm |
National | 16/09/1998 | 8 Kb | HTM | nsc02992-v4.htm |
| bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 DS90CF366 DS90CF366 DS90CF366 that converts the three LVDS data streams (Up to 1.785 Gbps throughput or 223 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE Availability, Models, Samples & Pricing General Description The DS90CF386 DS90CF386 DS90CF386 DS90CF386 receiver converts the four www.datasheetarchive.com/files/national/htm/nsc05460.htm |
National | 18/12/1998 | 8.17 Kb | HTM | nsc05460.htm |