NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: change without notice R R tn G R tn B R tn HSYNC VSYNC VGA-15 VGA-4 VGA-12 VGA-11 VGA , ) (D D C D at a) From 65550/554 ID 3 ID 2 ID 1 ID 0 HSYNC VSYNC VGA-13 VGA-14 R G , /548: R5=33ohm, R8=open R5=open, R8=33ohm 65550: HSYNC 65 VSYNC 64 MCD15-0 MCD15-0 (VR5-2,VG7-2,VB7-2 , FSTAT n/c EGEN# n/c BLANK# HSYNC VSYNC PCLK VCLK VRDY GRDY EVIDEO# VAFC-1 VAFC-2 VAFC-14 VAFC-14 , n/c EGEN# n/c BLANK# HSYNC VSYNC PCLK VCLK VRDY GRDY EVIDEO# D15:0 A8:0 RAS 256K CAS ... | Original |
18 pages, |
BIOS Flash ROM Chip 486DX datasheet 486DX BIOS Flash ROM Chip datasheet 486DX BIOS Flash ROM Chip CPU191 386SX VLB24 VLA11 VGA14 vga bios 65550 REQ64 PCV-40 PCI-B34 datasheet abstract |
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| Abstract: Position Mode Hsync Vsync VGA-480 VGA-400 VGA-350 Freedom Mode Negative Negative , format is VGA-400 (Hsync = Negative , Vsync = Positive) , LCD module will adjust the display area to the , Bla n kin g L in es Note 7-6: As the format is VGA-350 (Hsync = Negative, Vsync = Positive) , LCD , Symbol GND CLK Hsync Vsync GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND B0 B1 B2 , mode . The polarization of Hsync and Vsync determine the timings. Hsync Polarization Vsync ... | Original |
24 pages, |
VGA-480 VGA-400 T-51382D064J-FW-P-AC HP 306 DF9A-31P-1V BHR-03VS-1 Hsync Vsync VGA ctk 25 4 tube T-51382D064J-FW-P-AC abstract |
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| Abstract: polarization of Hsync and Vsync determine the timings. Hsync Polarization Vsync Polarization VGA , ) Vertical Display Position Mode Hsync Vsync VGA-480 VGA-400 VGA-350 Freedom Mode Negative , format is VGA-400 (Hsync = Negative , Vsync = Positive) , LCD module will adjust the display area to the , Bla n kin g L in es Note 7-6: As the format is VGA-350 (Hsync = Negative, Vsync = Positive) , LCD , Hsync Vsync GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND B0 B1 B2 B3 B4 B5 GND ... | Original |
24 pages, |
VGA-480 VGA-400 T-51382D064J-FW-P-AC T-51382D064J-FW-P-AA DF9A-31P-1V BHR-03VS-1 T-51382D064J-FW-P-AA abstract |
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| Abstract: : As the format is VGA-350(Hsync = Negative, Vsync = Positive), LCD module will adjust the display , Symbol GND CLK Hsync Vsync GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND B0 B1 B2 , The polarization of Hsync and Vsync determine the timings. Hsync Polarization Vsync Polarization , signals include CLK, Hsync, Vsync, DENB, R[0:5], G[0:5] and B[0:5]. Note 6-2: Humidity : 95% RH Max. at , All Periodic = Line Thp All Hsync Pulse Width Thpw All Back Porch Thbp All VGA ... | Original |
19 pages, |
vga connector 20 pin lcd to 15 pin lcd 4 switch 3 phase inverter ctk 25 4 tube lcd cross reference vga connector 15 Pin sine wave inverter 3 phase inverter circuit control sine wave power inverter vga connector 10 pin 3 phase inverter circuit Hsync Vsync VGA T-51382D064J-FW-P-AA T-51382D064J-FW-P-AA abstract |
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| Abstract: R0 G B0 HSYNC VSYNC VGA Connector H0 V0 VDD_5 R1 G1 B1 H1 V1 SDA1 SCL1 , · · 12 · RTG PACKAGE (TOP VIEW) 13 Supports 7-channel VGA Signals (R, G, B, HSYNC , Shifting Buffers for HSYNC and VSYNC Channels Voltage Clamping NMOS Switches for SCL and SDA Channels , bandwidth of 1.3 GHz. The TS3V713EL TS3V713EL has integrated level shifting buffers for the HSYNC and VSYNC signals , SDA2 SCL2 SEL A. Supply for HSYNC and VSYNC translators B. Control Logic Output ... | Original |
20 pages, |
TS3V713EL JESD22-A114E TF713EL Hsync Vsync VGA SCDS312A TS3V713EL abstract |
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| Abstract: Interface VGA Memory Address i L ti Data VGA Controller HSync,VSync VGA pixel data, Blank 8514/A 8514/A Graphics Processor Address Control Signals. ^ VGA R,G,B^ RAMDAC VGA Pass through data _HSync,VSync , Pending) 90 89 94 HSYNC VSYNC BLANK/ Tri-O Tri-0 Tri-O Both Both Low Horizontal and Vertical Sync signals , drive the HSYNC and VSYNC outputs instead of the 82C480 82C480 H/V Sync. 73 SENSE In High Sense Input for , VGA/8514 Pass-Through Interface.5 82C452 82C452 ... | OCR Scan |
109 pages, |
298n marking Um diode 31df bt471 82C452 15-13 pin vga cable connection bt478 EPROM 27256 programmer schematic msi motherboard circuit diagram s401 diode logic diagram of 74LS245 LMB 06E TIRIS DST 82C480 8514/A-COMPATIBLE 82C480 abstract |
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| Abstract: optimal fit of VGA graphics and text on 800x600 and 1024x768 panels VESA Standards supported · VAFC , backlight operation Mixed 3.3V and 5.0V Operation Fully Compatible with IBM® VGA Simultaneous Hardware , support Games SDK support Dynamic Resolution Switching VGA Graphics applications in Window VESA DDC , REVISION 1.2 · · · · · · · · · · · · · · · · · · · · · VGA Compatible BIOS PCI , Added more detailed system diagrams. Updated all register sections. Added VGA, PCI, BitBLT, Global ... | Original |
417 pages, |
vga bios 65550 486 system bus 486dx isa bios pin assignment 550b 65550 CHIPS 0.7 BIOS Flash ROM Chip datasheet bitblt s3 br06 386SX ST01 intel organisational structure LCD 128 16 24 graphics monochrome POS102 datasheet abstract |
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| Abstract: includes the ability to independently stop HSYNC or VSYNC and hold them at a static level. Additionally , ) Monitor Communication Protocol Full VGA compatibility 208-pin PFP is pin-compatible with the 64300 , fixed programming examples) Added parameter tables for Standard VGA Registers (VGA Parameters) Removed , . VGA Color Palette/DAC. BitBlt , . 38 VGA Indexed Registers. 39 Extension Registers ... | Original |
176 pages, |
6554X 64310 comparison 0f 80486dx and 80486sx CRTC 6845 DR08 27F256 schematic diagram cga to vga plasma 640x480 486 motherboard schematic EPROM 27256 programmer schematic 486SX 28.322MHz cga motorola datasheet abstract |
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| Abstract: This includes the ability to independently stop HSYNC or VSYNC and hold them at a static level. , the VESA Display Data Channel (DDC) Monitor Communication Protocol Full VGA compatibility 208-pin , Standard VGA Registers (VGA Parameters) Removed Hardware Assistance in Line Drawing 1.0 12/94 DH Initial , Attribute Controller.15 VGA Color Palette/DAC. , VGA Indexed Registers." 39 Extension ... | OCR Scan |
173 pages, |
tvga 486DX2-66 3C8 Ferrite Material 28.322MHz intel 775 motherboard diagram 80486dx memory interfacing 845 bios chip Hsync Vsync VGA EPROM 27256 programmer schematic DATA SHEET FOR OL 107 E SOLDER PEST 80486DX intel cga motorola pin configuration of ic LM339 datasheet abstract |
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| Abstract: (Bt484 Bt485 TLC34075 TLC34075 or equivalent) MS2:0 HSYNC, VSYNC A15:14, A1:0 D7:0 VHSYNC, VVSYNC VGA , drawing engine requires a VGA Memory Address Data HSync,VSync VGA Controller VGA pixel data , 82C481 82C481 Graphics Accelator Address HSync,VSync Control Signals, Blank Data Video Memory , ) BLANK/ (BANK) AF VHSYNC VVSYNC HSYNC VSYNC NCLK CAS01/ CAS01/ FWE WE0A/ PALWR/ PALRD/ 8BITDAC , registers at I/O address 32E8h 3EE8h. 90 89 94 HSYNC VSYNC BLANK/ Tri-O Tri-O Tri-O Both ... | Original |
138 pages, |
wingine 31DF 2 9H 31DF diode 82C480 82C481 API20 bt484 bt485 256Kx4 VRAM TLC34075 s3 trio display controller inmos IMSG176 IBM motherboard schematics 478 82C481b 82C481 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Dieses LCD ist ein analoges LCD. Farben, Hsync, Vsync vom VGA out und Clock vom LCD out. Funktioniert nur in gewissen Modis gut. Muss angepasst werden auf die Anforderungen des Benützers. Farben sind nur mittelmässig. Das Panel ist nicht zu empfehlen. LEB 2.02 www.datasheetarchive.com/download/1398051-80322ZC/vga548-v1.zip (Analog LQ5AW136.txt) |
Digital Logic | 28/08/2006 | 3465.22 Kb | ZIP | vga548-v1.zip |
| +hsync +vsync # TFT NTSC 480x234 connected on VGA Modeline "VGANTSC480X234 VGANTSC480X234 VGANTSC480X234 VGANTSC480X234#480x234" 25.175 480 664 760 800 234 491 493 525 # 640x400 @ 85 Hz, 37.86 kHz hsync #Modeline "MONITOR#640x400" 31.5 640 672 736 832 400 401 404 445 -HSync +VSync # 640x480 @ 60 Hz, 31.5 kHz Modeline "MONITOR #Modeline "MONITOR#800x600" 50 800 856 976 1040 600 637 643 666 +hsync +vsync # 800x600 777 806 -hsync -vsync # 1024x768 @ 60 Hz, 48.4 kHz Modeline "MONITOR#1024x768" 65 1024 1032 www.datasheetarchive.com/download/61085892-847989ZC/xfree86.zip (XF86Config) |
STMicroelectronics | 23/10/2000 | 1239.95 Kb | ZIP | xfree86.zip |
| IDSEL ENABKL HREF SGND SCKE VSYNC ENAVDD VREF VCLK PGND DCLK HSYNC RSET PCLK RSET SHFCLK DQMCL DQMCL BCLK DQMBL SGCLK VREF IDSEL VSYNC SGCKI ENABKL HSYNC SCKE SGCLK HREF ENAVDD BCLK PCLK ENAVDD MCLK DQMBL DQMAL VRDY VCLK VSYNC SCKE HSYNC DQMBH DCLK RESISTOR RESISTOR RESISTOR CAPACITOR POL.Normal CAPACITOR DQMCH DQMCH DQMCL DQMCL SCKE SCKE ENABKL ENABKL SHFCLK SHFCLK ENAVDD ENAVDD RSET RSET HSYNC HSYNC VSYNC , CA 95134 Part Reference Value 1st Part Field Name ENABKL SHFCLK ENAVDD RSET HSYNC VSYNC VREF HREF www.datasheetarchive.com/download/49805886-262311ZC/or69k.zip (abhiqv.dsn) |
Intel | 01/04/1999 | 807.99 Kb | ZIP | or69k.zip |
| polarity */ void SetSyncPolarity(int boHSyncNeg, int boVSyncNeg) { unsigned char bMiscOut; bMiscOut=IORead8(MISC_OUT_READ); bMiscOut&=0x03F; if( boHSyncNeg ) { bMiscOut|=0x40; } if( boVSync CrtcExtReg; int boForceClock=0; double dfFreq=40.00; int boForcePolarity=0; int boHSyncNeg=0; int boVSync \n"); } break; case 's' : boVSyncNeg=argv[nArg][2]-'0'; boHSyncNeg=argv[nArg][3 VRS=GetVRS(); wHRE=GetHRE(); wVRE=GetVRE(); wHSE=GetHSyncEnd(); wVSE=GetVSyncEnd(); wHBS=GetHBS(); w www.datasheetarchive.com/download/99750161-848057ZC/gwgtft09.zip (TIMING.C) |
STMicroelectronics | 03/01/2000 | 799.96 Kb | ZIP | gwgtft09.zip |
| ENABKL VSYNC ENAVDD VCLK VREF RSET DDCCLK HSYNC SHFCLK Vref Href VCLK REFCLK MCKGND ENAVDD ENABKL Hsync GND POWER VDDSAFE RESERVED HREF ENABKL ENTV ENAVDD VSYNC VCON VIDEO CLOCK-SOURCE VREF DDCCLK HSYNC Hsync Vsync GND SIGNAL DDCCLK ENAVDD ENABKL STNDBY DACGND GND FIELD SIGNAL MCKGND DCKGND 25x2 Panel VSYNC BLUE ENABKL DCLKIN MCLKIN MCKGND IDSEL BUSCLK SHFCLK DACGND 12X2 Panel Connector.Normal 12X2 Panel Connector WIPER WIPER Ferrite Bead.Normal Ferrite Bead.Normal ANODE CATHODE VGA Connector COMMON COMMON VOUT www.datasheetarchive.com/download/49805886-262311ZC/or69k.zip (69kref.dsn) |
Intel | 01/04/1999 | 807.99 Kb | ZIP | or69k.zip |
| interface to VGA Controllers and MPEG Video Decoders is simple: an on-chip logic "XNOR" accepts the available vertical (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD722 AD722 AD722 AD722 will also accept a standard CSYNC signal by connecting VSYNC to +5 V and applying CSYNC to HSYNC pin. The AD722 AD722 AD722 AD722 contains decoding logic to identify valid HSYNC pulses for www.datasheetarchive.com/files/analog-devices/gendesc/488.htm |
Analog Devices | 05/06/2003 | 2.19 Kb | HTM | 488.htm |
| -Row Clock P11-7 P11-7 P11-7 P11-7 HSYNC 12 S-Scan Start P11-9 P11-9 P11-9 P11-9 VSYNC -> 6 VSS Ground P11-7 P11-7 P11-7 P11-7 HSYNC -> 2 CP1 Horizontal Sync (42us) P11-9 P11-9 P11-9 P11-9 VSYNC -> 6 Hsync HORIZONTAL SYNCHRONOUS SIGNAL P11-9 P11-9 P11-9 P11-9 VSYNC -> 4 Vsync VERTICAL , the setting is for SHARPCVGA - SHARP LQ64D141 LQ64D141 LQ64D141 LQ64D141 Active VGA Panel. Please refer to the device Data clock (6mhz) P11-6 P11-6 P11-6 P11-6 GND -> 6 VSS Ground P11-7 P11-7 P11-7 P11-7 HSYNC -> 2 CL1 www.datasheetarchive.com/download/22743547-483219ZC/pc821lcd.zip (README) |
Motorola | 13/09/1996 | 45.15 Kb | ZIP | pc821lcd.zip |
| , CONFIGURATIONS STRAPS NTSC/PAL ENCODER DPAK OSCP FBEAD FERRITE AGND DCLK VGA, VIDEO INPUT PORT HSYNC VSYNC BLUE Title Size Document Number VSYNC HSYNC NRESET VREFRGB IREFRGB CKREF IREFCVBS VREFCVBS CVBS CENTER SYSCLK BLUE VSYNC HSYNC VREF COMP RSET PIRQ SIRQ PDRQ SDRQ POWERGD DCLK XTALI XTALO HCLK SIPVCC SIPVCC ISASYSCLK DCLK HSYNC MAINOSC IOCHRDY SYSCLOCK BLUE VSYNC HSYNC PIRQ SIRQ PDRQ SDRQ POWERGD DCLK BEAD FBEAD VSYNC HSYNC BLUE DDCCLOCK DCLK AND VIDEO_CLK PROTECTED WITH GROUND RING VIDEO INPUT PORT VREFRGB www.datasheetarchive.com/download/65997386-847681ZC/ref13sch.zip (RDCLIENT.DSN) |
STMicroelectronics | 02/11/1999 | 331.41 Kb | ZIP | ref13sch.zip |
| BLUE VSYNC HSYNC CENTER SHIELD DISKONCHIP 2000.Normal DISKONCHIP 2000.Normal DISK ON CHIP 2000.Normal VSYNC ISACLK COMP SIPV DEVCLK SIRQ SPKRD HSYNC RTCAS VCLK PCICLKO CVBS PIRQ VDAC SDRQ BLUE MCLKI MCLKO , GPO ONE CAPACITOR FOR EACH COMPONENT PLACE NEAR 74AC00 74AC00 74AC00 74AC00 VSYNC HSYNC SDAVGA CVBS BLUE SCLVGA DCLK SDAVGA IOCHRDY DEVCLK DCLK SDRQ MCLKI VSYNC HSYNC SPKRD BCLK RSTDRV SDONE DSKCHG HDSEL MCLKO DENSEL SLCT BUSY MCLKO DCLK VCLK VSYNC HSYNC CVBS BLUE Part Reference Value PCB Footprint FBEAD BEAD TESTPIN 1ST PART www.datasheetarchive.com/download/9765178-847640ZC/rd120r11.zip (RD120R11.DSN) |
STMicroelectronics | 27/07/2000 | 618.5 Kb | ZIP | rd120r11.zip |
| BLUE VSYNC HSYNC CENTER SHIELD DISKONCHIP 2000.Normal DISKONCHIP 2000.Normal DISK ON CHIP 2000.Normal VSYNC ISACLK COMP SIPV DEVCLK SIRQ SPKRD HSYNC RTCAS VCLK PCICLKO CVBS PIRQ VDAC SDRQ BLUE MCLKI MCLKO , GPO ONE CAPACITOR FOR EACH COMPONENT PLACE NEAR 74AC00 74AC00 74AC00 74AC00 VSYNC HSYNC SDAVGA CVBS BLUE SCLVGA DCLK SDAVGA IOCHRDY DEVCLK DCLK SDRQ MCLKI VSYNC HSYNC SPKRD BCLK RSTDRV SDONE DSKCHG HDSEL MCLKO DENSEL SLCT BUSY MCLKO DCLK VCLK VSYNC HSYNC CVBS BLUE Part Reference Value PCB Footprint FBEAD BEAD TESTPIN 1ST PART www.datasheetarchive.com/download/9765178-847640ZC/rd120r11.zip (RD120R11.DBK) |
STMicroelectronics | 27/07/2000 | 618.5 Kb | ZIP | rd120r11.zip |