PC133 HYM71V32635AT8N HYM71V32635AT8N-K HYM71V32635AT8N-H HYM71V32635ALT8N-K - Datasheet Archive

 

PC133 SDRAM Unbuffered DIMM based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V32635AT8N Series DESCRIPTION The

 

32Mx64bits PC133 PC133 SDRAM Unbuffered DIMM based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V32635AT8N HYM71V32635AT8N Series DESCRIPTION The Hynix HYM71V32635AT8N HYM71V32635AT8N Series are 32Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V32635AT8N HYM71V32635AT8N Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM71V32635AT8N HYM71V32635AT8N Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES · PC133/PC100MHz support · SDRAM internal banks : four banks · 168pin SDRAM Unbuffered DIMM · Module bank : two physical bank · Serial Presence Detect with EEPROM · Auto refresh and self refresh · 1.25" (31.75mm) Height PCB with double sided components · 4096 refresh cycles / 64ms · Programmable Burst Length and Burst Type · Single 3.3±0.3V power supply · All device pins are compatible with LVTTL interface · Data mask function by DQM - 1, 2, 4 or 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst · Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency Internal Bank Ref. HYM71V32635AT8N-K HYM71V32635AT8N-K HYM71V32635AT8N-H HYM71V32635AT8N-H HYM71V32635ALT8N-K HYM71V32635ALT8N-K HYM71V32635ALT8N-H HYM71V32635ALT8N-H SDRAM Package Plating TSOP-II Power Gold Normal 133MHz 4 Banks 4K Low Power This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5/Dec. 01 2 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series PIN DESCRIPTION PIN PIN NAME DESCRIPTION CK0~CK3 Clock Inputs The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE0, CKE1 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh /S0 ~ /S3 Chip Select Enables or disables all inputs except CK, CKE and DQM BA0, BA1 SDRAM Bank Address Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS, /WE Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS and /WE define the operation Refer function truth table for details DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ63 Data Input/Output Multiplexed data input / output pin VCC Power Supply (3.3V) Power supply for internal circuits and input buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~2 SPD Address Input Serial Presence Detect Address Input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM NC No Connection No connection Rev. 0.5/Dec. 01 3 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series PIN ASSIGNMENTS FRONT SIDE PIN NO. BACK SIDE NAME PIN NO. NAME FRONT SIDE PIN NO. NAME BACK SIDE PIN NO. NAME CK1 1 VSS 85 VSS 41 VCC 125 2 DQ0 86 DQ32 42 CK0 126 NC 3 DQ1 87 DQ33 43 VSS 127 VSS 4 DQ2 88 DQ34 44 NC 128 CKE0 5 DQ3 89 DQ35 45 /S2 129 /S3 6 VCC 90 VCC 46 DQM2 130 DQM6 7 DQ4 91 DQ36 47 DQM3 131 DQM7 8 DQ5 92 DQ37 48 NC 132 NC 9 DQ6 93 DQ38 49 VCC 133 VCC 10 DQ7 94 DQ39 50 NC 134 NC 51 NC 135 NC 52 NC 136 NC 53 NC 137 NC Architecture Key 11 DQ8 95 DQ40 12 VSS 96 VSS 54 VSS 138 VSS 13 DQ9 97 DQ41 55 DQ16 139 DQ48 14 DQ10 98 DQ42 56 DQ17 140 DQ49 15 DQ11 99 DQ43 57 DQ18 141 DQ50 16 DQ12 100 DQ44 58 DQ19 142 DQ51 17 DQ13 101 DQ45 59 VCC 143 VCC 18 VCC 102 VCC 60 DQ20 144 DQ52 19 DQ14 103 DQ46 61 NC 145 NC 20 DQ15 104 DQ47 62 NC 146 NC 21 NC 105 NC 63 CKE1 147 NC 22 NC 106 NC 64 VSS 148 VSS 23 VSS 107 VSS 65 DQ21 149 DQ53 24 NC 108 NC 66 DQ22 150 DQ54 25 NC 109 NC 67 DQ23 151 DQ55 26 VCC 110 VCC 68 VSS 152 VSS 27 /WE 111 /CAS 69 DQ24 153 DQ56 28 DQM0 112 DQM4 70 DQ25 154 DQ57 29 DQM1 113 DQM5 71 DQ26 155 DQ58 30 /S0 114 /S1 72 DQ27 156 DQ59 31 NC 115 /RAS 73 VCC 157 VCC 32 VSS 116 VSS 74 DQ28 158 DQ60 33 A0 117 A1 75 DQ29 159 DQ61 34 A2 118 A3 76 DQ30 160 DQ62 35 A4 119 A5 77 DQ31 161 DQ63 36 A6 120 A7 78 VSS 162 VSS 37 A8 121 A9 79 CK2 163 CK3 38 A10/AP A10/AP 122 BA0 80 NC 164 NC 39 BA1 123 A11 81 WP 165 SA0 40 VCC 124 VCC 82 SDA 166 SA1 83 SCL 167 SA2 84 VCC 168 VCC Voltage Key Rev. 0.5/Dec. 01 4 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series BLOCK DIAGRAM Note : 1. The serial resistor values of DQs are 10ohms Rev. 0.5/Dec. 01 5 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIPTION FUNCTION VALUE -H -K -H -K BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 NOTE SDRAM 04h # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 10 0Ah BYTE5 # of Module Banks on This Assembly 2 Bank 02h BYTE6 Data Width of This Assembly 64 Bits 40h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @/CAS Latency=3 7.5ns 7.5 75h 75h BYTE10 BYTE10 Access Time from Clock @/CAS Latency=3 5.4ns 5.4 54h 54h BYTE11 BYTE11 DIMM Configuration Type BYTE12 BYTE12 Refresh Rate/Type BYTE13 BYTE13 None 00h 80h x8 08h None 00h Error Checking SDRAM Width BYTE15 BYTE15 Minimum Clock Delay Back to Back Random Column Address BYTE16 BYTE16 Burst Lenth Supported BYTE17 BYTE17 01h 15.625us / Self Refresh Supported Primary SDRAM Width BYTE14 BYTE14 LVTTL 1 # of Banks on Each SDRAM Device tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h BYTE18 BYTE18 SDRAM Device Attributes, /CAS Lataency BYTE19 BYTE19 SDRAM Device Attributes, /CS Lataency /CS Latency=0 01h BYTE20 BYTE20 SDRAM Device Attributes, /WE Lataency /WE Latency=0 01h BYTE21 BYTE21 SDRAM Module Attributes Neither Buffered nor Registered 00h +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 2 0Eh BYTE22 BYTE22 SDRAM Device Attributes, General BYTE23 BYTE23 SDRAM Cycle Time @/CAS Latency=2 7.5ns 10 75h A0h BYTE24 BYTE24 Access Time from Clock @/CAS Latency=2 5.4ns 6 54h 60h BYTE25 BYTE25 SDRAM Cycle Time @/CAS Latency=1 - - 00h 00h BYTE26 BYTE26 Access Time from Clock @/CAS Latency=1 - - 00h 00h BYTE27 BYTE27 Minimum Row Precharge Time (tRP) 15ns 20ns 0Fh 14h BYTE28 BYTE28 Minimum Row Active to Row Active Delay (tRRD) 15ns 15ns 0Fh 0Fh BYTE29 BYTE29 Minimum /RAS to /CAS Delay (tRCD) 15ns 20ns 0Fh 14h BYTE30 BYTE30 Minimum /RAS Pulse Width (tRAS) 45ns 45ns 2Dh 2Dh BYTE31 BYTE31 Module Bank Density BYTE32 BYTE32 Command and Address Signal Input Setup Time 1.5ns 1.5ns 15h 15h BYTE33 BYTE33 Command and Address Signal Input Hold Time 0.8ns 0.8ns 08h 08h BYTE34 BYTE34 Data Signal Input Setup Time 1.5ns 1.5ns 15h 15h BYTE35 BYTE35 Data Signal Input Hold Time 0.8ns 0.8ns 08h 08h BYTE36 BYTE36 ~61 Superset Information (may be used in future) BYTE62 BYTE62 SPD Revision BYTE63 BYTE63 Checksum for Byte 0~62 BYTE64 BYTE64 Manufacturer JEDEC ID Code BYTE65 BYTE65 ~71 .Manufacturer JEDEC ID Code BYTE72 BYTE72 Manufacturing Location Rev. 0.5/Dec. 01 128MB 128MB 20h - 00h Intel SPD1.2B 12h - 3, 8 B0h 6Fh Hynix JEDED ID ADh Unused FFh HSI (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) HSS(Singapore) Asia Area 0*h 1*h 2*h 3*h 4*h 5*h 11 6 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series Continued BYTE NUMBER FUNCTION DESCRIPTION FUNCTION VALUE -H -K -H -K NOTE BYTE73 BYTE73 Manufacturer's Part Number (Component) BYTE74 BYTE74 Manufacturer's Part Number (128Mb based) BYTE75 BYTE75 Manufacturer's Part Number (Voltage Interface) V (3.3V, LVTTL) 56h 4, 5 BYTE76 BYTE76 Manufacturer's Part Number (Memory Width) 3 33h 4, 5 BYTE77 BYTE77 .Manufacturer's Part Number (Memory Width) 2 32h 4, 5 BYTE78 BYTE78 Manufacturer's Part Number (Data Width) 6 36h 4, 5 BYTE79 BYTE79 .Manufacturer's Part Number (Data Width) 3 33h 4, 5 BYTE80 BYTE80 Manufacturer's Part Number (Refresh, SDRAM Bank) 5 (4K Refresh, 4Banks) 35h 4, 5 BYTE81 BYTE81 Manufacturer's Part Number (Generation) A 41h 4, 5 BYTE82 BYTE82 Manufacturer's Part Number (Package Type) BYTE83 BYTE83 Manufacturer's Part Number (Component Configuration) BYTE84 BYTE84 Manufacturer's Part Number(PCB Revision) BYTE85 BYTE85 Manufacturer's Part Number (Hyphent) BYTE86 BYTE86 Manufacturer's Part Number (Min. Cycle Time) BYTE87 BYTE87 ~90 Manufacturer's Part Number 7 (SDRAM) 37h 4, 5 1 31h 4, 5 T 54h 4, 5 8 (x8 based) 38h 4, 5 N 4Eh - (Hyphen) 2Dh K H 4Bh 4, 5 48h 4, 5 Blanks 20h 4, 5 BYTE91 BYTE91 Revision Code (for Component) Process Code - 4, 6 BYTE92 BYTE92 .Revision Code (for PCB) Process Code - 4, 6 BYTE93 BYTE93 Manufacturing Date Year - 3, 6 BYTE94 BYTE94 .Manufacturing Date Work Week - 3, 6 Serial Number - 6 None 00h 100MHz 64h 7, 8, 9 Refer to Note7 FFh 7, 8, 9 - 00h BYTE95 BYTE95 ~98 BYTE99 BYTE99 ~125 Assembly Serial Number Manufacturer Specific Data (may be used in future) BYTE126 BYTE126 System Frequency Support BYTE127 BYTE127 Intel Specification Details for 100MHz Support BYTE128 BYTE128 ~256 Unused Storage Locations Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for `HYM' in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0~CK3 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge suport 8. Refer to the most recent Intel and JEDEC SPD Specification 9. These values are applied to PC100 PC100 applications only per Intel PC SDRAM specification 10. In the case of L-Part, character `L' will be added between byte 81 and byte 82 11. Refer to HSI Web site Rev. 0.5/Dec. 01 7 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 16 W Soldering Temperature Time TSOLDER 260 10 °C Sec Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input Low voltage VIL -0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 0.5/Dec. 01 11 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series AC CHARACTERISTICS II -K Parameter -H Symbol Unit Min Max Min Note Max Operation tRC 60 - 65 - ns Auto Refresh tRRC 60 - 65 - ns RAS to CAS Delay tRCD 15 - 20 - ns RAS Active Time tRAS 45 100K 45 100K ns RAS Precharge Time tRP 15 - 20 - ns RAS to RAS Bank Active Delay tRRD 15 - 15 - ns CAS to CAS Delay tCCD 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - CLK Data-In to Precharge Command tDPL 2 - 2 - CLK Data-In to Active Command tDAL 4 - 5 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - CLK CAS Latency = 2 tPROZ2 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - CLK Refresh Time tREF - 64 - 64 ms RAS Cycle Time Precharge to Data Output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.5/Dec. 01 12 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series DEVICE OPERATING OPTION TABLE HYM71V32635A HYM71V32635A(L)T8N-K CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns HYM71V32635A HYM71V32635A(L)T8N-H CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns Rev. 0.5/Dec. 01 13 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series COMMAND TRUTH TABLE A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X No Operation H X X H X Note X Bank Active BA OP code Command Read H X X X L H H H L L H H ADDR X RA Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop H X L H L H X CA H X L H L L X CA H X L L H L X X H Read with Autoprecharge X L H H L X H L H V V H X L V X DQM H V X Auto Refresh H H L L L H X X Burst-Read-SingleWRITE H X L L L L X A9 Pin High (Other Pins OP code) H L X Entry Self Refresh1 Exit L X V L H Entry H L Exit L H Precharge power down Entry H L Exit Clock Suspend L H L L L H H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V X X MRS Mode X X X X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.5/Dec. 01 14 PC133 PC133 SDRAM Unbuffered DIMM HYM71V32635AT8N HYM71V32635AT8N Series PACKAGE DEMENSION Rev. 0.5/Dec. 01 15