HYM536A814A HY5117404A HYM536A814AM/ASLM HYM536A814AMG/ASLMG A0-A10 DQ0-DQ35

4Mx36-bit CMOS DRAM MODULE with EXTENDED DATA OUT DESCRIPTION The HYM536A814A is a 8M x 36-bit EDO mode CMOS DRAM module

HYM536A814A HYM536A814A M-Series 4Mx36-bit CMOS DRAM MODULE with EXTENDED DATA OUT DESCRIPTION The HYM536A814A HYM536A814A is a 8M x 36-bit EDO mode CMOS DRAM module consisting of eighteen HY5117404A HY5117404A in 24/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.1§ Þ and 0.01§ Þ decoupling are mounted for each DRAM. The HYM536A814AM/ASLM HYM536A814AM/ASLM are Tin-Lead plated and HYM536A814AMG/ASLMG HYM536A814AMG/ASLMG are Gold plated socket type Single In-line Memory Modules suitable for easy interchange and addition of 32M byte memory. FEATURES PIN CONNECTION · Low power dissipation Max. self-refresh 29.7W (SL-part) Max. battery back-up 59.4W (SL-part) Max. CMOS standby 39.6mW (SL-part) 99.0mW Max. TTL standby 198.0mW Max. operating Speed Power 60 6.04W 70 5.05W 80 4.55W · Single power supply of 5V±10% · TTL compatible inputs and outputs · Fast access time Speed tRAC tCAC tHPC 60 60ns 15ns 25ns 70 70ns 20ns 30ns 80 80ns 20ns 35ns · EDO mode operation · /CAS-before-/RAS, /RAS-only, Hidden refresh, Self-refresh · 2048 refresh cycles / 256ms (SL-part) 2048 refresh cycles / 32ms PIN CONNECTION /RAS0-/RAS1 /CAS0-/CAS1 /WE /OE A0-A10 A0-A10 DQ0-DQ35 DQ0-DQ35 PD1-PD5 VCC VSS Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input Data Input/Output Presence Detect Power (+5V) Ground This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. 1CF15-10-FEB95 1CF15-10-FEB95 HYM536A814A HYM536A814A M-Series PIN NAME BLOCK DIAGRAM # NAME # NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3 A4 A5 A6 /OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 NC NC DQ17 DQ18 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DQ19 DQ20 VSS /CAS0 A10 NC /CAS1 /RAS0 /RAS1 DQ21 /WE VSS DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 NC NC NC PD1 PD2 PD3 PD4 NC VSS PRESENCE DETECT PINS PIN PD1 PD2 PD3 PD4 PD5 -60 NC VSS NC NC VSS -70 NC VSS VSS NC VSS -80 NC VSS NC VSS VSS 1CF15-10-FEB95 1CF15-10-FEB95 2 HYM536A814A HYM536A814A M-Series ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature 0 to 70 ¡ É TSTG Storage Temperature -55 to 125 ¡ É VIN, VOUT Voltage on Any Pin Relative to VSS -1.0 to 7.0 V VCC Voltage on VCC Relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 18 W NOTE : Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA= 0¡ É 70¡ É to ) SYMBOL PARAMETER VCC Supply Voltage VIH Input High Voltage VIL Input Low Voltage NOTE : All voltages are referenced to VSS. 3 1CF15-10-FEB95 1CF15-10-FEB95 MIN. 4.5 2.4 -1.0 TYP. 5.0 - MAX. 5.5 VCC+1.0 0.8 UNIT V V V HYM536A814A HYM536A814A M-Series DC CHARACTERISTICS (TA=0¡ É 70¡ É VCC=5V±10%, VSS=0V, unless otherwise noted.) to , SYMBOL PARAMETER TEST CONDITIONS SPEED/ MIN. MAX. UNIT NOTE POWER ILI Input Leakage Current (Any Input Pin) VSS¡ Â IN¡ Â CC+1.0, V V All other pins not under test=VSS -180 180 ¥ ì A ILO Output Leakage Current (High impedance State) VSS¡ Â OUT¡ Âcc V v /RAS & /CAS at VIH -20 20 ¥ ì A VCC Supply Current tRC=tRC (min.) 60 - 1098 mA 70 - 918 80 - 828 - 36 mA 60 - 1098 mA 1,3 70 - 918 80 - 828 60 - 918 mA 1,2,3 70 - 828 80 - 738 ICC1 Operating ICC2 /RAS & /CAS at VIH, TTL Standby ICC3 VCC Supply Current other inputs VSS VCC Supply Current tRC=tRC(min.) /RAS-only refresh ICC4 VCC Supply Current, tHPC= tHPC (min.) EDO mode ICC5 VCC Supply Current /RAS & /CAS VCC - 0.2V VCC Supply Current - 18 - 7.2 60 - 1098 70 - 918 80 CMOS Standby ICC6 - 828 - 6.3 - 10.8 - SL-part tRC=tRC(min.) /CAS before /RAS refresh VCC Supply Current, tRC= 62.5µs, Tras Battery Back Up /CAS = CBR cycling or 0.2V, mA 5 mA 1,3 mA 1,4,5 5.4 mA 5 300ns (SL-part only) ICC7 1,2,3 /WE = VCC - 0.2V A0 - A10 = VCC - 0.2V or 0.2V tRAS DQ0 - DQ35 = VCC - 0.2V, 0.2V 1¥ ì s or open VCC Supply Current /RAS & /CAS 0.2V Self Refresh /OE & /WE & A0-A10 A0-A10= VCC-0.2V or 0.2V (SL-part only) ICC8 DQ0-DQ35 DQ0-DQ35= VCC-0.2V, 0.2V or open VOL Output Low Voltage IOL= 4.2mA - 0.4 V VOH Output High Voltage IOH= -5mA 2.4 - V NOTE 1. ICC1, ICC3, ICC4,ICC6 and ICC7 depend on cycle rate. 2. output loading. Specified values are obtained with the ouptup open. 3. ICC is specified as average current. For ICC1,ICC3 and ICC6 address can be changed maximum two times while /RAS=VIL. For ICC4, address can be changed maximum once while /CAS=VIH. 4. Only tRAS(max.)=1µs is applied to refresh of battery backup but tRAS(max.)=10µs is applied to normal functional operation. 5. ICC5(max.)=7.2mA, ICC7 and ICC8 are applied to SL-part only (HYM536A814ASLM/ASLMG HYM536A814ASLM/ASLMG) 1CF15-10-FEB95 1CF15-10-FEB95 4 HYM536A814A HYM536A814A M-Series AC CHARACTERISTICS (TA=0¡ É 70¡ É VCC= 5V± 10%, VSS= 0V, unless otherwise noted.) NOTE : 1,2,3 to , HYM536A814A HYM536A814A M-Series # SYMBOL PARAMTER -60 -70 -80 UNIT MIN. MAX. MIN. MAX. MIN. NOTE MAX. 1 tRC Random Read or Write Cycle Time 110 - 130 - 150 - 2 tRWC /RAS to /CAS Precharge Time 160 - 180 - 200 - ns 3 tHPC EDO Mode Cycle Time 20 - 30 - 35 - ns 4 tHPRWC Time from /CAS Precharge 85 - 90 - 100 - ns 5 tRAC Access Time from /RAS - 60 - 70 - 80 ns 6 tCAC Access Time from /CAS - 15 - 18 - 20 ns 4,9 7 tAA Access Time from Coulmn Address - 30 - 35 - 40 ns 4,10 8 tCPA Access Time from /CAS Precharge - 35 - 40 - 45 ns 4 9 tCLZ /CAS to Output Low Impedance 0 - 0 - 0 - ns 4 10 tCEZ Output Buffer Turn-off Delay 0 15 0 15 0 15 ns 5 11 tT Transition Time (Rise and Fall) 2 50 2 50 2 50 ns 3 12 tRP /RAS Precharge Time 40 - 50 - 60 - ns 13 tRAS /RAS Pulse Width 60 10K 70 10K 80 10K ns 14 tRASP /RAS Pulse Width (EDO Mode) 60 125K 70 125K 80 125K ns 15 tRSH /RAS Hold Time 15 - 18 - 20 - ns 16 tCSH /CAS Hold Time 40 - 50 - 60 - ns 17 tCAS /RAS Pulse Width 12 10K 15 10K 20 10K ns 18 tRCD /RAS to /CAS Delay 20 45 20 50 20 60 ns 9 19 tRAD /RAS to Column Address Delay Time 15 30 15 30 17 40 ns 10 20 tCRP /CAS to RAS Precharge Time 5 - 5 - 5 - ns 21 tCP /CAS Precharge Time 8 - 10 - 10 - ns 22 tASR Row Address Set-up Time 0 - 0 - 0 - ns 23 tRAH Row Address Hold Time 10 - 10 - 12 - ns 24 tASC Column Address Set-up Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 10 - 10 - 15 - ns 26 tAR Column Address Hold Time from /RAS 50 - 55 - 60 - ns 27 tRAL Column Address to /RAS Lead Time 30 - 35 - 40 - ns 28 tRCS Read Command Set-up Time 0 - 0 - 0 - ns 29 tRCH Read Command Hold Time Referenced to /CAS 0 - 0 - 0 - ns 6 30 tRRH Read Command Hold Time Referenced to /RAS 0 - 0 - 0 - ns 6 31 tWCH Write Command Hold Time 10 - 10 - 15 - ns 32 tWCR Write Command Hold Time from /RAS 45 - 50 - 55 - ns 33 tWP Write Command Pulse Width 10 - 10 - 15 - ns 34 tRWL Write Command to /RAS Lead Time 15 - 18 - 20 - ns 35 tCWL Write Command to /CAS Lead Time 15 - 18 - 20 - ns 36 tDS Data-In Set-up Time 0 - 0 - 0 - ns 7 37 tDH Data-In Hold Time 13 - 13 - 15 - ns 7 38 tDHR Data-In Hold Time Referenced to /RAS 50 - 55 - 60 - ns 39 tREF Refresh Period (2048 cycles) - 32 256 - 32 256 - 32 256 ms ms 12 40 tWCS Write Command Set-up Time 0 - 0 - 0 - ns 8 SL-part 5 1CF15-10-FEB95 1CF15-10-FEB95 ns 4,9,10 HYM536A814A HYM536A814A M-Series AC CHARACTERISTICS (continued) HYM536A814A HYM536A814A M-Series # SYMBOL PARAMTER -60 -70 -80 MIN. MAX. MIN. MAX. UNIT MIN. NOTE MAX. 41 tCWD /CAS to /WE Delay Time 38 - 43 - 45 - ns 8 42 tRWD /RAS to /WE Delay Time 83 - 95 - 105 - ns 8 43 tAWD Column Address to /WE Delay Time 53 - 60 - 65 - ns 8 44 tCSR /CAS Set-up Time (CBR Cycle) 5 - 5 - 5 - ns 45 tCHR /CAS Hold Time (CBR Cycle) 10 - 10 - 10 - ns 46 tRPC /RAS to /CAS Precharge Time 0 - 0 - 0 - ns 47 tCPT /RAS Precharge Time (CBR Counter Test) 20 - 25 - 25 - ns 48 tROH /RAS Hold Time Reference to /OE 0 - 0 - 0 - ns 49 tOEA /OE Access Time - 15 - 18 - 20 ns 50 tOED /OE to Data Delay 15 - 15 - 15 - ns 51 tOEZ Output Buffer Turn Off Delay Time from /OE 0 15 0 15 0 15 ns 52 tOEH /OE Command Hold Time 10 - 10 - 10 - ns 53 tCPWD /WE Delay Time from /CAS Precharge 60 - 65 - 70 - ns 54 tRHCP /RAS Hold Time from /CAS Precharge 35 - 40 - 45 - ns 55 tWRP /WE to /RAS Precharge Time (CBR Cycle) 10 - 10 - 10 - ns 56 tWRH /WE to /RAS Hold Time (CBR Cycle) 10 - 10 - 10 - ns 57 tRASS /RAS Pulse Width (Slef Refresh Cycle) 100 - 100 - 100 - ns 58 tRPS /RAS Precharge Time (Self Refresh Cycle) 110 - 130 - 150 - ns 59 tCHS /CAS Hold Time (Self Refresh Cycle) -50 - -50 - -50 - ns 60 tDOH Output Data Hold Time 3 - 3 - 3 - ns 61 tREZ Output Buffer Turn-off Delay (/RAS) - 15 - 15 - 15 ns 5,15 62 tWEZ Output Buffer Turn-off Delay (/WE) - 15 - 15 - 15 ns 5 63 tWPE /WE Pulse Width for Output Disable 10 - 10 - 10 - ns 64 tOEP /OE Pulse Width for Output Disable 10 - 10 - 10 - ns 65 tOCH /OE Low to /CAS High Delay Time 0 - 0 - 0 - ns 66 tCHO /CAS High to /OE High Hold Time 10 - 10 - 10 - ns 67 tWED /WE to Data Delay Time 15 - 15 - 15 - ns 5 8 1CF15-10-FEB95 1CF15-10-FEB95 6 HYM536A814A HYM536A814A M-Series NOTE : 1. An initial pause of 200§ Á required after power-up followed by 8 /RAS cycles before proper device operation is achieved. In case of is using internal refresh counter, a minimum of 8 /CAS-before-/RAS intilization cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented from being entered into multi bit test mode. 2. If /RAS= Vss during power-up, the HYM536A814A HYM536A814A could begin an active cycle. This conditionn results in higher power-up current than necessary demands from the power-up. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize the power-up current. 3. Refer to the HY5117404A HY5117404A data sheet for detailed information. 4. Measured with a load equivalent to 2 TTL loads and 100pF.(VOH=2.0V, VOL=0.8V) 5. tCEZ(max.).tOEZ(max.),tREZ(max.) and tWEZ(max.) define the time at which the output achiveds the open circuit condition and is not referenced to output voltage levels. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in late write or read-modify-write Cycles. 8. tWCS is not a restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) throught the entire cycle 9. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11. Measured with the specified current load and 100pF. 12. A burst of 2048 /CAS-before-/RAS refresh cycles must bwe executed within 32ms after existing self refresh ( for SL-part). 13. If tCWD tWCS(min.) tRWDtRWD(min.), tAWDtAWD(min.) and tCPWDtCPWD(min.), the cycle is a read modify write cycle and the data output will contain data read from the selected cell. If neighter of the above conditions are met, the condition of the data out ( at access time and until /CAS goes back to VIH ) is indeterminated. 14. In /CAS before /RAS self refresh mode. In case of using distributed /CAS before /RAS refresh, refresh 1024 times during a 256ms after reset In case of using burst /CAS before /RAS refresh, refresh 1024 times during a 32ms after reset In case of using /RAS only refresh, refresh against all refresh address during a 32ms after rese 15. If /RAS goes to high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going. If /CAS goes to high before /RAS high going, the open circuit condition of the output is achieved by /RAS high going. CAPACITANCE (TA=25¡ É Vcc=5V± 10%, Vss=0V, f=1MHz, unless otherwise noted.) , SYMBOL PARAMETER MAX. UNIT Input Capacitance (A0-A10 A0-A10) - 125 pF CIN2 Input Capacitance (/WE, /OE) - 145 pF CIN3 Input Capacitance (/RAS0-/RAS1) - 72 pF CIN4 Input Capacitance (/CAS0-/CAS1) - 72 pF CDQ 7 TYP. CIN1 Data Input/output Capacitance (DQ0-DQ35 DQ0-DQ35) - 25 pF 1CF15-10-FEB95 1CF15-10-FEB95 HYM536A814A HYM536A814A M-Series PACKAGE DIMENSION 72pin Single Inline Memory Module (M; Tin-Lead plated, MG; Gold plated) HYM536A814A/ASL HYM536A814A/ASL (SOJ Mounted) 1CF15-10-FEB95 1CF15-10-FEB95 8 HYM536A814A HYM536A814A M-Series ORDERING INFORMATION PART NUMBER SPEED HYM536A814AM HYM536A814AM 60/70/80 HYM536A814AMG HYM536A814AMG HYM536A814ASLMG HYM536A814ASLMG 60/70/80 9 1CF15-10-FEB95 1CF15-10-FEB95 SL-part PLATING Tin-Lead SIMM Tin-Lead SIMM 60/70/80 SL-part PACKAGE SIMM 60/70/80 HYM536A814ASLM HYM536A814ASLM POWER Gold SIMM Gold