HYM328025S/GS-50/-60 L-SIM-72-15 328025S/GS-50/-60 5117405BJ 328025S/GS-60/-70 - Datasheet Archive

 

HYM328025S/GS-50/-60 Preliminary Information · 8 388 608 words by 32-bit organization · Fast access and cycle time

 

8M × 32-Bit EDO-DRAM Module HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 Preliminary Information · 8 388 608 words by 32-bit organization · Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) · Hyper page mode (EDO) capability 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) · Single + 5 V (± 10 %) supply · Low power dissipation max. 5280 mW active (-50 version) max. 4840 mW active (-60 version) CMOS ­ 88 mW standby TTL ­176 mW standby · CAS-before-RAS refresh RAS-only-refresh Hidden-refresh · 16 decoupling capacitors mounted on substrate · All inputs, outputs and clocks fully TTL compatible · 72 pin Single in-Line Memory Module (L-SIM-72-15 L-SIM-72-15) with 25.40 mm height · Utilizes sixteen 4Mx4-DRAMs in SOJ packages · 2048 refresh cycles / 32 ms · Optimized for use in byte-write non-parity applications · Tin-Lead contact pads (S- version) · Gold contact pads (GS -version) Semiconductor Group 1 11.95 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module The HYM 328025S/GS-50/-60 328025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 32-bit in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 5117405BJ 4M × 4 DRAMs in 300 mil wide SOJ-packages mounted together with sixteen 0.2 µF ceramic decoupling capacitors on a PC board. Each HYB 5117405BJ 5117405BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 328025S/GS-60/-70 328025S/GS-60/-70 dictates the use of early write cycles. Ordering Information Type Ordering Code Package Description HYM 328025S-50 328025S-50 L-SIM-72-15 L-SIM-72-15 EDO-DRAM Module (access time 50 ns) HYM 328025S-60 328025S-60 L-SIM-72-15 L-SIM-72-15 EDO-DRAM Module (access time 60 ns) HYM 328025GS-50 328025GS-50 Q67100-Q2098 Q67100-Q2098 L-SIM-72-15 L-SIM-72-15 EDO-DRAM Module (access time 50 ns) HYM 328025GS-60 328025GS-60 Q67100-Q2099 Q67100-Q2099 L-SIM-72-15 L-SIM-72-15 EDO-DRAM Module (access time 60 ns) Semiconductor Group 2 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module Pin Configuration Pin Names VSS DQ16 DQ17 DQ18 DQ19 N.C. A1 A3 A5 A10 DQ20 DQ21 DQ22 DQ23 N.C A8 RAS3 N.C. 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 N.C. 36 N.C. VSS CAS2 CAS1 RAS1 WE 47 DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 PD0 PD2 N.C. 37 N.C. 38 39 CAS0 40 41 CAS3 42 43 RAS0 44 45 N.C. 46 N.C. 48 49 DQ24 50 51 DQ25 52 53 DQ26 54 55 DQ27 56 57 DQ28 58 59 DQ29 60 61 DQ30 62 63 DQ31 64 65 N.C. 66 67 PD1 68 69 PD3 70 71 VSS 72 Semiconductor Group A0-A10 A0-A10 Address Inputs DQ0-DQ31 DQ0-DQ31 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0- RAS3 Row Address Strobe WE Read/Write Input VCC VSS Power (+ 5 V) PD Presence Detect Pin N.C. No Connection Ground Presence Detect Pins -50 PD0 N.C. N.C. PD1 VSS VSS PD2 VSS N.C. PD3 3 -60 VSS N.C. HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module RAS0 RAS1 CAS0 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D1 CAS RAS I/O1-I/O4 OE D3 CAS RAS I/O1-I/O4 D2 OE DQ8-DQ11 DQ8-DQ11 CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D5 DQ12-DQ15 DQ12-DQ15 CAS RAS I/O1-I/O4 OE D7 CAS RAS I/O1-I/O4 OE D6 DQ0-DQ3 DQ4-DQ7 CAS1 RAS3 RAS2 CAS2 CAS RAS I/O1-I/O4 OE D8 CAS RAS I/O1-I/O4 OE D9 CAS RAS I/O1-I/O4 OE D11 CAS RAS I/O1-I/O4 D10 OE DQ24-DQ27 DQ24-DQ27 CAS RAS I/O1-I/O4 OE D12 CAS RAS I/O1-I/O4 OE D13 DQ28-DQ31 DQ28-DQ31 CAS RAS I/O1-I/O4 D15 OE CAS RAS I/O1-I/O4 D14 OE DQ16-DQ19 DQ16-DQ19 DQ20-DQ23 DQ20-DQ23 CAS3 A0 - A10 WE VCC D0 - D15 D0 - D15 C0 - C15 VSS Block Diagram Semiconductor Group 4 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module Absolute Maximum Ratings Operation temperature range . 0 to + 70 °C Storage temperature range. ­ 55 to 125 °C Input/output voltage .­0.5V to min (Vcc+0.5, 7.0) V Power supply voltage. ­ 1 to + 7 V Power dissipation. 6.72 W Data out current (short circuit) . 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VCC = 5 V ± 10 % Parameter Symbol Limit Values Unit Test Condition min. max. 2.4 Vcc+0.5 V 1) Input low voltage VIH VIL ­ 0.5 0.8 V 1) Output high voltage (IOUT = ­ 5 mA) VOH 2.4 ­ V 1) Output low voltage (IOUT = 4.2 mA) VOL ­ 0.4 V 1) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) ­ 20 20 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) ­ 10 10 µA 1) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -50 version -60 version ICC1 ­ ­ 960 880 mA mA 2) 3) 4) Standby VCC supply current (RAS = CAS = VIH) ICC2 ­ 32 mA Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -50 version -60 version ICC3 ­ ­ 960 880 mA mA Input high voltage Semiconductor Group 5 2) 4) HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module DC Characteristics1) (cont'd) Parameter Symbol Limit Values Unit Test Condition min. ­ ­ ICC5 Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -50 version -60 version mA mA 2) 3) 4) ­ 16 mA 1) 960 880 mA mA 2) 4) ICC4 Standby VCC supply current (RAS = CAS = VCC ­ 0.2 V) 560 440 ­ ­ Average VCC supply current during hyper page mode (EDO) (RAS = VIL, CAS, address cycling, tPC = tPC min) -50 version -60 version max. ICC6 Capacitance TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. Unit max. Input capacitance (A0 to A10,WE) CI1 ­ 120 pF Input capacitance (RAS0 - RAS3) CI2 CI3 ­ 45 pF ­ 40 pF CIO ­ 25 pF Input capacitance (CAS0 - CAS3) I/O capacitance (DQ0-DQ31 DQ0-DQ31) Semiconductor Group 6 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 Unit Note -60 min. max. min. max. common parameters Random read or write cycle time tRC 84 ­ 104 ­ ns RAS precharge time tRP 30 ­ 40 ­ ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 8 10k 10 10k ns Row address setup time tASR 0 ­ 0 ­ ns Row address hold time tRAH 8 ­ 10 ­ ns Column address setup time tASC 0 ­ 0 ­ ns Column address hold time tCAH 8 ­ 10 ­ ns RAS to CAS delay time tRCD 12 37 14 45 ns RAS to column address delay time tRAD 10 25 12 30 ns RAS hold time tRSH 13 15 ­ ns CAS hold time tCSH 50 60 ­ ns CAS to RAS precharge time tCRP 5 ­ 5 ­ ns Transition time (rise and fall) tT 1 50 1 50 ns Refresh period tREF ­ 32 ­ 32 ms Access time from RAS tRAC ­ 50 ­ 60 ns 8, 9 Access time from CAS tCAC ­ 13 ­ 15 ns 8, 9 Access time from column address tAA ­ 25 ­ 30 ns 8,10 Column address to RAS lead time tRAL 25 ­ 30 ­ ns Read command setup time tRCS 0 ­ 0 ­ ns Read command hold time tRCH 0 ­ 0 ­ ns 11 Read command hold time referenced to RAS tRRH 0 ­ 0 ­ ns 11 CAS to output in low-Z tCLZ 0 ­ 0 ­ ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 7 Read Cycle Semiconductor Group 7 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module AC Characteristics (cont'd) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 Unit Note -60 min. max. min. max. Early Write Cycle Write command hold time tWCH 8 ­ 10 ­ ns Write command pulse width tWP 8 ­ 10 ­ ns Write command setup time tWCS 0 ­ 0 ­ ns Write command to RAS lead time tRWL 13 ­ 15 ­ ns Write command to CAS lead time tCWL 13 ­ 15 ­ ns Data setup time tDS 0 ­ 0 ­ ns 14 Data hold time tDH 8 ­ 10 ­ ns 14 Hyper page mode (EDO) cycle time tHPC 20 ­ 25 ­ ns CAS precharge time tCP 8 ­ 10 ­ ns Access time from CAS precharge tCPA ­ 27 ­ 32 ns Output data hold time tCOH 5 ­ 5 ­ ns RAS pulse width in hyper page mode tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHCP 27 ­ 32 ­ ns CAS setup time tCSR 10 ­ 10 ­ ns CAS hold time tCHR 10 ­ 10 ­ ns RAS to CAS precharge time tRPC 5 ­ 5 ­ ns Write to RAS precharge time tWRP 10 ­ 10 ­ ns Write hold time referenced to RAS tWRH 10 ­ 10 ­ ns 13 Hyper Page Mode (EDO) Cycle CAS before RAS Refresh Cycle Semiconductor Group 8 7 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module Notes: 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 50 pF, (Vol = 0.8 V and Voh = 2.0 V) . 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge. Semiconductor Group 9 HYM328025S/GS-50/-60 HYM328025S/GS-50/-60 8M × 32-Bit EDO-Module Package Outline 107.95 101.19 8.89 max R1.57 10.16 6.35 25.40 3.18 3.38 1.27 R 1.57 +/- 0.05 6.35 +/- 0.05 2.03 6.35 95.25 +/- 0.05 1.27 +0.10 -0.08 0.25 max 2.54 min Detail of Contacts 1.27 1.04 +/- 0.05 file: LSIM7215 LSIM7215.DRW/WMF Tolerances : +/- 0.13 unless otherwise specified Module Package, L-SIM-72-15 L-SIM-72-15 (Single in-Line Memory Module) Semiconductor Group 10 Dimensions in mm GLS05859 GLS05859