HY5RS123235FP A3/A8/A9/A10 12/J1 HY5RS123235 A0-A11 HY5RS123235FP-11 - Datasheet Archive
512M (16Mx32) GDDR3 SDRAM HY5RS123235FP This document is a general product description and is subject to change without notice.
HY5RS123235FP HY5RS123235FP 512M (16Mx32) GDDR3 SDRAM HY5RS123235FP HY5RS123235FP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 / Apr. 2006 1 HY5RS123235FP HY5RS123235FP Revision History Revision No. History Draft Date 0.1 Defined target spec. Mar. 2004 Remark 0.2 Page 11) Add Cas Latency 11 Page 14) Write Latency definitions Page15) DI, WR_A, AL definitions Page47) Table18 typo corrected Page48) Table19 renewered Page50) note 46 added JULY.2004 CL WL DI/WR_A/AL Speed BIN Several Parameters tRPRE 0.3 Page4) Ballout configurations correct Appendix C) BST function description Aug.2004 A3/A8/A9/A10 A3/A8/A9/A10 0.4 - Non-Consectutive Read to Write timing clarifications - Read to Precharge timing Clarifications Sep.24,2004 Page28 page41 Page23 0.5 - Modified the pin descriptions and added command description for BST - Added the LP mode feature for EMRS Nov.8,2004 Page4,6,21 0.6 -Added the Lead free package part number and Package dimension page Jan.31,2005 Page3,56 1.0 - Clarified the ODT control and Data terminator disable command and its duration timing - Modify the Data termination disable mode note of EMRS - Modified the PIN description of VDDA/ VSSA(K1,12/J1 12/J1,12) - Changed the tPDIX, from 4tCK to 6tCK - Changed the tXSRD, from 300tCk to 1000tCK - Added the tCJC definition - IDD spec update - DC spec Update Apr.30,2005 Page 15,20 Page15,16 Page 9 Page 4,7 Page 47 Page 48 page 48 page 46 Table 12 1.1 VDD/VDDQ change, 500Mhz Speed Bin Insert, IDD value tuning Jun. 2005 & typo corrected 1.2 VDD/VDDQ Change at 600MHz speed bin to 1.8V from 2.0V Nov. 2005 1.3 900MHz speed bin insert Feb. 2006 1.4 VDD/VDDQ change for 800MHz speed bin & IDD value change Mar. 2006 1.5 Changed Async parameter at 700/800/900MHz speed bin (tRAS/tRC/tRFC/tRCDW/tRP/tDAL) Rev. 1.5 / Apr. 2006 Apr. 2006 2 HY5RS123235FP HY5RS123235FP DESCRIPTION The Hynix HY5RS123235 HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The Hynix HY5RS123235 HY5RS123235 is internally configured as a eight-bank DRAM. The Hynix HY5RS123235 HY5RS123235 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix HY5RS123235 HY5RS123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix HY5RS123235 HY5RS123235 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS123235 HY5RS123235 must be initialized. FEATURES · 2.2V +/-0.1V VDD/VDDQ power supply supports 900 / center-aligned with data for WRITE 800MHz · Eight internal banks for concurrent operation 2.0V VDD/ VDDQ wide range min/max power supply · Data mask (DM) for masking WRITE data supports 700MHz · 4n prefetch 1.8V VDD/ VDDQ wide range min/max power supply · Programmable burst lengths: 4, 8 supports 500 / 600MHz · 32ms, 8K-cycle auto refresh · Single ended READ Strobe (RDQS) per byte · Auto precharge option · Single ended WRITE Strobe (WDQS) per byte · Auto Refresh and Self Refresh Modes · Internal, pipelined double-data-rate (DDR) architecture; · 1.8V Pseudo Open Drain I/O two data accesses per clock cycle · Concurrent Auto Precharge support · Calibrated output driver · tRAS lockout support, Active Termination support · Differential clock inputs (CK and CK#) · Programmable Write latency(1, 2, 3, 4, 5, 6) · Commands entered on each positive CK edge · Boundary Scan Feature for connectivity test(refer to JEDEC · RDQS edge-aligned with data for READ; with WDQS · · std., not in this version of Specifications) ORDERING INFORMATION Part No. HY5RS123235FP-11 HY5RS123235FP-11 HY5RS123235FP-12 HY5RS123235FP-12 HY5RS123235FP-14 HY5RS123235FP-14 HY5RS123235FP-16 HY5RS123235FP-16 HY5RS123235FP-2 HY5RS123235FP-2 Power Supply VDD=2.2V, VDDQ=2.2V VDD=2.0V, VDDQ=2.0V VDD=1.8V, VDDQ=1.8V Clock Frequency Max Data Rate 900MHz 1800Mbps/pin 800MHz 1600Mbps/pin 700MHz 1400Mbps/pin 600MHz 1200Mbps/pin 500MHz Interface Package POD_18 12mmx14mm 136Ball FBGA 1000Mbps/pin Note) HY5RS123235FP-xx is the Lead Free Package part number Rev. 1.5 / Apr. 2006 3 HY5RS123235FP HY5RS123235FP BALLOUT CONFIGURATION 1 2 3 4 9 10 11 12 A VDDQ VDD VSS ZQ MF VSS VDD VDDQ B VSSQ DQ0 DQ1 VSSQ VSSQ DQ9 DQ8 VSSQ C VDDQ DQ2 DQ3 VDDQ VDDQ DQ11 DQ10 VDDQ D VSSQ W DQS0 RDQS0 VSSQ VSSQ RDQS1 W DQS1 VSSQ E VDDQ DQ4 DM0 VDDQ VDDQ DM1 DQ12 VDDQ F VDD DQ6 DQ5 CAS# CS# DQ13 DQ14 VDD G VSS VSSQ DQ7 BA0 BA1 DQ15 VSSQ VSS H VREF A1 RAS# CKE W E# BA2 A5 VREF J VSS NC RFU VDDQ VDDQ CK# CK VSS K VDD A10 A2 A0 A4 A6 A8/AP VDD L VSS VSSQ DQ25 A11 A7 DQ17 VSSQ VSS M VDD DQ24 DQ27 A3 A9 DQ19 DQ16 VDD N VDDQ DQ26 DM3 VDDQ VDDQ DM2 DQ18 VDDQ P VSSQ W DQS3 RDQS3 VSSQ VSSQ RDQS2 W DQS2 VSSQ R VDDQ DQ28 DQ29 VDDQ VDDQ DQ21 DQ20 VDDQ T VSSQ DQ30 DQ31 VSSQ VSSQ DQ23 DQ22 VSSQ U VDDQ VDD VSS RES VSS VDD VDDQ SEN 5 6 7 8 16M x 32 Configuration Refresh Count 8k Bank Address BA0 - BA2 Row Address A0~A11 Column Address A0~A7, A9 AP Flag Rev. 1.5 / Apr. 2006 2M x 32 x 8 banks A8 4 HY5RS123235FP HY5RS123235FP FUNCTIONAL BLOCK DIAGRAM 8Banks x 2Mbit x 32 I/O Double Data Rate Synchronous DRAM CKE CK CK# COMMAND DECODE CS# RAS# CAS# CONTROL LOGIC WE# MODE REGISTERS REFRESH COUNTER 12 ROW ADDRESS MUX 15 12 12 BANK8 BANK6 BANK5 BANK4 BANK3 BANK0 BANK2 BANK1 ROW ADDRESS LATCH BANK0 & ROW DECODER ADDRESS 40% LATCH & DECODER BANK7 BANK6 BANK5 BANK4 BANK3 BANK2 BANK1BANK0 MEMORY ARRAY (4096x512x128) BANK0 MEMORY ARRAY (4096x512x128) SENSE AMPLIFIERS CK/ CK# CCL0, CCL1 DLL 32 READ LATCH 128 32 32 32 MUX DRVRS DATA 32 DQ0~DQ32 SENSE AMPLIFIERS 66,536 A0~A11 BA0- BA2 15 4 128 CK/CK# 7 CK IN 2 COL0, COL1 Rev. 1.5 / Apr. 2006 CK OUT 4 32 32 COLUMN DECODER 4 32 32 32 32 128 4 4 MASK 32 128 DATA WCK(0~3) 4 32 WRITE FIFO & DRIVERS 512 (x128) 9 4 16 3 COLUMN ADDRESS COUNTER LATCH 4 4 I/O GATING DM MASK LOGIC BANK CONTROL LOGIC ADDRESS REGISTER CK/CK# INPUT REGISTERS 3 RCVRS DM(0~3) 32 4 5 HY5RS123235FP HY5RS123235FP BALLOUT DESCRIPTIONS FBGA BALLOUT SYMBOL TYPE DESCRIPTION J10, J11 CK, CK# Input Clock: CK and Ck# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. H4 CKE F9 CS# Input Chip Select: CS# enables (registered LOW)and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. H3, F4, H9 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE#(along with CS#) define the command being entered. E(3, 10), N(3, 10) DM0-DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on rising and falling edges of WDQS. G(4, 9), H10 BA0 - BA2 Input Bank Address Inputs: BA0 and BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit(A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0 - BA2 ) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. H(2, 11), K(2-4, 9-11), L(4, 9), M(4, 9) A0-A11 A0-A11 Input B(2, 3), C(2, 3), E2, F(2, 3), G3,B(10, 11), C(10, 11), E11, F(11, 19), G10, L10, M(10, 11), N11, R(10, 11), T(10,11), L3, M(2, 3), N2,R(2, 3), T(2, 3) DQ0-31 DQ0-31 I/O D(3, 10), P(3, 10) RDQS0-3 Output READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. D(2, 11), P(2, 11) WDQS0-3 Input WRITE Data strobe: Input with write data. WDQS is center aligned to the input data. U4 SEN Input Scan Enable Pin. Logic High would enable Scan Mode. Should be tied to GND when not in use. This pin is a CMOS input. J(2, 3) NC/RFU Rev. 1.5 / Apr. 2006 Data Input/Output: No Connect 6 HY5RS123235FP HY5RS123235FP BALLOUT DESCRIPTIONS -CONTINUE FBGA Ball Out SYMBOL TYPE DESCRIPTION A(1, 12), C(1, 4, 9, 12), J(4, 9), N(1, 4, 9, 12), R(1, 4, 9, 12), U(1, 12) VDDQ Supply B(1, 4, 9, 12), D(1, 4, 9, 12), G(2, 11), L(2, 11), P(1, 4, 9, 12), T(1, 4, 9, 12) VSSQ Supply A(2, 11), F(1, 12), M(1, 12), U(2, 11) K(1, 12) VDD Supply Power Supply: +1.8V. A(3, 10), G(1, 12), L(1, 12), U(3, 10) J(1, 12) VSS Supply Ground H(1, 12) VREF Supply Reference voltage. A9 MF Reference Mirror Function for clamshell mounting of DRAMs A4 ZQ Reference External Reference Pin for autocalibration. It should be connected to RQ(=240) U9 RES Reference Reset Pin. The RES pin is a VDD CMOS input. DQ Power Supply: +1.8V. Isolated on the die for improved noise immunity. DQ Ground: Isolated on the die for improved noise immunity. Mirror Function The GDDR3 SDRAM provides a mirror function(MF) ball to change the physical location of the control lines and all address lines, assisting in routing devices back to back. The MF ball will affect RAS#, CAS#, WE#, CS# and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input. The MF ball should be tied directly to VSS of VDD depending on the control line orientation desired. When MF ball is tied low the ball orientation is as follows. RAS#-H3, CAS#-F4, WE#-H9, CS#-F9, CKE-H4, A0-K4, A1-H2, A2-K3, A3M4, A4-K9, A5-H11 A5-H11, A6-K10 A6-K10, A7-L9, A8-K11 A8-K11, A9-M9, A10-K2 A10-K2, A11-L4 A11-L4, BA0-G4, BA1-G9 and BA2-H10 BA2-H10. The high condition on the MF ball will change the location of the control balls as follows; CS#-F4, cas#-F9, ras#-H10, WE#-H4, CKE-H9, A0-K9, A1-H11 A1-H11, A2-K10 A2-K10, A3-M9, A4-K4, A5-H2, A6-K3, A7-L4, A8-K2, A9-M4, A10-K11 A10-K11, A11-L9 A11-L9, BA0-G9, BA1-G4 and BA2-H3. This Mirror Fuction does not work under Boundary Scan Test condition. Mirror Function Signal Mapping PIN RAS# CAS# WE# CS# CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 BA2 Rev. 1.5 / Apr. 2006 MF LOGIC STATE HIGH LOW H10 F9 H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 L4 K2 M4 K11 L9 G9 G4 H3 H3 F4 H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 H10 7 HY5RS123235FP HY5RS123235FP GDDR3 Initialization and Power Up GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must be first applied to VDD and VDDQ simultaneously or VDD first and VDDQ later, and then to VREF. VREF can be applied any time after VDDQ. Once power has been applied and the clocks are stable the GDDR3 device requires 200us before the RES pin transitions to high. Upon power-up and after the clock is stable, the on-die termination value for the address and control pins will be set, based on the state of CKE when the RES pin transitions from LOW to HIGH. On the rising edge of RES, the CKE pin is latched to determine the on die termination value for the address and control lines. If CKE is sampled at a logic LOW then the on die termination will be set to 1/2 of ZQ and, if CKE is sampled logic HIGH then the on die termination will be set to the same value as ZQ. CKE must meet tATS and tATH on the rising of RES to set the on die termination for address and control lines. Once tATH is met, set CKE to HIGH. An additional 200us is required for the address and command on die terminations to calibrate and update. RES must be maintained at a logic LOW-level value and CS# must be maintained HIGH, during the first stage of power-up to ensure that the DQ outputs will be in a High-Z state(un-terminated). After the RES pin transitions from LOW to HIGH, wait until a 200us delay is satisfied. Issue DESELECT on the command bus during this time. Issue a PRECHARGE ALL command. Next a LOAD MODE REGISTER command must be issued for the extended mode register (BA1 LOW and BA0 HIGH) to activate the DLL and set operating parameters, followed by the LOAD MODE REGISTER command (BA0/BA1 both LOW) to reset the DLL and to program the rest of the operating parameters. 20k clock cycles are required between the DLL reset and any READ command to allow the DLL to lock. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be issued. Following these requirements, the GDDR3 SDRAM is ready for normal operation. Rev. 1.5 / Apr. 2006 8 HY5RS123235FP HY5RS123235FP ODT Updating The GDDR3 SDRAM uses a programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and VSSQ. The value of the resistor must be six times the desired driver impedance. For example, a 240. resistor is required for an output impedance of 40. To ensure that output impedance is one-sixth the value of RQ (within 10 percent), RQ should be in the range of 210. to 270. (30. 50. output impedance). CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The output impedance and on die termination is updated during every AUTO REFRRESH commands to compensate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all datasheet timings and current specifications are met during an update. A maximum of eight AUTO REFRESH commands can be posted to any given GDDR3 SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x 3.9us (31.2us). This maximum absolute interval guarantees that the output drivers and the on die terminations of GDDR3 SDRAMs are recalibrated often enough to keep the impedance characteristics of those within the specified boundaries. ODT Control Bus snooping for READ commands other than CS# is used to control the on die termination in the dual load configuration. The GDDR3 SGRAM will disable the DQ and RDQS on die termination when a READ command is detected regardless of the state of CS#. The on die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2+2CK. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on die termination, for the DQ and DQS pins if a READ command is detected. The on die termination for all other pins on the device is always turned-on for both a single-rank system and a dual-rank system unless it is turned off in the EMRS. Only DQ,WDQS,RDQS and DM pins can turn off through the EMRS. Rev. 1.5 / Apr. 2006 9 HY5RS123235FP HY5RS123235FP Mode Register Definition The mode register is used to define the specific mode of operation of the GDDR3 SDRAM. This definition includes the selection of a burst length, CAS latency, WRITE latency, and operating mode, as shown in Figure 3, Mode Register Definition, on page 11. The mode register is porgrammed via the MODE REGISTER SET command (with BA0=0, BA1=0 and BA2=0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Re-programming the mode register will not alter the contents of the memory. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A2-A0 specify the burst length; A3 specifies the type of burst (sequential); A4-A6 specify the CAS latency; A7 is a test mode; A8 specifies the operating mode; and A9-A11 A9-A11 specifiy the WRITE latency. Rev. 1.5 / Apr. 2006 10 HY5RS123235FP HY5RS123235FP Figure 3: Mode Register Definition BA2 BA1 BA0 0 0 A11 0 A10 A9 A8 DLL WL A11 A10 A9 0 0 RFU 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 0 1 1 0 6 1 1 1 RFU A4 A3 CAS Latency 5 1 TM A5 4 1 A6 A2 BT A1 A0 Burst Length WRITE Latency 0 A7 A7 Test Mode A2 A1 A0 Burst Length 0 Normal 0 0 0 RFU 1 Test Mode 0 0 1 RFU 0 1 0 4 0 1 1 8 1 0 0 RFU 1 0 1 RFU 1 1 0 RFU 1 1 1 RFU A8 DLL Reset 0 No 1 Yes 1) A6 A5 A4 CAS Latency A3 Burst Type 0 0 0 8 0 Sequential 0 0 1 9 1 RFU 0 1 0 10 0 1 1 11 1 0 0 RFU 1 0 1 5 1 1 0 6 1 1 1 7 Note: 1) The DLL reset command is self-clearing. 2) For the each of RFU code means Reserved for Future Use, however with this version, RFU of Burst Length is programmed BL=4, Burst type is Sequential, Cas Latency is CL=5 and Write Latency is 1. Rev. 1.5 / Apr. 2006 11 HY5RS123235FP HY5RS123235FP Burst Length Read and write accesses to the GDDR3 SDRAM are burst-oriented, with the burst length being programmable, as shown in Figure3, Mode Register Definition. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 4 or 8 locations are available for the sequential burst type. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2. Ai when the burst length is set to four and by A3. Ai when the burst length is set to eight(where Ai is the most significant column address bit for a given configuration). The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3. This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table3. Table 3: Burst Definition Burst1, 2 Length Starting Column Address Order of Accesses Within a Burst Type=Sequential A1 A0 0 0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 1 0 0 4-5-6-7-0-1-2-3 4 8 0-1-2-3 NOTE: 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero. 2. For a burst length of eight, A3-A7 select the of eight burst; A0-A2 select the starting column within the block. Rev. 1.5 / Apr. 2006 12 HY5RS123235FP HY5RS123235FP CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 5-11 clocks, as shown in Figure 4, CAS Latency, on page 13. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table4 indicates the operating frequencies at which each CAS latency setting can be used. For the proper operation, do not change the CL without DLL reset. Or proper CL should be set with DLL reset code Reserved states should not be used as unknown operation or incompatibility with future versions may result. Table 4: CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) SPEED CL=11 CL=10 -11 900