HV5522 HV5522PG-G HV5522PJ-G -40OC -65OC 150OC 260OC HV5522PG HV5522PJ HVOUT11 - Datasheet Archive

 

32-Channel Serial to Parallel Converter With Open Drain Outputs Features General Description The HV5522 is a low-voltage serial

 

HV5522 HV5522 32-Channel Serial to Parallel Converter With Open Drain Outputs Features General Description The HV5522 HV5522 is a low-voltage serial to high-voltage parallel converter with open drain outputs. This device has been designed for use as a driver for AC-electroluminescent displays. It can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum fluorescent, or large matrix LCD displays. Processed with HVCMOS® technology Sink current minimum 100mA Shift register speed 8.0MHz Polarity and Blanking inputs CMOS compatible inputs Forward and reverse shifting options Diode to VPP allows efficient power recovery This device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low transition of the clock. The HV5522 HV5522 shifts in the counter clockwise direction when viewed from the top of the package. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low. Functional Block Diagram Polarity Blanking Latch Enable HV OUT 1 Data Input Latch HV OUT 2 Clock Latch 32-Bit Shift Register (Outputs 3 to 30 not shown) HV OUT 31 Latch HV OUT 32 Data Out Latch HV5522 HV5522 Ordering Information Package Options 44-Lead Quad Plastic Gullwing 44-Lead Quad Plastic Chip Carrier HV5522PG-G HV5522PG-G Device HV5522PJ-G HV5522PJ-G 10.00x10.00mm body 2.45mm height (max) 0.80mm pitch HV5522 HV5522 .690x.690in body .180in height (max) .050in pitch -G indicates package is RoHS compliant (`Green') Pin Configurations Absolute Maximum Ratings Parameter Value Supply voltage, VDD1 Output voltage, V Logic input levels1 Ground current -0.5V to +15V -0.5V to +230V 1 PP -0.5V to VDD +0.5V 1.5A 2 Continuous total power dissipation3 44 1 1200mW Operating temperature range 44-Lead PQFP (PG) (top view) -40OC -40OC to +85OC Storage temperature range 6 -65OC -65OC to +150OC 150OC Lead temperature4 1 44 40 260OC 260OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. All voltages are referenced to VSS 2. Duty cycle is limited by the total power dissipated in the package 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C 4. 1.6mm (1/16inch) from case for 10 seconds Recommended Operating Conditions (top view) Product Marking Top Marking Sym Parameter Min Max Units VDD Logic voltage supply 10.8 13.2 V -0.3 +220 V HVOUT High voltage output 44-Lead PLCC (PJ) VIH Input high voltage VDD -2.0 VDD V VIL Input low voltage 0 2.0 V fCLK Clock frequency - 8.0 Operating free-air temperature -40 +85 LLLLLLLLL Bottom Marking MHz TA YYWW HV5522PG HV5522PG C O CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking 44-Lead PQFP (PG) Top Marking YY = Year Sealed WW = Week Sealed LLLLLLLLLL L = Lot Number C = Country of Origin* Bottom Marking A = Assembler ID* = "Green" Packaging CCCCCCCCCCC YYWW Power-Up Sequence HV5522PJ HV5522PJ Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs to a known state AAA Power-down sequence should be the reverse of the above. 2 *May be part of top marking 44-Lead PLCC (PJ) HV5522 HV5522 Electrical Characteristics (over recommended operating conditions unless otherwise noted) DC Characteristics Sym Parameter Min Max Units Conditions IDD VDD supply current - 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz IDDQ VDD supply current (quiescent) - 100 µA VIN = 0V Off state output current - 10 µA All outputs high, all SWS parallel IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V VDD -1.0V - V IDOUT = -100µA HVOUT - 15 V IHVOUT = +100mA Data out - 1.0 V IDOUT = +100µA - -1.5 V IOL = -100mA Min Max Units Conditions - 8.0 MHz - IO(OFF) VOH High-level output data out VOL Low-level output voltage VOC HVOUT clamp voltage AC Characteristics Sym (VDD = 12V, TC = 25OC) Parameter fCLK Clock frequency tW Clock width, high or low 62 - ns - tSU Data set-up time before CLK falls 25 - ns - tH Data hold time after CLK falls 10 - ns - tON Turn-on time, HVOUT from enable - 500 ns RL = 2.0K to VPP max. tDHL Delay time clock to data high to low - 100 ns CL = 15pF tDLH Delay time clock to data low to high - 100 ns CL = 15pF tDLE Delay time clock to LE low to high 50 - ns - tWLE Width of LE pulse 50 - ns - tSLE LE setup time before clock falls 50 - ns - Input and Output Equivalent Circuits VDD VDD HVOUT Data Out Input HVIN VSS VSS VSS Logic Inputs Logic Data Output 3 High Voltage Outputs HV5522 HV5522 Switching Waveforms V IH Data Input 50% 50% Data Valid V IL tSU tH V IH Clock 50% 50% 50% tWH 50% V IL tWL V OH 50% V OL tDLH Data Out V OH 50% V OL tDHL Latch Enable V IH 50% 50% V IL tWLE tDLE tSLE V OH HV OUT w/ S/R HIGH 10% V OL tON Functional Table Inputs Function Outputs Shift Reg 1 2.32 1 2.32 L * *.* On On.On * L H * *.* Off Off.Off * L H L * *.* * *.* * L H H H or L *.* * *.* * X H or L H H * *.* * *.* * X H or L H L * *.* * *.* * L H H H L *.* Off *.* * H H H H H *.* On *.* * CLK LE BL POL All on X X X L All off X X X Invert mode X X Load S/R H or L Load latches Transparent latch mode HV Outputs Data Out * Data Notes: H = high level, L = low level, X = irrelevant, = high-to-low transition, = low-to-high transistion. * dependent on previous stage's state before the last CLK or last LE high. 4 HV5522 HV5522 44-Lead PQFP Pin Assignment (PG) Pin # Function 1 HVOUT11 HVOUT11 2 HVOUT12 HVOUT12 3 HVOUT13 HVOUT13 4 HVOUT14 HVOUT14 5 HVOUT15 HVOUT15 6 HVOUT16 HVOUT16 7 HVOUT17 HVOUT17 8 Description HVOUT18 HVOUT18 9 HVOUT19 HVOUT19 10 HVOUT20 HVOUT20 11 HVOUT21 HVOUT21 12 HVOUT22 HVOUT22 13 HVOUT23 HVOUT23 14 HVOUT24 HVOUT24 15 HVOUT25 HVOUT25 16 HVOUT26 HVOUT26 17 HVOUT27 HVOUT27 18 HVOUT28 HVOUT28 19 HVOUT29 HVOUT29 20 HVOUT30 HVOUT30 21 HVOUT31 HVOUT31 22 HVOUT32 HVOUT32 23 Data Out 24 N/C 25 N/C High voltage outputs. Data output pin. No internal connection. 26 N/C 27 POL Inverts the polarity of the HVOUT pins 28 CLK Clock pin, shift registers shifts data on falling edge of input clock. 29 VSS Reference voltage, usually ground. 30 VDD Logic supply voltage. 31 LE 32 Data In 33 Blanking 34 N/C 35 HVOUT1 36 HVOUT2 37 HVOUT3 38 HVOUT4 39 HVOUT5 40 HVOUT6 41 HVOUT7 42 HVOUT8 43 HVOUT9 44 Latch enable pin, data is shifted from shift register to latches on logic input high. HVOUT10 HVOUT10 Data input pin. Blanking pin sets all HVOUT pins low or high depending upon state of polarity. See function table. No internal connection. High voltage outputs. 5 HV5522 HV5522 44-Lead PLCC Pin Assignment (PJ) Pin # Function 1 HVOUT16 HVOUT16 2 HVOUT17 HVOUT17 3 HVOUT18 HVOUT18 4 HVOUT19 HVOUT19 5 HVOUT20 HVOUT20 6 HVOUT21 HVOUT21 7 HVOUT22 HVOUT22 8 Description HVOUT23 HVOUT23 9 HVOUT24 HVOUT24 10 HVOUT25 HVOUT25 11 HVOUT26 HVOUT26 12 HVOUT27 HVOUT27 13 HVOUT28 HVOUT28 14 HVOUT29 HVOUT29 15 HVOUT30 HVOUT30 16 HVOUT31 HVOUT31 17 HVOUT32 HVOUT32 18 Data Out 19 N/C 20 N/C 21 N/C 22 POL Inverts the polarity of the HVOUT pins 23 CLK Clock pin, shift registers shifts data on falling edge of input clock. 24 VSS Reference voltage, usually ground. 25 VDD Logic supply voltage. 26 LE 27 Data In 28 Blanking 29 N/C 30 HVOUT3 33 HVOUT4 34 HVOUT5 35 HVOUT6 36 HVOUT7 37 HVOUT8 38 HVOUT9 39 HVOUT10 HVOUT10 40 HVOUT11 HVOUT11 41 HVOUT12 HVOUT12 42 HVOUT13 HVOUT13 43 HVOUT14 HVOUT14 44 No internal connection. HVOUT2 32 Data output pin. HVOUT1 31 High voltage outputs. Latch enable pin, data is shifted from shift register to latches on logic input high. HVOUT15 HVOUT15 Data input pin. Blanking pin sets all HVOUT pins low or high depending upon state of polarity. See function table. No internal connection. High voltage outputs. 6 HV5522 HV5522 44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 Gauge Plane 44 L 1 L1 e b Top View Seating Plane View B View B A A2 Seating Plane A1 Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A MIN Dimension NOM (mm) MAX A1 A2 b D D1 E E1 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* - - 2.00 - 13.90 10.00 13.90 10.00 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* JEDEC Registration MO-112 MO-112, Variation AA-2, Issue B, Sep.1995. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings not to scale. Supertex Doc. #: DSPD-44PQFPPG DSPD-44PQFPPG, Version B101708 B101708. 7 e 0.80 BSC L 0.73 0.88 1.03 L1 1.95 REF L2 0.25 BSC 0O 3.5O 7O HV5522 HV5522 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 1 44 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 .020max (3 Places) Top View Vertical Side View View B A Base Plane A2 Seating Plane e A1 b1 .020 MIN b Horizontal Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 e .050 BSC JEDEC Registration MS-018 MS-018, Variation AC, Issue A, June, 1993. This dimension is a non-JEDEC dimension. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ DSPD-44PLCCPJ, Version D092408 D092408. Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. ©2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV5522 DSFP-HV5522 A111908 A111908 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com