HV5308B HVOUT32 HV5308DJ-B HV5308PG-B-G HV5308PJ-B-G -40OC -55OC 125OC -65OC - Datasheet Archive

 

32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs Features General Description The HV5308B is a low

 

HV5308B HV5308B 32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs Features General Description The HV5308B HV5308B is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for AC-electroluminescent displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capabilities, such as driving plasma panels, vacuum fluorescent, or large matrix LCD displays. Processed with HVCMOS® technology Low power level shifting Source/sink current minimum 20mA Shift register speed 8.0MHz Latched data outputs CMOS compatible inputs Forward and reverse shifting options Diode to VPP allows efficient power recovery Th HV5308B HV5308B consists of a 32-bit shift register, 32 latches, and control logic to enable outputs. Q1 is connected to the first stage of the shift register through the Output Enable logic. Data is shifted through the shift register on the low to high transition of the clock. When viewed from the top of the package, the HV5308B HV5308B shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (32). Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is retained when LE is low. Typical Application Circuit VPP VDD Data Input CLK HVOUT1 Low Voltage Shift Register Latches Output Contr. Level Translators & Push-Pull Output Buffers LE Micro Processor OE Columns High Voltage Data Out Supertex HV5308B HV5308B Row Driver HVOUT32 HVOUT32 Display Panel Data Input for cascading the next HV5308B HV5308B 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com HV5308B HV5308B Ordering Information Package Options 44-Lead Quad Cerpac Device 44-Lead PQFP HV5308DJ-B HV5308DJ-B* .653x.653in body .180in height (max) .050in pitch HV5308PG-B-G HV5308PG-B-G .650x.650in body .190in height (max) .050in pitch HV5308B HV5308B 44-Lead PLCC 10.00x10.00mm body 2.35mm height (max) 0.80mm pitch HV5308PJ-B-G HV5308PJ-B-G -G indicates package is RoHS compliant (`Green'). * Hi-Rel process flow available. Pin Configurations Absolute Maximum Ratings Parameter 6 Value Supply voltage, VDD -0.5V to +16V Supply voltage, VPP 40 1 44 -0.5V to +90V Logic input levels -0.5V to VDD +0.5V Ground current1 1.5A Continuous total power dissipation2 Plastic Ceramic 1200W 1500W Operating temperature range Plastic Ceramic (top view) -40OC -40OC to +85OC -55OC -55OC to +125OC 125OC Storage temperature range 44-Lead Quad Cerpac (DJ) -65OC -65OC to +150OC 150OC Lead temperature3 260OC 260OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 44 1 44-Lead PQFP (PG) (top view) 6 Notes: 1. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 15mW/°C for ceramic. 3. 1.6mm (1/16 inch) from case for 10 seconds 44-Lead PLCC (PJ) (top view) Product Marking YYWW HV5308DJ HV5308DJ LLLLLLLLLL Bottom Marking CCCCCCCCCCC AAA Top Marking Top Marking Top Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* *May be part of top marking 44-Lead Quad Cerpac (DJ) 40 1 44 YYWW HV5308PG HV5308PG LLLLLL L L L Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking 44-Lead PQFP (PG) YYWW AAA HV5308PJ-B HV5308PJ-B LLLLLLLLLL Bottom Marking CCCCCCCCCCC YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = "Green" Packaging *May be part of top marking 44-Lead PLCC (PJ) Packages may or may not include the following marks: Si or 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 HV5308B HV5308B Recommended Operating Conditions (over -40 to 85°C for plastic and -55°C to 125°C for ceramic) Sym Parameter Min Max Units VDD Logic voltage supply 10.8 13.2 V VPP High voltage supply 8.0 80 V VIH Input high voltage VDD - 2.0 VDD V VIL Input low voltage 0 2.0 V fCLK Clock frequency 0 8.0 MHz Power-Up Sequence Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs (Data, CLK, LE, etc.) to a known state 4. Apply VPP 5. The VPP should not fall below VDD or float during operation. Power-down sequence should be the reverse of the above. Electrical Characteristics (V PP DC Characteristics Sym = 60V, VDD = 12V, TA = 25°C) Parameter Min Max Units Conditions IPP VPP supply current - 0.5 mA HVOUTPUTS high to low IDDQ IDD supply current (quiescent) - 100 µA All inputs = VDD or GND IDD IDD supply current (operating) - 15 mA VDD = VDD max, fCLK = 8.0MHz 10.5 - V IO = 100µA VOH (data) Shift register output voltage VOL (data) Shift register output voltage - 1.0 V IO = 100µA IIH Current leakage, any input - 1.0 µA VIN = VDD IIL Current leakage, any input - -1.0 µA VIN = 0 VOC HV output clamp diode voltage - -1.5 V IOL = -100mA VOH HV output when sourcing 52 - V IOH = -20mA, -40 to 85°C VOL HV output when sinking - 8.0 V IOL = 20mA, -40 to 85°C VOH HV output when sourcing 52 - V IOH = -15mA, -55 to 125°C VOL HV output when sinking - 8.0 V IOL = 15mA, -55 to 125°C 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 HV5308B HV5308B AC Characteristics Sym Parameter Min Max Units Conditions - 8.0 MHz - Clock width, HIGH or LOW 62 - ns - tSU Setup time before CLK rises 25 - ns - tH Hold time after CLK rises 10 - ns - tDLH (Data) Data output delay after L to H CLK - 110 ns CL = 15pF tDHL (Data) Data output delay after H to L CLK - 110 ns CL = 15pF fCLK Clock frequency tWL or tWH tDLE LE delay after L to H CLK 50 - ns - tWLE Width of LE pulse 50 - ns - tSLE LE setup time before L to H CLK 50 - ns - tON Delay from LE to HVOUT, L to H - 500 ns - tOFF Delay from LE to HVOUT, H to L - 500 ns - Switching Waveforms VIH 50% Data Input 50% Data Valid tSU VIL tH VIH CLK 50% 50% 50% tWL 50% tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL VIH 50% 50% VIL LE tWLE tDLE tSLE 90% 10% HVOUT w/ S/R LOW VIL VOH VOL tOFF HVOUT w/ S/R HIGH 10% 90% tON 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 VOH VOL HV5308B HV5308B Input and Output Equivalent Circuits VDD VDD VPP Data Out Input GND GND HVOUT GND Logic Data Output Logic Inputs High Voltage Outputs Functional Block Diagram VPP OE LE Data Input HVOUT1 Clock 32 bit Static Register HVOUT2 · · · 28 Additional Outputs · · · HVOUT31 HVOUT31 32 bit Latches Data Out HVOUT32 HVOUT32 Function Tables Data Output Data Input LE OE HV Output H H X X L L L All HVOUT = LOW X L H Previous latched data H H H H L H H L Data Input X CLK* No Note: * = LOW - to - HIGH transition No change H = High L = Low X = Don't Care 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 HV5308B HV5308B 44-Lead PQFP Pin Assignment (PG) Pin # Function 1 HVOUT22 HVOUT22 2 HVOUT21 HVOUT21 3 HVOUT20 HVOUT20 4 HVOUT19 HVOUT19 5 HVOUT18 HVOUT18 6 HVOUT17 HVOUT17 7 HVOUT16 HVOUT16 8 HVOUT15 HVOUT15 9 HVOUT14 HVOUT14 10 HVOUT13 HVOUT13 11 HVOUT12 HVOUT12 12 HVOUT11 HVOUT11 13 HVOUT10 HVOUT10 14 HVOUT9 15 HVOUT8 16 HVOUT7 17 HVOUT6 18 HVOUT5 19 HVOUT4 20 HVOUT3 21 HVOUT2 22 HVOUT1 23 DATA OUT Description High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to GND, or to VPP rail levels. Serial data output. Data output for cascading to the data input of the next device. 24 25 N/C No connect. 26 Data shift register clock 27 CLK 28 GND Logic and high voltage ground 29 VPP High voltage power rail. 30 VDD Low voltage logic power rail. Input are shifted into the shift register on the positive edge of the clock. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6 HV5308B HV5308B 44-Lead PQFP Pin Assignment (PG) Pin # Function Description Latch enable input. 31 LE 32 DATA IN When LE is HIGH, shift register data is transferred into a data latch. When LE is LOW, data is latched, and new data can be clocked into the shift register. Serial data input. Data needs to be present before each rising edge of the clock. Output enable input. 33 OE 34 N/C 35 HVOUT32 HVOUT32 36 HVOUT31 HVOUT31 37 HVOUT30 HVOUT30 38 HVOUT29 HVOUT29 39 HVOUT28 HVOUT28 40 HVOUT27 HVOUT27 41 HVOUT26 HVOUT26 42 HVOUT25 HVOUT25 43 HVOUT24 HVOUT24 44 HVOUT23 HVOUT23 When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in each channel. When OE is HIGH, all HV outputs reflect data latched. No connect. High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to GND, or to VPP rail levels. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 7 HV5308B HV5308B 44-Lead PLCC Pin Assignment (DJ/PJ) Pin # Function 1 HVOUT17 HVOUT17 2 HVOUT16 HVOUT16 3 HVOUT15 HVOUT15 4 HVOUT14 HVOUT14 5 HVOUT13 HVOUT13 6 HVOUT12 HVOUT12 7 HVOUT11 HVOUT11 8 HVOUT10 HVOUT10 9 HVOUT9 10 HVOUT8 11 HVOUT7 12 HVOUT6 13 HVOUT5 14 HVOUT4 15 HVOUT3 16 HVOUT2 17 HVOUT1 18 DATA OUT Description High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to GND, or to VPP rail levels. Serial data output. Data output for cascading to the data input of the next device. 19 20 N/C No connect. 21 Data shift register clock 22 CLK 23 GND Logic and high voltage ground 24 VPP High voltage power rail. 25 VDD Low voltage logic power rail. Input are shifted into the shift register on the positive edge of the clock. Latch enable input. 26 LE 27 DATA IN When LE is HIGH, shift register data is transferred into a data latch. When LE is LOW, data is latched, and new data can be clocked into the shift register. Serial data input. Data needs to be present before each rising edge of the clock. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 8 HV5308B HV5308B 44-Lead PLCC Pin Assignment (DJ/PJ) Pin # Function Description Output enable input. 28 OE 29 N/C 30 HVOUT32 HVOUT32 31 HVOUT31 HVOUT31 32 HVOUT30 HVOUT30 33 HVOUT29 HVOUT29 34 HVOUT28 HVOUT28 35 HVOUT27 HVOUT27 36 HVOUT26 HVOUT26 37 HVOUT25 HVOUT25 38 HVOUT24 HVOUT24 39 HVOUT23 HVOUT23 40 HVOUT22 HVOUT22 41 HVOUT21 HVOUT21 42 HVOUT20 HVOUT20 43 HVOUT19 HVOUT19 44 HVOUT18 HVOUT18 When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in each channel. When OE is HIGH, all HV outputs reflect data latched. No connect. High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to GND, or to VPP rail levels. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 9 HV5308B HV5308B 44-Lead Quad Cerpac Package Outline (DJ) .650x.650in body, .190in height (max), .050in pitch D D1 1 44 .040 x 45O 6 .150 MAX .035 x 45O 40 Note 1 (Index Area) .075 MAX E1 0.25 max 3 Places E Vertical Side View Top View View B A b1 .025 MIN A2 Seating Plane e A1 b View B Horizontal Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (inches) A A1 MIN .155 .090 NOM .172 .100 MAX .190 .120 A2 .060 REF b b1 D D1 E E1 .017 .026 .685 .630 .685 .630 .019 .029 .690 .650 .690 .650 .021 .032 .695 .665 .695 .665 JEDEC Registration MO-087 MO-087, Variation AB, Issue B, August, 1991. Drawings not to scale. Supertex Doc. #: DSPD-44CERPACDJ DSPD-44CERPACDJ, Version D090808 D090808. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 10 e .050 BSC HV5308B HV5308B 44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 Gauge Plane 44 L 1 L1 e b Top View Seating Plane View B View B A A2 Seating Plane A1 Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A MIN Dimension NOM (mm) MAX A1 A2 b D D1 E E1 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* - - 2.00 - 13.90 10.00 13.90 10.00 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* e 0.80 BSC L 0.73 0.88 1.03 L1 1.95 REF JEDEC Registration MO-112 MO-112, Variation AA-2, Issue B, Sep.1995. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PQFPPG DSPD-44PQFPPG, Version C041309 C041309. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 11 L2 0.25 BSC 0O 3.5O 7O HV5308B HV5308B 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 1 44 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 .020max (3 Places) Top View Vertical Side View View B A Base Plane A2 Seating Plane e A1 b1 .020 MIN b Horizontal Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 e .050 BSC JEDEC Registration MS-018 MS-018, Variation AC, Issue A, June, 1993. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ DSPD-44PLCCPJ, Version E041309 E041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www. supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. ©2009 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV5308B DSFP-HV5308B A092309 A092309 12 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com