HUF76439P3 HUF76439S3S 6439P HUF76 439S3 76439P 76439S HUF76439S3ST TB334 - Datasheet Archive

 

Data Sheet October 1999 File Number 4674.1 71A, 60V, 0.014 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET [ /Title

 

HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Data Sheet October 1999 File Number 4674.1 71A, 60V, 0.014 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET [ /Title Packaging Features (HUF7 JEDEC TO-220AB JEDEC TO-263AB · Ultra Low On-Resistance 6439P 6439P - rDS(ON) = 0.012, VGS = 10V 3, SOURCE DRAIN - rDS(ON) = 0.014, VGS = 5V DRAIN (FLANGE) HUF76 HUF76 GATE · Simulation Models 439S3 439S3 - Temperature Compensated PSPICE® and SABERTM S) Electrical Models GATE /Subjec - Spice and SABER Thermal Impedance Models SOURCE DRAIN t (71A, - www.Intersil.com (FLANGE) 60V, · Peak Current vs Pulse Width Curve HUF76439P3 HUF76439P3 HUF76439S3S HUF76439S3S 0.014 · UIS Rating Curve Ohm, · Switching Time vs RGS Curves Symbol NChann D Ordering Information el, Logic PART NUMBER PACKAGE BRAND Level G HUF76439P3 HUF76439P3 TO-220AB 76439P 76439P UltraF HUF76439S3S HUF76439S3S TO-263AB 76439S 76439S S ET NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76439S3ST HUF76439S3ST. Power MOSF Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified ET) HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S UNITS /Autho Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 60 V r () Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V ±16 V /Keyw Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Drain Current ords Continuous (TC = 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 75 A (Intersi 75 A Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 54 A l 52 A Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Corpor Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Figure 4 ation, Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18 NPower Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 180 W Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.20 W/oC Chann oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 el, Maximum Temperature for Soldering Logic oC 300 Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL oC 260 Package Body for 10s, See Techbrief TB334 TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg Level NOTES: UltraF 1. TJ = 25oC to 150oC. ET CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the Power device at these or any other conditions above those indicated in the operational sections of this specification is not implied. MOSF Product reliability information can be found at http://www.mtp.intersil.com/reliability.html For severe environments, see our Automotive HUFA series. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 ISO9000 and QS9000 QS9000 quality systems certification. ©2001 Fairchild Semiconductor Corporation HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ID = 250µA, VGS = 0V (Figure 12) 60 - - V ID = 250µA, VGS = 0V , TC = -40oC (Figure 12) 55 - - V OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS Gate to Source Leakage Current IDSS IGSS VDS = 55V, VGS = 0V - - 1 µA VDS = 50V, VGS = 0V, TC = 150oC Zero Gate Voltage Drain Current - - 250 µA VGS = ±16V - - ±100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figures 9, 10) - 0.010 0.012 ID = 54A, VGS = 5V (Figure 9) - 0.0117 0.014 ID = 52A, VGS = 4.5V (Figure 9) - 0.0125 0.015 TO-220AB and TO-263AB - - 0.96 oC/W - - 62 oC/W - - 470 ns - 16 - ns ns THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time tON td(ON) Rise Time VDD = 30V, ID = 52A VGS = 4.5V, RGS = 3.9 (Figures 15, 21, 22) tr - 300 - td(OFF) - 29 - ns tf Turn-Off Delay Time - 105 - ns tOFF - - 200 ns - - 205 ns - 11 - ns ns Fall Time Turn-Off Time SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time tON td(ON) VDD = 30V, ID = 75A VGS = 10V, RGS = 3.9 (Figures 16, 21, 22) - 125 - td(OFF) - 45 - ns tf Rise Time - 125 - ns tOFF - - 255 ns - 70 84 nC - 38 45 nC - 2.5 3 nC tr Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Qg(TOT) VGS = 0V to 10V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V VDD = 30V, ID = 50A, Ig(REF) = 1.0mA (Figures 14, 19, 20) Gate to Source Gate Charge Qgs - 8 - nC Gate to Drain "Miller" Charge Qgd - 19 - nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) CRSS - 2745 - pF - 840 - pF - 145 - pF Source to Drain Diode Specifications PARAMETER Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation MIN TYP MAX UNITS ISD = 54A - - 1.25 V ISD = 27A Source to Drain Diode Voltage SYMBOL - - 1.00 V trr ISD = 54A, dISD/dt = 100A/µs - - 72 ns QRR ISD = 54A, dISD/dt = 100A/µs - - 140 nC VSD TEST CONDITIONS HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 VGS = 10V 60 VGS = 4.5V 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V VGS = 5V 100 50 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY ©2001 Fairchild Semiconductor Corporation HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Typical Performance Curves (Continued) 500 100 100µs If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 1000 100 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms SINGLE PULSE TJ = MAX RATED TC = 25oC 1 1 10ms 10 STARTING TJ = 25oC STARTING TJ = 150oC 10 0.01 100 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 AN9321 and AN9322 AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 150 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 120 VGS = 10V VGS = 5V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 150 90 60 TJ = 175oC 30 TJ = -55oC 120 2.0 2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 90 60 VGS = 3.5V 30 VGS = 3V TJ = 25oC 0 VGS = 4V 0 3.5 4.0 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) 0 5.0 FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS 25 2.5 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 75A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 4 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) ID = 50A 15 ID = 25A 10 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A 2.0 1.5 1.0 0.5 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2001 Fairchild Semiconductor Corporation -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Typical Performance Curves (Continued) 1.2 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 1.1 1.0 0.4 0.9 -80 -40 0 40 80 120 160 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 10 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 40 80 120 200 160 FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 5000 CISS = CGS + CGD CRSS = CGD 1000 0 TJ , JUNCTION TEMPERATURE (oC) COSS CDS + CGD 100 VGS = 0V, f = 1MHz VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 50A ID = 25A 2 0 50 0.1 1.0 10 0 60 VDS , DRAIN TO SOURCE VOLTAGE (V) 15 30 45 Qg, GATE CHARGE (nC) 60 75 NOTE: Refer to Intersil Application Notes AN7254 AN7254 and AN7260 AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 1000 500 VGS = 10V, VDD = 30V, ID = 75A 800 SWITCHING TIME (ns) SWITCHING TIME (ns) VGS = 4.5V, VDD = 30V, ID = 48A tr 600 400 tf 200 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () FIGURE 15. SWITCHING TIME vs GATE RESISTANCE ©2001 Fairchild Semiconductor Corporation tf 300 tr 200 td(ON) td(ON) 0 td(OFF) 100 td(OFF) 0 400 0 50 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 FIGURE 16. SWITCHING TIME vs GATE RESISTANCE HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD VGS = 5V VGS DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 21. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 22. SWITCHING TIME WAVEFORM HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S PSPICE Electrical Model .SUBCKT HUF76439 HUF76439 2 1 3 ; rev 17 June 1999 CA 12 8 3.70e-9 CB 15 14 3.80e-9 CIN 6 8 2.60e-9 LDRAIN DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DPLCAP 10 RLDRAIN RSLC1 51 DBREAK + EBREAK 11 7 17 18 66.25 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RSLC2 5 51 ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 + 17 EBREAK 18 50 - IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.17e-9 LSOURCE 3 7 2.33e-9 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.72e-3 RGATE 9 20 0.88 RLDRAIN 2 5 10 RLGATE 1 9 51.7 RLSOURCE 3 7 23.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.43e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 12 S2A 14 13 13 8 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RVTHRES VBAT 22 19 DC 1 ESLC 51 50 )} .MODEL DBODYMOD D (IS = 2.52e-12 RS = 3.53e-3 TRS1 = 1.79e-3 TRS2 = 1.27e-6 CJO = 2.82e-9 TT = 4.90e-8 M = 0.43) .MODEL DBREAKMOD D (RS = 1.95e-1 TRS1 = 9.01e-4 TRS2 = 2.07e-6) .MODEL DPLCAPMOD D (CJO = 2.28e-9 IS = 1e-30 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 1.88 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.88) .MODEL MSTROMOD NMOS (VTO = 2.31 KP = 137 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.65 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.8 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.19e-3 TC2 = -1.91e-7) .MODEL RDRAINMOD RES (TC1 = 1.15e-2 TC2 = 3.07e-5) .MODEL RSLCMOD RES (TC1 = 9.92e-4 TC2 = 1.23e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.65e-3 TC2 = -7.94e-6) .MODEL RVTEMPMOD RES (TC1 = -1.39e-3 TC2 = -2.13e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.0 VOFF= -2.5) VON = -2.5 VOFF= -6.0) VON = -0.5 VOFF= 0.0) VON = 0.0 VOFF= -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S SABER Electrical Model REV 17 June 1999 template ta76445 n2,n1,n3 electrical n2,n1,n3 { var i iscl d.model dbodymod = (is = 2.52e-12, cjo = 2.82e-9, tt = 4.90e-8, m = 0.43) d.model dbreakmod = () d.model dplcapmod = (cjo = 2.28e-9, is = 1e-30, m = 0.85 ) m.model mmedmod = (type=_n, vto = 1.88, kp = 2.1, is = 1e-30, tox = 1) m.model mstrongmod = (type=_n, vto = 2.31, kp = 137, is = 1e-30, tox = 1) m.model mweakmod = (type=_n, vto = 1.65, kp = 0.05, is = 1e-30, tox = 1) sw_vcsp.model s1amod = (ron = 1e-5, roff = 0.1, von = -6, voff = -2.5) sw_vcsp.model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -6) sw_vcsp.model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0) sw_vcsp.model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5) LDRAIN DPLCAP 10 RSLC1 51 c.ca n12 n8 = 3.70e-9 c.cb n15 n14 = 3.80e-9 c.cin n6 n8 = 2.60e-9 RLDRAIN RDBREAK RSLC2 72 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + i.it n8 n17 = 1 LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 MWEAK MSTRO CIN DBODY EBREAK + 17 18 MMED m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 71 11 16 6 RLGATE res.rbreak n17 n18 = 1, tc1 = 1.19e-3, tc2 = -1.91e-7 res.rdbody n71 n5 = 3.53e-3, tc1 = 1.79e-3, tc2 = 1.27e-6 res.rdbreak n72 n5 = 1.95e-1, tc1 = 9.01e-4, tc2 = 2.07e-6 res.rdrain n50 n16 = 4.72e-3, tc1 = 1.15e-2, tc2 = 3.07e-5 res.rgate n9 n20 = 0.88 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51.7 res.rlsource n3 n7 = 23.3 res.rslc1 n5 n51 = 1e-6, tc1 = 9.92e-4, tc2 = 1.23e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.43e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.39e-3, tc2 = -2.13e-7 res.rvthres n22 n8 = 1, tc1 = -2.65e-3, tc2 = -7.94e-6 21 RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.17e-9 l.lsource n3 n7 = 2.33e-9 DRAIN 2 5 - 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 66.25 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ( )* 3.5) } } ©2001 Fairchild Semiconductor Corporation HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. A HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S SPICE Thermal Model th JUNCTION REV 23 June 1999 HUF76439T HUF76439T CTHERM1 th 6 3.00e-3 CTHERM2 6 5 1.90e-2 CTHERM3 5 4 6.95e-3 CTHERM4 4 3 7.00e-3 CTHERM5 3 2 2.95e-2 CTHERM6 2 tl 12.55 RTHERM1 RTHERM1 th 6 6.32e-3 RTHERM2 6 5 1.57e-2 RTHERM3 5 4 4.43e-2 RTHERM4 4 3 2.49e-1 RTHERM5 3 2 3.75e-1 RTHERM6 2 tl 4.98e-2 CTHERM1 RTHERM2 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF76445T HUF76445T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 3.00e-3 ctherm.ctherm2 6 5 = 1.90e-2 ctherm.ctherm3 5 4 = 6.95e-3 ctherm.ctherm4 4 3 = 7.00e-3 ctherm.ctherm5 3 2 = 2.95e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 6.32e-3 rtherm.rtherm2 6 5 = 1.57e-2 rtherm.rtherm3 5 4 = 4.43e-2 rtherm.rtherm4 4 3 = 2.49e-1 rtherm.rtherm5 3 2 = 3.75e-1 rtherm.rtherm6 2 tl = 4.98e-2 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl ©2001 Fairchild Semiconductor Corporation CASE HUF76439P3 HUF76439P3, HUF76439S3S HUF76439S3S Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1