HT9580 M6502 SED15X MC141X HD66410 0000H 0001H 0002H 0003H 0004H 0005H 0006H - Datasheet Archive

 

HT9580 Character Pager Controller Features · · · · · · · · ·

 

Preliminary HT9580 HT9580 Character Pager Controller Features · · · · · · · · · · · · · · · Operating voltage: 2.4V~3.5V Temperature range: -30°C to +85°C low power, high performance M6502 M6502 core low power crystal oscillator control - 512/1200/2400 bps data rate operation ²CCIR Radio Paging Code No.1² (POCSAG) compatible 76.8kHz crystal for all available data rates High/low system clock switching capability 44 Kbytes program ROM 848 bytes global data RAM Internal 2 Mbits Character ROM 256 Kbits internal SRAM External option up to 2 Mbits Character ROM or 2 Mbits SRAM SED15X SED15X(KSX), MC141X MC141X and HD66410 HD66410 series LCD driver compatible interface option 46 bytes message buffer One 16-bit timer and one 8-bit timer · · · · · · · · · · · · · · Internal 2Hz or 1Hz RTC or Real Time Clock option Single buzzer generator output (BZ) with duty cycle control low current HALT mode operation 16-bit watchdog timer Built-in data filter (16-times over-sampling ) and bit clock recovery Advanced synchronization algorithm 2-bit random and (optional) 4-bit burst error correction for address and message Up to 6 user addresses and 6 user frames, independently programmable 3 RF power-on timing control pins and Received data inversion (optional) Built in SPI circuit Out-of-range condition indicator One internal 8-bit D/A converter Battery fail and battery low detection 80-pin LQFP package General Description therefore provides excellent decoder sensitivity. The controller contains a full function pager decoder at a 512, 1200, 2400 bps data rates. Using an M6502 M6502 core takes advantage of a flexible external control interface, LCD driver chips and abundant programming resources from worldwide providers. The internal SPI would communicate with SPI of FLEXTM high speed pager decoder. The HT9580 HT9580 is a high performance pager controller which can be used for Chinese Pager system applications. The HT9580 HT9580 4-in-1 Character Pager Controller combines a POCSAG decoder with a M6502 M6502 microprocessor core, 2 Mbits Character ROM and 256 Kbits SRAM to provide both high decoder performance and excellent system flexibility. The decoder utilizes a 2-bit random error correction algorithm and FLEX TM is a trademark of Motorola Inc. 1 April 28, 2000 Preliminary HT9580 HT9580 Block Diagram R e g is te r S e c tio n C o n tr o l S e c tio n R E S IR Q N M I L o g ic In d e x R e g is te r Y A 1 A 2 A 4 A B L S Y N C A 8 A c c u m u la to r A In te rn a l A D L A 9 A 1 0 A B H M L T im in g C o n tro l S p e c ia l B u s A 7 A 1 2 R D Y In s tr u c tio n D e c o d e r A L U In te rn a l A D L A 6 C lo c k G e n e ra to r/ O s c illa to r P C L P ro c e s s o r S ta tu s R e g is te r P P C H In p u t D a ta L a tc h (D L ) A 1 3 D a ta B u s B u ffe r P H I2 (IN ) O S C 1 P H I1 (O U T ) P H I2 (O U T ) S O R /W B E A 1 4 A 1 5 IR Q V P S ta c k P o in t R e g is te r ( s ) A 5 A 1 1 N M I In d e x R e g is te r X A 0 A 3 In te rru p t L o g ic R E S E T O S C 2 In te rru p t L o g ic D 0 L e g e n d D 1 D 2 = 8 B it L in e D 3 D 4 = 1 B it L in e D 5 D 6 D 7 M 6 5 0 2 C o re 5 P ro g ra m R O M A d d re s s D e c o d e r 6 T M R 0 ( 8 b it) S R A M X 1 S y s te m C lo c k T M R 1 ( 1 6 b it) L C D _ E C h a ra c te r R O M L C D _ R W L C D _ C S 0 L C D _ C S 1 M U X 7 P _ M O D E X 1 S y s te m C lo c k T M R 1 P A C L C D _ A 0 P A 0 ~ P A 5 P B P B 0 ~ P B 7 P C C W D T P A P B C L C D D r iv e r In te rfa c e L C D _ C L P C T o n e G e n e ra to r P C 0 ~ P C 1 D u ty C y c le C o n tr o l B Z R T C R S S I D ig ita l F ilte r B A F D A _ O U T P r e - s c a le r M U X 4 M U X R A 1 R A 1 R A 1 R A 1 8 - b it D /A D A 7 D A 6 D A 5 D A 4 D A 3 D A 2 D A 1 D A 0 D a ta P h a s e R e c o v e ry B C H C o d e D e c o d e r S ta tu s C o n tr o lle r P O C S A G 2 R F P o w e r C o n tr o lle r U s e r A d d re s s a n d C o n fig u r a tio n M e m o ry D e c o d e r D a ta O u tp u t C o n tro l S P I C ir c u it B S 1 /S S B S 2 /S C K B S 3 /M O S I D I/M IS O B A L /S R D Y S P I C o n tro l X 1 X 2 D e c o d e r April 28, 2000 Preliminary HT9580 HT9580 Pin Assignment R S S I D I/M IS O B S 3 /M O S I B S 2 /S C K B S 1 /S S T S P A 5 P A 4 P A 3 P A 2 P A 1 P A 0 R E S E T T S C T S 1 O S C 2 O S C 1 V S S X 2 X 1 V D D L C D _ C S 1 L C D _ C S 0 L C D _ C L L C D _ A 0 L C D _ R W L C D _ E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 R /W S R A M _ C E M A S K _ C E O E P S E N 1 8 0 6 1 6 0 H T 9 5 8 0 8 0 L Q F P 4 1 4 0 2 0 2 1 D A B A S R V S V D B Z P C P C P B P B P B P B P B P B P B P B T M A 0 A 1 A 2 _ O U T F D Y /B A L S D 1 0 7 6 5 4 3 2 0 1 R 1 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 A 1 5 V S S P _ M V D D R A 1 R A 1 R A 1 R A 1 4 5 6 7 O D E 3 April 28, 2000 Preliminary HT9580 HT9580 Pin Description Pin No. Pin Name I/O Description 1, 25, 56 VDD ¾ Positive power supply 2 LCD_CS1 O LCD driver chip select control (for slave LCD driver) 3 LCD_CS0 O LCD driver chip select control (for master LCD driver) 4 LCD_CL O LCD driver clock output 5 LCD_A0 O LCD driver data/command select control 6 LCD_RW O LCD Driver Read/Write signal output 7 LCD_E O LCD driver enable clock control 15~8 D0~D7 I/O 16 R/W O Read/Write signal output 17 SRAM_CE O SRAM chip Enable. This signal is generated from the HT9580 HT9580 to provide read or write timing for external SRAM devices. (See Application Circuit) 18 MASK_CE O Mask ROM Chip Enable. This signal is generated from the HT9580 HT9580 to provide read timing for external Mask ROM devices. (See Application Circuit) 19 OE O Mask ROM or SRAM Output Enable. This signal is generated from the HT9580 HT9580 to provide read timing for external Mask ROM and SRAM devices. (See Application Circuit) 20 PSEN O Program Store Enable. This pin is used to connect the OE and CE pins of the external 44 Kbytes program ROM when the ²MODE_P² internal pad is connected to VSS. (See note) 21~24 RA17~RA14 O Extended address bus pins I Internal or external program ROM selection without pull-high resistor. If the pin connects to VDD, the internal program ROM will be fetched (normal type), otherwise the external program ROM will be fetched when the pin connects to VSS (Romless). 27, 57, 78 VSS ¾ Negative power supply 43~28 A0~A15 O Address bus pins. This is used for memory and I/O exchanges on the data bus. 44 TMR1 I 26 P_MODE 8-bit, tristate, bidirectional I/O data bus. Schmitt trigger input for timer1 counter with pull-high resisor. 45~52 PB0~PB7 I/O General Input/Output Port B. The input cell structures can be selected as CMOS or CMOS with pull-high resistors. 53~54 PC0~PC1 I/O General Input/Output Port C. The input cell structures can be selected as CMOS or CMOS with pull-high resistors. 55 BZ O Buzzer non-inverting BZ output 4 April 28, 2000 Preliminary Pin No. Pin Name BAL I/O HT9580 HT9580 Description I Battery voltage detector input with pull-high resistor. SRDY I SPI slave ready ¾ This slave ready pin is a Schmitt trigger input with pull-high resistor. When the slave initiates the SPI transfer, a high to low transition activates an interrupt. When the master initiates the SPI transfer, a high to low transition trigger the master to start the transfer. 59 BAF I Battery fail indication input, active low. 60 DA_OUT O D/A converter output. This pin is an 8-bit D/A analog output RSSI I RSSI output from IF circuit. This pin should be pulled high or low externally when this pin is not used. DI I POCSAG code input serial data. CMOS input with pull-high resistor. MISO I SPI master-in-slave-out ¾ this is the data input with pull-high resistor for SPI communications. BS3 O PLL power control enable, CMOS output MOSI O SPI master-out-slave-in ¾ this is the data output for SPI communications. BS2 O RF quick charge control enable, CMOS output 58 61 62 63 64 SPI serial clock ¾ the SCK signal is used to synchronize the data transfer. If HT9580 HT9580 is in the master mode, the SCK is output clock. Otherwise, SCK is input clock if HT9580 HT9580 is in the slave mode. 66 I/O BS1 65 SCK O Pager receiver power control enable output, CMOS output SS O SPI slave select ¾ this signal is used to enable the SPI slave for transfer. TS I Decoder test mode input pin, active low with pull-high resistor. I/O General Input/Output Port A. These ports can be programmed to have a wake-up capability for applications in keyboard operations or as normal I/O. Also the input cell structures are all Schmitt trigger types and can be selected between CMOS or CMOS with pull-high resistors. 72~67 PA0~PA5 73 RESET I Schmitt trigger reset input, active low. 74 TSC I mC test mode input pin, active low with internal pull-high resistor. The test circuit will be activated when this pin pulls low. 75 TS1 I Decoder test mode input pin, active low with pull-high resistor. The internal test mode will be activated when this pin pulls low. 77 76 OSC1 OSC2 I O OSC1 and OSC2 are connected to an RC network to form a main clock oscillator 80 79 X1 X2 I O X1 and X2 are connected to a crystal to form an internal low power clock oscillator (32.768kHz, 76.8kHz, or 153.6kHz) 5 April 28, 2000 Preliminary HT9580 HT9580 Absolute Maximum Ratings Supply Voltage.-0.3V to 3.6V Storage Temperature.-55°C to 150°C Input Voltage .VSS-0.5V to VDD+0.5V Operating Temperature .-30°C to 85°C Current Drain Per Pin Excluding VDD and VSS .10mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage ¾ 3V application 2.4 3.0 3.5 V IDD Operating Current 3V No load, OSC1=1MHz fX1=76.8kHz ¾ 300 ¾ mA ISTP HALT Mode Current 3V No load, mC clock stop, fX1=76.8kHz ¾ ¾ 100 mA VIL Input low Voltage for I/O Port 3V ¾ 0 ¾ 0.3´VDD V VIH Input High Voltage for I/O Port 3V ¾ 0.7´VDD ¾ 3 V VIL1 Input low Voltage 3V ¾ 0 ¾ 0.3´VDD V VIH1 Input High Voltage 3V ¾ 0.7´VDD ¾ 3 V VIL2 Input low Voltage (BAF) 3V ¾ 0 ¾ 0.9 V VIH2 Input High Voltage (BAF) 3V ¾ 1.0 ¾ 3 V VOL Output low Voltage 3V ¾ ¾ ¾ 0.4 V VOH Output High Voltage 3V ¾ 2.3 ¾ ¾ V IOL I/O Port Sink Current 3V VOL=0.3V 2.0 3.6 ¾ mA IOH I/O Port Source Current 3V VOH=2.7V -1.2 -2.2 ¾ mA IOL1 BZ, PC0~PC1 Sink Current 3V VOL=0.3V 2 4.5 ¾ mA IOH1 BZ, PC0~PC1 Source Current 3V VOH=2.7V -1.5 -2.5 ¾ mA IOL2 BS1, BS2, BS3 Sink Current 3V VOL=0.3V 350 ¾ ¾ mA IOH2 BS1, BS2, BS3 Source Current 3V VOH=2.7V -1.0 ¾ ¾ mA ROSC RC Oscillator Resistor 3V fOSC=1MHz ¾ 51 ¾ kW RPH I/O Port Pull-high Resistance 3V ¾ 100 250 ¾ kW 6 April 28, 2000 Preliminary HT9580 HT9580 A.C. Characteristics Symbol Ta=25°C Parameter Test Conditions Min. VDD Conditions Typ. Max. Unit fOSC1 Main Clock (RC OSC) 3V ¾ 76.8 1000 2000 kHz DOSC1 Main Clock Duty Cycle 3V ¾ 40 50 60 % fX1 Pager Clock Input (Crystal OSC) 3V ¾ 32.768 76.8 153.6 kHz tRESET RESET Input Pulse Width ¾ ¾ 1 ¾ ¾ ms Functional Description Memory map 0 0 0 0 H 0 0 3 B H 0 0 4 0 H 0 0 6 D H 0 0 8 0 H 0 1 C F H 0 1 D 0 H 0 1 F F H 0 2 0 0 H 0 3 F F H I/O a n d D a ta S p a c e 6 0 B y te s 1 0 0 0 H M e s s a g e B u ffe r 4 6 B y te s G lo b a l D a ta M e m o r y 3 3 6 B y te s In te rn a l C h a ra c te r R O M S p a c e (B a n k 0 ) 8 K b y te s 2 F F F H S ta c k s 4 8 B y te s B a n k 0 ~ B a n k 3 1 ( 2 M b its ) G lo b a l D a ta M e m o r y 5 1 2 B y te s 1 0 0 0 H 1 0 0 0 H In te r n a l/E x te r n a l C h a ra c te r R O M 8 K b y te s E x te rn a l C h a ra c te r R O M S p a c e (B a n k 0 ) 8 K b y te s 2 F F F H 2 F F F H 3 0 0 0 H In te r n a l/E x te r n a l S R A M 8 K b y te s B a n k 0 ~ B a n k 3 1 ( 2 M b its ) 4 F F F H 5 0 0 0 H 3 0 0 0 H P ro g ra m R O M S p a c e 2 8 K B y te s In S S (B te rn a l R A M p a c e a n k 0 ) 8 K b y te s 4 F F F H B F F F H C 0 0 0 H B a n k 0 ~ B a n k 3 (3 2 K B y te s ) P ro g ra m R O M S p a c e 1 6 3 7 8 B y te s F F F A H N M I-L F F F B H 3 0 0 0 H N M I-H F F F C H 4 F F F H R E S E T -L F F F D H R E S E T -H F F F E H B a n k 0 ~ B a n k 3 1 (2 5 6 K B y te s ) IR Q -L F F F F H E x te rn a l S R A M S p a c e (B a n k 0 ) 8 K b y te s IR Q -H 7 April 28, 2000 Preliminary HT9580 HT9580 HT9580 HT9580 memory mapping table (I/O and data space) Register Name Bit 7 Bit 6 0000H 0000H Config. HALT CLK_SEL 0001H 0001H WDT-TMR X X 0002H 0002H CLR WDT X X Address Bit 5 Bit 4 OSC_MOD LPM TMR0_PR1 TMR0_PR0 X X Bit 3 Bit 2 Bit 1 Bit 0 State on POR 0001 0000 RTC BZ_CLK MDUT MGEN WDTEN WS2 WS1 WS0 0000 0111 X X X X uuuu uuuu 0003H 0003H BZ-L BZL7 BZL6 BZL5 BZL4 BZL3 BZL2 BZL1 BZL0 0000 0000 0004H 0004H BZ-H BZH7 BZH6 BZH5 BZH4 BZH3 BZH2 BZH1 BZH0 0000 0000 0005H 0005H INT ctrl 0 0 0 RTCEN ORMSK RTCMSK 0006H 0006H INT flag 0 RTC_FG DR_FG BF_FG WDTOVFG OR_FG 0007H 0007H TMRC TMR1MOD X TMR1EN TMR0EN 0000 0000 0008H 0008H TMR1L TM1D7 TM1D6 TM1D5 TM1D4 TM1D3 TM1D2 TM1D1 TM1D0 uuuu uuuu TMR1CLK TMR0CLK TMR1EDG TMR0EDG TM1IMSK TM0IMSK 0000 1111 TM1OVFG TM0OVFG 0000 0000 0009H 0009H TMR1H TM1D15 TM1D15 TM1D14 TM1D14 TM1D13 TM1D13 TM1D12 TM1D12 TM1D11 TM1D11 TM1D10 TM1D10 TM1D9 TM1D8 uuuu uuuu 000AH 000AH TMR0 TM0D7 TM0D6 TM0D5 TM0D4 TM0D3 TM0D2 TM0D1 TM0D0 uuuu uuuu 000BH 000BH PA data X X PA5 PA4 PA3 PA2 PA1 PA0 uu11 1111 000CH 000CH PB data PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 1111 1111 000DH 000DH PC data X X X X X X PC1 PC0 uuuu uu11 uu11 1111 000EH 000EH PAC X X PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 000FH 000FH PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC3 PBC1 PBC0 1111 1111 0010H 0010H PCC X X X X X X PCC1 PCC0 uuuu uu11 0011H 0011H PA WUE X X PAWUE5 PAWUE4 PAWUE3 PAWUE2 PAWUE1 PAWUE0 uu00 0000 0012H 0012H PA IM X X PAIM5 PAIM4 PAIM3 PAIM2 PAIM1 PAIM0 uu11 1111 0013H 0013H PB IM PBIM7 PBIM6 PBIM5 PBIM4 PBIM3 PBIM2 PBIM1 PBIM0 1111 1111 0014H 0014H PC IM X X X X X X PCIM1 PCIM0 uuuu uu11 0015H 0015H MROM-BP BP_MODM1 BP_MODM0 M_BP5 M_BP4 M_BP3 M_BP2 M_BP1 M_BP0 0000 0000 0016H 0016H SRAM-BP BP_MODS1 S_BP5 S_BP4 S_BP3 S_BP2 S_BP1 S_BP0 0000 0000 0017H 0017H LCD_CTRL LCD-CLK CLK-MOD LCD-CS1 LCD-CS0 LCD-A0 LCD-WRB 0000 1101 0018H 0018H LCD_CMD LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 uuuu uuuu 0019H 0019H Decoder Control/ flag X BL OR X STB X RES ON uu0u uu01 001AH 001AH~ 002EH 002EH Decoder Configuration Memory BP_MODS0 LCD-CHIP1 LCD-CHIP0 uuuu uuuu 002FH 002FH D/A-L DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000 0000 0030H 0030H D/A-H X X X X X D/A_PD RSSI BAT uuuu u1uu 0031H 0031H Buffer Status MSG_END X count_5 count_4 count_3 count_2 count_1 count_0 0uuu uuuu 0032H 0032H SPI-CONFIG S/M LEN1 LEN0 REQST SPIFG CLK_EDG SPI_EN START 0111 1000 0033H 0033H SPI-SPEED SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0000 0000 0034H 0034H SPI-OUT3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0035H 0035H SPI-OUT2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0036H 0036H SPI-OUT1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0037H 0037H SPI-OUT0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0038H 0038H SPI-IN3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0039H 0039H SPI-IN2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 003AH 003AH SPI-IN1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 003BH 003BH SPI-IN0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 8 April 28, 2000 Preliminary HT9580 HT9580 HT9580 HT9580 memory attribute table (I/O and data space) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR 0000H 0000H Config. R/W R/W R/W R/W R/W R/W R/W R/W 0001 0000 0001H 0001H WDT-TMR X X R/W R/W R/W R/W R/W R/W 0000 0111 0002H 0002H CLR WDT W W W W W W W W uuuu uuuu Address 0003H 0003H BZ-L R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0004H 0004H BZ-H R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0005H 0005H INT ctrl 0 0 0 R/W R/W R/W R/W R/W 0000 1111 0006H 0006H INT flag 0 R/W R/W R R/W R/W R/W R/W 0000 0000 0007H 0007H TMRC R/W X R/W R/W R/W R/W R/W R/W 0000 0000 0008H 0008H TMR1L R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 0009H 0009H TMR1H R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 000AH 000AH TMR0 R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 000BH 000BH PA data X X R/W R/W R/W R/W R/W R/W uuuu uuuu 000CH 000CH PB data R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 000DH 000DH PC data X X X X X X R/W R/W uuuu uuuu 000EH 000EH PAC X X R/W R/W R/W R/W R/W R/W uu11 1111 000FH 000FH PBC R/W R/W R/W R/W R/W R/W R/W R/W 1111 1111 0010H 0010H PCC X X X X X X R/W R/W uuuu uu11 0011H 0011H PA WUE X X R/W R/W R/W R/W R/W R/W uu00 0000 0012H 0012H PA IM X X R/W R/W R/W R/W R/W R/W uu00 0000 0013H 0013H PB IM R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0014H 0014H PC IM X X X X X X R/W R/W uuuu uu00 0015H 0015H MROM-BP R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0016H 0016H SRAM-BP R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0017H 0017H LCD_CTRL R/W R/W R/W R/W R/W R/W R/W R/W 0000 1101 0018H 0018H LCD_CMD R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 0019H 0019H Decoder Control/ flag X R/W R X R X R/W R/W uu0u uu01 001AH 001AH~ 002EH 002EH Decoder Configuration Memory R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu 002FH 002FH D/A-L R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0030H 0030H D/A-H X X X X X R/W R R uuuu u1uu 0031H 0031H Buffer Status R X R R R R R R 0uuu uuuu 0032H 0032H SPI-CONFIG R/W R/W R/W R R R/W R/W R/W 0111 1000 0033H 0033H SPI-SPEED R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0034H 0034H SPI-OUT3 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0035H 0035H SPI-OUT2 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0036H 0036H SPI-OUT1 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0037H 0037H SPI-OUT0 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000 0038H 0038H SPI-IN3 R R R R R R R R 0000 0000 0039H 0039H SPI-IN2 R R R R R R R R 0000 0000 003AH 003AH SPI-IN1 R R R R R R R R 0000 0000 003BH 003BH SPI-IN0 R R R R R R R R 0000 0000 Note: ²R² Read Only ²W² Write Only ²R/W² Read or Write ²X² N/A 9 April 28, 2000y Preliminary HT9580 HT9580 Configuration register Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR 0000H 0000H Config. HALT CLK_SEL OSC_MOD LPM RTC BZ_CLK MDUT MGEN 0001 0000 Oscillator configuration ²OSC_MOD² bit selects the OSC input clock to be either RC or DF. If ²OSC_MOD² is set to ²low² then the RC configuration is selected, otherwise the DF application is selected. The programmer should note that the condition of ²CLK_SEL², ²HALT² and ²OSC_MOD² assures that the system clock is working properly. It is recommended that the OSC clock source is either DF or RC. If DF and RC are necessary, it is required to switch the system clock to X1-clock before switching between DF and RC. Then switch the system clock back to the OSC input by using bit CLK_SEL if the switching action of DF and RC is complete. Before enter HALT mode, the system clock must select X1-clock. There are two clock source input pins on the chip, the main clock and the pager decoder input clock. The main clock is generated by an RC network. The system clock may be the OSC inp u t o r t he X 1 - c l oc k d ep end i ng o n b i t ²CLK_SEL². The pager decoder input clock comes from two external pins, X1 and X2. The frequency of the sub-clock will be double that of the X1, X2 input clock. The OSC1 main clock will be generated from an RC network that needs an external resistor (see Application Circuit). The system clock may be X1-clock, DF or RC clock. If no higher frequency (RC) is needed, the external resistor between OSC1 and OSC2 can be removed. The system clock can be switched by bit ²CLK_SEL². If ²CLK_SEL²=0 (POR State), the system clock will be X1-clock. In other cases, with ²CLK_SEL²=1, the OSC input clock will be the system clock. The clock switching function will assist software programmers to change the mC system clock within an adequate time if necessary. The M a in C lo c k O S C 1 O S C _ M O D O S C C o n tro l X 1 - c lo c k S S T 1 0 - b it R ip p le C o u n te r F re q u e n c y D o u b le r D F S u b - c lo c k 0 : R C 1 : D F O S C In p u t The HT9580 HT9580 will generate two RTC frequencies, 1Hz and 2Hz respectively, determined by bit RTC. If the bit is logic low, the 1Hz RTC frequency will be selected, otherwise the 2Hz RTC frequency will be selected. The RTC counter is enabled/disabled by bit RTCEN and can be masked or not masked as determined by the bit RTCMSK of the interrupt control register X 1 - c lo c k X 1 S S T C o n tro l H A L T C lo c k S e le c t C L K _ S E L S y s te m C lo c k 0 : X 1 - c lo c k 1 : O S C In p u t 1 H z & T im e O u t X 1 - c lo c k C o u n te r R T C 2 H z & T im e O u t T im e O u t R T C RTC block diagram 10 April 28, 2000 Preliminary (0005H 0005H). If the RTC counter is enabled, the RTC counter will start to count. The RTC counter source clock is the X1-clock, so the X1 clock setting via by SPF12 SPF12, SPF13 SPF13 and SPF14 SPF14 should be correct. V RTC L P M (L o w p o w e r m o d e c o n tr o l) 5 0 k W X 2 H T 9 5 8 0 5 0 k W X 1 1 0 0 k W 0 Select 2Hz as the RTC D D 1 0 0 k W In order to guarantee that the system clock has started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulse when the system is powered up. 1 HT9580 HT9580 Select 1Hz as the RTC V S S L o w p o w e r o s c illa to r fu n c tio n low power oscillator The low power oscillator of the pager decoder input clock should be crystal type. The decoder subsystem low power oscillator, on the other hand, is of a crystal type which is designed with a power on start-up function to reduce the stabilization time of the oscillator. This start-up function is enabled by bit ²LPM² which is initially set high at power on reset, and should be cleared to low so as to enable the low-power oscillator function. The oscillator configuration is running in the low power mode. circuit is powered up, when the bit is low. When this bit is set high, the CPU is also stopped. When this bit is cleared low, the CPU core returns to its normal operation. After this is set HIGH by the software, it may also be cleared low when reset, interrupt (IRQ or NMI), RTC timeout, and port wake-up conditions are met. 0 The system clock oscillator can be enabled/disabled by the register bit, ²HALT². The system clock circuit is powered down, when the bit is set to high. On the other hand, the system clock 1 System clock HALT enable System clock powered down The WDT is a 16-bit counter and sourced by the WDT-TMR (Watchdog timer) register Address Register Name Bit 7 Bit 6 0001H 0001H WDT-TMR X X 0002H 0002H CLR WDT X X Bit 5 Bit 4 X Bit 2 Bit 1 Bit 0 WDTEN WS2 WS1 WS0 0000 0011 X TMR0_PR1 TMR0_PR0 X State on POR Bit 3 X X X uuuu uuuu be executed before the timer overflows. The clear-WDT operation is to write any number to the register, CLRWDT (0002H 0002H). When the watchdog timer overflows (checked by bit 3 of 0006H 0006H ²WDTOVFG²), the program counter is set to FFFC H and FFFD H to read the program start vector. The definitions of the control bits are listed below. sub-clock divided by 8. The counter is segmented as a 9-bit prescaler and a 7-bit user programmable counter. The input clock is first divided by 512 (9-stage) to get the nominal time-out period. The output of the 9-bit pre-scaler can then be divided by a 7-bit programmable counter to generate the longer watchdog time-out depending on the user¢s requirements. The 7-bit programmable counter is controlled by 3 register bits, WS0~2. The watchdog timer is enabled/disabled by a control bit WDTEN. To prevent the overflow of this watchdog timer, a clear-WDT operation should 1 Enable the WDTEN watchdog timer 11 0 Disable the watchdog timer April 28, 2000 Preliminary The WDT 7-bit counter is programmed by bits WS0~WS2. The division ratio for the counter is listed in the table. WS2 WS1 WS0 0 0 1:1 0 0 1 0 1 0 1 1 The other pair ²TMR0_PR0² and ²TMR0_PR1² are used to select the prescaler ratio for timer0. The definition is shown in the table. Division Ratio 0 HT9580 HT9580 TMR0_PR1 TMR0_PR0 TMR0 Prescaler Ratio 1:2 0 0 1/4 0 1:4 0 1 1/8 1 1:8 0 0 1:16 1 0 1/16 1 0 1 1:32 1 1 1/32 1 1 0 1:64 1 1 1 1:128 1 /8 X 1 - c lo c k 9 - b it P r e s c a le r W S 0 ~ 2 7 - b it C o u n te r 8 to 1 M U X W D T tim e - o u t Buzzer generator registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 State on POR Bit 0 0003H 0003H BZ-L BZL7 BZL6 BZL5 BZL4 BZL3 BZL2 BZL1 BZL0 0000 0000 0004H 0004H BZ-H BZH7 BZH6 BZH5 BZH4 BZH3 BZH2 BZH1 BZH0 0000 0000 clock source of the buzzer is selected by bit ²BZ_CLK². When BZ_CLK=0, the clock source is the system clock. On the other hand, when BZ_CLK=1, the value of the selector will be the X1-clock. The buzzer generator is composed of a 16-bit PFD counter and a duty cycle control. The counter value is set by two registers, namely BZ-H and BZ-L. The source for this generator may be the system clock or the X1-clock. The buzzer generator is enabled/disabled by the register bit ²MGEN² in the configuration register(0000H 0000H). When this bit is set high, the buzzer generator is activated. There is another bit in the configuration register(0000H 0000H) which controls the buzzer output volume, bit ²MDUT². If the bit is logic high, the output of the BZ will be modulated by the X1-clock. The The truth table for enabling/disabling the buzzer generator is shown in the table. 1 MGEN 12 0 Enable the Disable the buzzer generator buzzer generator April 28, 2000 Preliminary the application circuits is always active. Therefore it is recommended that both BZ-L and BZ-H be cleared and that the ²MGEN² bit in the configuration register (0000H 0000H) also be cleared, when it is desired to disable or stop the buzzer. When BZ-L and BZ-H are all 00H, the tone generator is disabled and BZ is high. The value of t h e f r eq uenc y d i v i d er, r a ng es fr o m 2 (BZ-L=01H, BZ-H=00H)~65536 (BZ-L=FFH, BZ-H=FFH). Writing to BZ-L only writes the data into a low byte buffer, while writing to BZ-H will write the high byte data and the contents of the low byte buffer into the PFD counter. The output of the 16-bit PFD counter is divided by 2 to generate a BZ output with or without modulation. For example, if the desired output of BZ is 1.6kHz with modulation and the frequency source is X1-clock (76.8kHz), then the value of 16-bit PFD counter is set to BZ-L=17H, BZ-H=00H and ²MDUT² is set high. When the buzzer generator is disabled by clearing the ²MGEN² bit in the configuration register (0000H 0000H), the BZ pin remains at its last state. If the BZ pin is low, the BZ transistor in S y s te m C lo c k X 1 - c lo c k HT9580 HT9580 X 1 - c lo c k B Z _ C L K = 0 1 6 - b it P F D C o u n te r B Z _ C L K = 1 P W M M o d u la to r ¸ 2 M G E N B Z _ C L K B Z M D U T M D U T = 0 M D U T = 1 Interrupt registers Register Name Bit 7 0005H 0005H INT ctrl 0 0006H 0006H INT flag 0 Address Bit 6 Bit 5 Bit 4 0 0 RTC_FG DR_FG Bit 1 Bit 0 State on POR Bit 3 Bit 2 RTCEN ORMSK RTCMSK TM1IMSK TM0IMSK 0000 1111 BF_FG WDTOVFG OR_FG TM1OVFG TM0OVFG 0000 0000 A battery fail condition is triggered by a high to low transition on pin BAF and will set the battery fail interrupt request flag BF_FG to logic high. For details, refer to the POCSAG Decoder section. The sources for the IRQ are timer 0 overflow, timer 1 overflow, out-of-range status changes and RTC time out. The four interrupt sources all could be masked, but the four corresponding interrupt flags will still be set when the interrupt conditions are met. All the four flags are readable/writeable. When an interrupt condition is met, a flag will be set. If an interrupt routine is performed, the software should check which flag is set to high then determine what kind of interrupt source occurred. The WDTOVFG is the flag for the watchdog There are two interrupts for the HT9580 HT9580: a Non-Mask Interrupt (NMI) and a generic interrupt request (IRQ). The data ready interrupt and battery fail interrupt share the NMI call location. Which interrupt occurred can be determined by checking bit BF_FG and the data ready interrupt bit DR_FG or SPI complete flag SPIFG (in SPI-CONFIG register). DR_FG is the data ready interrupt indication bit. When a valid call is detected, data begins to transfer. Either one call is terminated or a message buffer is full or one batch is over but the message is not terminated, the data ready interrupt will occur and DR_FG is set high. The DR_FG bit should be cleared low by the mC software after a data ready condition has occurred. 13 April 28, 2000 Preliminary timer overflow and RTC_FG is an indicator for the RTC time out interrupt request flag. The OR_FG will be set high when an out-of-range status from low to high or high to low transition occurrs. Those flags such as TM0OVFG, TM1OVFG, BF_FG, DR_FG, OR_FG and RTC_FG should be cleared by the software after they are activated. 1 HT9580 HT9580 1 0 TM0OVFG Timer 0 overflows No timer 0 overflow TM1OVFG Timer 1 overflows No timer 1 overflow Watchdog WDTOVFG timer has overflown 0 No watchdog timer overflow RTCEN RTC counter is enabled RTC counter is disabled BF_FG Battery fail request No battery fail request RTCMSK RTC interrupt is masked RTC interrupt is not masked DR_FG Data ready request No data ready request TM0IMSK Timer 0 overflow Timer0overflow interrupt is interruptisnot masked masked OR_FG Out-of-range request No out-of-range request Timer 1 overflow interrupt is not masked RTC_FG RTC interrupt request TM1IMSK Timer 1 overflow interrupt is masked No RTC interrupt request ORMSK Out-of-range interrupt is masked Out-of-range interrupt is not masked D a ta R e a d y S P I R e q s t B a tte r y F a il N M I M 6 5 0 2 C o r e T M 0 /1 IM S K T M 0 /1 O V F G R T C _ F G IR Q R T C M S K O R _ F G O R M S K Block diagram of NMI and IRQ 14 April 28, 2000 Preliminary tim e r 0 o v e r flo w tim e r 1 o v e r flo w S tim e r 0 o v e r flo w S tim e r 1 o v e r flo w S S HT9580 HT9580 tim e r 0 o v e r flo w tim e r 0 o v e r flo w S tim e S IR Q M a s k e d b y T M 0 O V F G M a s k e d b y T M 0 IM S K M a s k e d b y T M 1 O V F G T M 0 IM S K T M 1 IM S K C le a r e d b y s o ftw a r e C le a r e d b y s o ftw a r e C le a r e d b y s o ftw a r e T M 0 O V F G C le a r e d b y s o ftw a r e C le a r e d b y s o ftw a r e T M 1 O V F G Timer0 and Timer1 timing diagram Reset conditions transition on the chip reset will then cause an initialization sequence to begin. After the system is operating, a low on this line of at least 1 ms in duration will cause mC activity. When a positive edge is detected, there is an initialization sequence lasting 8-clock cycles. Then the interrupt mask flag is set, the decimal mode is cleared and the program counter is loaded with the restart vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. This input should be high during normal operation. The HT9580 HT9580 will reset the whole chip when the following conditions are met: · Power On · The external RESET pin is held low for at least 1 ms · The WDT overflows The input is used to reset the mC. Reset must be held low at least 1 ms after VDD reaches operating voltage from a power down. A positive 15 April 28, 2000 Preliminary HT9580 HT9580 5 0 0 0 H P ro g ra m R O M S p a c e F F F A H F F F B H V D a ta R e a d y & B a tte r y F a il S e r v ic e R o u tin e V e c to r L o w B y te D a ta R e a d y & B a tte r y F a il S e r v ic e R o u tin e V e c to r H ig h B y te F F F C H P ro g ra m R e s e t V e c to r L o w F F F D H P ro g ra m D D R E S E T B y te R e s e t V e c to r H ig h B y te F F F E H IR Q S e r v ic e R o u tin e V e c to r L o w F F F F H IR Q H T 9 5 8 0 S e r v ic e R o u tin e V e c to r H ig h B y te R E S E T In te r n a l P u ll- u p S y s te m C lo c k B y te P o w e r O n D e te c to r 1 0 - b it R ip p le C o u n te r C h ip R e s e t G e n e r a to r W D T O v e r flo w V D D V D D 1 0 2 4 C lo c k C y c le s 8 C lo c k C y c le s R E S E T O S C R E S E T T im e - O u t W D T T im e - O u t C h ip R e s e t C h ip R e s e t RESET active and WDT time-out Power on reset timing 16 April 28, 2000 Preliminary HT9580 HT9580 Timer registers Register Name Bit 7 0007H 0007H TMRC 0008H 0008H TMR1L 0009H 0009H 000AH 000AH Address State on POR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR1MOD X TMR1CLK TMR0CLK TMR1EDG TMR0EDG TMR1EN TMR0EN 0u00 0000 TM1D7 TM1D6 TM1D5 TM1D4 TM1D3 TM1D2 TM1D1 TM1D0 uuuu uuuu TMR1H TM1D15 TM1D15 TM1D14 TM1D14 TM1D13 TM1D13 TM1D12 TM1D12 TM1D11 TM1D11 TM1D10 TM1D10 TM1D9 TM1D8 uuuu uuuu TMR0 TM0D7 TM0D6 TM0D5 TM0D4 TM0D3 TM0D2 TM0D1 TM0D0 uuuu uuuu buffer into the Timer Counter preload register (16-bit). Note that the Timer counter preload register contents are changed by a TMR1H write operation while writing to TMR1L does not change the contents of the preload register. Reading TMR1H will also latch the contents of TMR1L into the byte buffer to avoid false timing problem. Reading TMR1L returns the contents of the low byte buffer. In other words, the low byte of the timer counter cannot be read directly. It must first read TMR1H to latch the low byte contents of the timer counter into the buffer. TMRC is the timer counter control register, which defines the timer counter options. The timer1 clock source can be selected from either the internal clock or an external input clock by bit TMR1MOD of the TMRC register. The timer0/timer1 can also select its clock source by bits TMR0CLK/TMR1CLK. TMRC as shown in the table. In addition to the watchdog timer, the HT9580 HT9580 provides two timers: an 8-bit timer (timer 0) and one 16-bit timer (timer 1). Those two timers are controlled and configured by the register TMRC. Both timers are programmable up-count counters whose clocks may be derived from the X1-clock (32.768kHz, 76.8kHz or 153.6kHz). To program the timers, TMR0, TMR1L, and TMR1H should be written with a start value. When the timers are enabled, they will count-up from the start value. If the timers overflow, corresponding interrupts will be generated. When the timers are disabled, the counter contents will not be reset. To reset the counter contents, the software should write the start value again. Since timer1 is a 16-bit counter, it is important to note the method of writing data to both TMR1L and TMR1H. Writing to TMR1L only writes the data into a low byte buffer, while writing to TMR1H will simultaneously write the high byte data and the contents of the low byte Labels (TMRC0 and TMRC1) Bits Function TMR0EN, TMR1EN 0 1 Enable/disable timer counting (0=disable; 1=enable) TMR0EDG, TMR1EDG 2 3 Define the TMR0 and TMR1 active edge (0=active on low to high; 1=active on high to low) TMR0CLK 4 Select TMR0 clock source (0=X1-clock; 1=OSC1 input clock/system clock) TMR1CLK 5 Select TMR1 clock source if internal clock input is selected (0=X1-clock; 1=OSC1 input clock/system clock) TMR1MOD 7 Define the TMR1 operation mode (0=internal clock input; 1=external clock input) 17 April 28, 2000 Preliminary S y s te m T M R 0 C L K 1 C lo c k D a ta B u s T im e r C o u n te r P r e lo a d R e g is te r 0 X 1 - C lo c k HT9580 HT9580 P r e s c a le r T M R 0 _ P R 1 E d g e S e le c t T M R 0 _ P R 0 T im e r 0 C o u n te r ( 8 - b it) T M R 0 E D G R e lo a d O v e r flo w T o In te rru p t T M R 0 E N Timer 0 block diagram S y s te m T M R 1 C L K 1 C lo c k X 1 - C lo c k D a ta B u s T im e r /e v e n t C o u n te r P r e lo a d R e g is te r 0 R e lo a d 0 T M R 1 E d g e S e le c t 1 T M R 1 M O D T im e r 1 C o u n te r ( 1 6 - b it) T M R 1 E D G O v e r flo w T o In te rru p t T M R 1 E N Timer 1 block diagram 18 April 28, 2000 Preliminary HT9580 HT9580 I/O port configuration registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR uu11 1111 000BH 000BH PA data X X PA5 PA4 PA3 PA2 PA1 PA0 000CH 000CH PB data PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 1111 1111 000DH 000DH PC data X X X X X X PC1 PC0 uuuu uu11 000EH 000EH PAC X X PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 uu11 1111 000FH 000FH PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 1111 1111 0010H 0010H PCC X X X X X X PCC1 PCC0 uuuu uu11 0011H 0011H PA WUE X X PAWUE5 PAWUE4 PAWUE3 PAWUE2 PAWUE1 PAWUE0 uu00 0000 0012H 0012H PA IM X X PAIM5 PAIM4 PAIM3 PAIM2 PAIM1 PAIM0 uu11 1111 0013H 0013H PB IM PBIM7 PBIM6 PBIM5 PBIM4 PBIM3 PBIM2 PBIM1 PBIM0 1111 1111 0014H 0014H PC IM X X X X X X PCIM1 PCIM0 uuuu uu11 The HT9580 HT9580 has three general purpose I/O ports. The I/O cell structures are configurable. Details are shown in the table. Port B Port B is a general-purpose I/O port controlled by the PBC register. The PBIM register controls the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resistors. Port A Port A is a general-purpose I/O port. The PAC register controls the data directions for port A. When set as input data type, this port has wake-up capability and the input cell structures are schmitt trigger types. While in a ²HALT² condition, a falling edge signal on Port A can wake-up the mC. In addition, the input cell structures can be configured as pull-high or non-pull-high. When set as an output data type, the output structures are CMOS outputs. 1 1 The pin output logic high PBC PAC As input pin Output pin PBIM Port C As output pin PAIM Input pin CMOS input CMOS input structure with structure without pull-high pull-high resistor resistor PB The pin output logic low CMOS input structure with pull-high resistor Pin output logic low 0 PA The pin has PAWUE wake-up capability 0 Pin output logic high This is a general-purpose I/O port contolled by the PCC register. The PCIM register controls the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resistors. The pin has no wake-up capability 1 PC CMOS input structure without pull-high resistor The pin output logic high 0 The pin output logic low PCC As output pin PCIM 19 As input pin CMOS input structure with pull-high resistor CMOS input structure without pull-high resistor April 28, 2000 Preliminary V E N M D D U P u ll- u p R e s is to r X P A D a ta HT9580 HT9580 P A C P A W U E P A IM O n e S h o t C ir c u it T o C P U I/O structure of port A Mask ROM (Character ROM) bank point register Address 0015H 0015H Register Name Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR M_BP5 M_BP4 M_BP3 M_BP2 M_BP1 M_BP0 0000 0000 Bit 6 MROM-BP BP_MODM1 BP_MODM0 (BP_MODM1, BP_MODM0)=(1, 0), selects the external Mask ROM device. The internal Mask ROM can switch from bank 0 to bank 31 and the external Mask ROM can switch from bank 0 to bnak 31 by software programming. In addition, the address range of the internal/external Mask ROMwillallrangefrom1000Hto2FFFH. The Mask ROM bank point register can switch between the internal 2 Mbits Mask ROM or an external up to 2 Mbits Mask ROM space. The selection table is based on the following table. The space size of each Mask ROM bank is 8 Kbytes. The bits BP_MODM1 and BP_MODM0 define whether internal or external Mask ROM devices are used. (BP_MODM1, BP_MODM0)=(0, 1), sel e c t s t he i nter na l M a s k RO M d e v i c e . BP_MODM1 BP_MODM0 M_BP5 The Mask ROM bank point register selection table is shown in the table. M_BP4 M_BP3 M_BP2 0 0 X X X X M_BP1 M_BP0 BP Value X X 0 1 0 0 0 0 0 0 0 1 ¯ Internal 2 Mbits Mask ROM (low 8 Kbytes) ¯ 1 1 1 31 0 0 0 32 Reserved ¯ Reserved 1 63 Reserved 0 0 External 2 Mbits Mask ROM (low 8 Kbytes) 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 ¯ ¯ 1 0 Internal 2 Mbits Mask ROM (High 8 Kbytes) 1 1 Reserved ¯ 0 0 Memory Area X ¯ 1 1 20 1 ¯ 31 External 2 Mbits Mask ROM (High 8 Kbytes) April 28, 2000 Preliminary HT9580 HT9580 If the internal 2 Mbits mask ROM is placed as shown in the figure and the software programmer obtains a start address from CNS (Taiwan) code or a GB (China) code, A0~A17. The following steps will map from the start address to the bank point register, then the hardware address decode circuit will point to the real 2 Mbits space. (If the internal mask ROM is selected.) 0 0 0 0 0 H C N S P a tte rn (G B P a tte rn ) (A 1 8 = "0 ") 3 F F F F H 4 0 0 0 0 H R e s e rv e d (A 1 8 = "1 ") · Step 1 7 F F F F H · Step 5 The formula obtains A0~A18 from the received GB or CNS code. If it is in the lower 2 Mbits space, A18=0. Otherwise, A18=1 if it is in reserved space. The following example will load 32 bytes continuous (one Chinese word) pattern from the internal mask ROM and store them to the start address $C3C2C1C0 H (if absolute index addressing mode is used). · Step 2 Set (BP_MODM1, BP_MODM0)=(0, 1) LDX #00H LDY #00H READ: LDA $B3B2B1B0, X STA $C3C2C1C0, Y INX INY CPX #20H BNZ READ · Step 3 Assign correct ²M_BP0²~²M_BP5² as shown: A13®M_BP0 A14®M_BP1 ¨ A15®M_BP2 ¨ A16®M_BP3 ¨ A17®M_BP4 ¨ A18®M_BP5 (the bit will be 0 at this condition) · Step 4 Adding $1000 H to A12~A0 to get new HEX value $B3B2B1B0 H. ¨ ¨ 0 0 0 A 1 2 A 1 1 A 1 0 0 0 0 1 0 0 0 0 A 1 1 A 1 0 B 3 R A 1 3 R A 1 2 (0 ,0 ,R A 1 3 ,R A 1 2 ) B 2 A 9 0 A 8 0 A 9 A 7 A 6 0 A 8 0 A 7 (A 1 1 ,A 1 0 ,A 9 ,A 8 ) 21 A 6 B 1 A 5 0 A 4 0 A 5 A 3 A 2 0 A 4 (A 7 ,A 6 ,A 5 ,A 4 ) 0 A 3 A 2 B 0 A 1 0 A 0 0 A 1 A 0 (A 3 ,A 2 ,A 1 ,A 0 ) April 28, 2000 Preliminary HT9580 HT9580 SRAM bank point register Address Register Name 0016H 0016H SRAM-BP Bit 7 Bit 5 BP_MODS1 BP_MODS0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR S_BP5 Bit 6 S_BP4 S_BP3 S_BP2 S_BP1 S_BP0 0000 0000 vices. (BP_MODS1, BP_MODS0)=(1, 0), is for external SRAM devices. The internal SRAM would switch from bank 0 to bank 3 and the external SRAM would switch from bank 0 to bank 31 by software programming. In addition, the address range of the internal/external SRAM will all range from 3000H 3000H to 4FFFH. The SRAM bank point register can switch to either external 256 Kbytes or internal 32 Kbytes SRAM space. The selection table is based on the following table. The space size of each SRAM bank is 8 Kbytes. Bits BP_MODS1 and BP_MODS0 define whether internal or external SRAM devices are used. (BP_MODS1, BP_MODS0)=(0, 1), is for internal SRAM deBP_MODS1 BP_MODS0 S_BP5 S_BP4 S_BP3 S_BP2 S_BP1 S_BP0 BP Value Memory Area 0 0 X X X X X X X Reserved 0 1 0 0 0 0 0 0 0 Internal 32 Kbits SRAM (Low 8 Kbytes) 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 ¯ ¯ 0 1 1 1 0 0 ¯ 3 Internal 32 Kbits SRAM (High 8 Kbytes) 4 Reserved ¯ Reserved 1 63 Reserved 0 0 External 256 Kbits SRAM (Low 8 Kbytes) ¯ ¯ 1 31 External 256 Kbits SRAM (High 8 Kbytes) ¯ ¯ LCD control and data register Address Register Name Bit 7 0017H 0017H LCD_CTRL LCD-CHIP1 0018H 0018H LCD_CMD LCD_D7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LCD-CHIP0 LCD-CLK CLK-MOD LCD-CS1 LCD_D6 LCD_D5 LCD_D4 LCD_D3 State on POR Bit 1 Bit 0 LCD-CS0 LCD-A0 LCD-WRB 0000 1101 LCD_D2 LCD_D1 LCD_D0 uuuu uuuu LCD-CTRL register corresponds to the chip select pin of the LCD driver. The bit ²LCD-CS0² is used to control the master LCD driver chip while ²LCD-CS1² is for the slave LCD driver chip. Both bits are active low. The bit ²CLK_MOD² is used to enable or disable the pin out of LCD_CL. If the bit is set low, the clock output of pin LCD_CL will be disabled, otherwise the LCD_CL clock will be set according to the following Truth Table. The LCD control and command registers are used for LCD driver interface. There are three kinds of LCD driver chips available for the HT9580 HT9580. These LCD drivers are SED15X SED15X(KSX) series, Motorola LCD driver chip MC141X MC141X series and HD66410 HD66410 respectively according to the following ²LCD-CHIP0² and ²LCD-CHIP1² bit table settings. The combination of the LCD_CMD and LCD-CTRL registers can control the SED15X SED15X(KSX), MC141X MC141X series or HD66410 HD66410 LCD drivers. Bits LCD-CS0/1 of the 22 April 28, 2000 Preliminary HT9580 HT9580 ²LCD-CHIP0² and ²LCD-CHIP1² Truth Table LCD-CHIP0=²0² LCD-CHIP0=²1² LCD-CHIP1=²0² SED15X SED15X(KSX) series LCD driver is MC141X MC141X series LCD driver is selected selected LCD-CHIP1=²1² HD66410 HD66410 LCD driver is selected N/A ²LCD_CL² Truth Table LCD-CHIP0=²0² LCD-CHIP0=²1² LCD-CHIP1=²0² LCD_CL: 2 kHz output LCD_CL: If ²LCD-CLK²=0, 32 kHz output If ²LCD-CLK²=1, X1-clock output LCD-CHIP1=²1² LCD_CL: 10.9kHz output N/A The following is a comparison table of the HT9580 HT9580 pin description between the SED15X SED15X (KSX) series and the MC141X MC141X series LCD driver. HT9580 HT9580 (Pin) LCD_A0 SED15X SED15X(KSX) Series A0 MC141X MC141X Series Data/command select input. A0=0: Display control data on D/C D0~D7 A0=1: Display data on D0~D7 This input pin acknowledges valid data on D0~D7. If high then D0~D7 contains display data, if low D0~D7 containscommanddata. LCD_CS0 CS (Master) When high, enables the Active low chip select input. CE (Master) control pins on the driver. (Master) (Master) LCD_CS1 CS (Slave) Active low chip select input. CE (Slave) (Slave) When high, enables the control pins on the driver. (Slave) D0~D7 8-bit, tristate, bidirectional I/O D0~D7 bus. Bidirectional bus for data/command transfer. Enable clock input CS This pin is normal low clock input. Data on D0~D7 is latched at the falling edge of CS. R/W To read the display data RAM or the internal status, pull this pin high. The pin low indicates a write operation. OSC2 Oscillator input for external clock is used. (32kHz or X1-clock output from HT9580 HT9580 as determined by the ²LCD-CLK²). LCD_E D0~D7 E LCD_RW R/W LCD_CL CL Read/write input External clock input. (2kHz output from HT9580 HT9580) 23 April 28, 2000 Preliminary L C D 5 L C D _ A 0 3 M a s te r S la v e C S (M a s te r) 2 L C D _ C S 1 ( S la v e ) C S ( S la v e ) 1 5 ~ 8 D 0 ~ D 7 D 0 ~ D 7 7 L C D _ E S E D 1 5 X (K S X ) E 6 L C D _ R W R /W 4 L C D _ C L D r iv e r A 0 L C D _ C S 0 (M a s te r) H T 9 5 8 0 HT9580 HT9580 C L T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 0 a n d "L C D -C H IP 0 " = 0 L C D D r iv e r 5 L C D _ A 0 3 L C D _ C S 0 (M a s te r) C E ( S la v e ) 1 5 ~ 8 D 0 ~ D 7 D 0 ~ D 7 7 L C D _ E M C 1 4 1 X C S 6 L C D _ R W L C D _ C L S la v e C E (M a s te r) 2 L C D _ C S 1 ( S la v e ) H T 9 5 8 0 M a s te r D /C R /W 4 O S C 2 T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 0 24 a n d "L C D -C H IP 0 " = 1 April 28, 2000 Preliminary L C D 5 L C D _ A 0 3 M a s te r C S ( S la v e ) 1 5 ~ 8 D 0 ~ D 7 D 0 ~ D 7 7 H D 6 6 4 1 0 R D L C D _ E 6 W R L C D _ R W 4 C R T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 1 LCD Driver Chip Selection LCD-CHIP0="0" LCD-CHIP1="0" LCD-CHIP0="1" LCD-CHIP1="0" S la v e C S (M a s te r) 2 L C D _ C S 1 ( S la v e ) L C D _ C L D r iv e r R S L C D _ C S 0 (M a s te r) H T 9 5 8 0 HT9580 HT9580 Application a n d "L C D -C H IP 0 " = 0 Note SEDX(EPSON) series LCD driver at 68 family MPU appli- RESET is low active cation mode. KSX(SAMSUNG) series LCD Pin options set as 68 family driver at 68 family MPU appliMPU application mode. cation mode. MC14X MC14X(MOTOROLA) series LCD driver. HD66410 HD66410(HITACHI) series LCD driver. LCD-CHIP0="0" LCD-CHIP1="1" SEDX(EPSON) series LCD d r i v e r a t 8 0 f a m i l y M P U RESET is high active application mode. KSX(SAMSUNG) series LCD Pin options set as 80 family driver at 80 family MPU appliMPU application mode. cation. LCD-CHIP0="1" LCD-CHIP1="1" N/A The contents of the on-chip RAM and of the register remain unchanged. Power down operation - HALT The HALT mode is initiated by setting the configuration register bit HALT high and results in the following . As the WDT and the WDT prescaler depend on software control, the WDT will continue to count when the ²HALT² bit is set high. The system clock turns off, the low power pager sub-clock, LCD driver, pager decoder and RTC all keep running. All the I/O ports remain in their original status. 25 April 28, 2000 Preliminary HT9580 HT9580 D/A registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 002FH 002FH D/A-L DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000 0000 0030H 0030H D/A-H X X X X X D/A_PD RSSI BAT uuuu u1uu Address Bit 2 Bit 0 State on POR BAF. The bit RSSI of DA-H register (0030H 0030H) is the output of another comparator. Its input at ²-² terminal is from the D/A output and ²+² terminal comes from the input pin RSSI. The software can detect the battery voltage and the RSSI signal by writing to the bits DA0 ~DA7 (002FH 002FH) and reading the bits BAT, RSSI (0030H 0030H). The system can quit the HALT mode by an external reset, an interrupt, an external falling edge signal on port A or an RTC time out. The HT9580 HT9580 has one internal 8-bit D/A converter which can measure the battery voltage and the RSSI input signal from the IF of the RF circuit. The DA0~DA7 is the digital input of the D/A converter and the analog outputs to the pin named DA_OUT. Bit BAT of the DA-H register (0030H 0030H) is the output of the comparator. Its input at the ²-² terminal is from the D/A output and the ²+² terminal comes from the input pin Bit ²D/A_PD² is used for the D/A power down control. If this bit is logic high, the D/A will be in the power down mode. Otherwise, the D/A is in the normal condition. For details see the following figure. R S S I R S S I V Bit 1 D D B A T B A T D /A _ P D V D D (D /A ) D A 7 D A 6 D A 5 V S S D A 4 D A 3 D A 2 D A 1 D A 0 D A _ O U T 2 R 2 R R 2 R R 2 R R 2 R R 2 R R 2 R 2 R R R 2 R T h e c o n fig u r a tio n o f th e 8 - b it D /A c o n v e r te r a n d p o w e r d o w n c o n tr o l 26 April 28, 2000 Preliminary HT9580 HT9580 Buffer status register Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State on POR 0031H 0031H Buffer Status MSG_END X count_5 count_4 count_3 count_2 count_1 count_0 0uuu uuuu The buffer status register will relay to the mC the status of the message buffer when the data ready request interrupt occurred. The ²MSG_END² bit will be set high when the data (including address codeword and message codeword) is at the end of this data ready interrupt call. The valid data length of the message buffer is determined by bit count_0 to count_5. If ²MSG_END² is low, the data length is more than 46 or data is not at the end, the mC should wait for the next data ready interrupt until the bit ²MSG_END² is set high. Example 1: if the data read from 0031H 0031H is ²95H² when a new data ready interrupt occurred, it means the total data length is 21 including the address codeword in this call and the message is terminated (bit ²MSG_END² =1). The figure below illustrates example 1. M e s s a g e B u ffe r 0 0 4 0 H A d d re s s C o d e w o rd 0 0 4 1 H M e s s a g e C o d e w o rd 1 0 0 4 2 H M e s s a g e C o d e w o rd 2 0 0 5 3 H M e s s a g e C o d e w o rd 1 9 0 0 5 4 H M e s s a g e C o d e w o rd 2 0 0 0 5 5 H N /A 0 0 6 D H N /A B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 1 0 0 1 0 1 0 1 0 0 3 1 H Example 1 27 April 28, 2000 Preliminary HT9580 HT9580 shown in the following figure. The programmer should note that the information on the message buffer must be read out before the next continuous codeword arrives. Otherwise the data on the message will be overwritten. Example 2: if the data read from 0031H 0031H is ²2EH² when a new data ready interrupt occurred, that means the data length of this call is more than 46 and the next data ready interrupt will occur. If the next interrupt occurs and the contents of 0031H 0031H is ²85H², the result are M e s s a g e B u ffe r M e s s a g e B u ffe r 0 0 4 0 H A d d re s s C o d e w o rd 0 0 4 0 H M e s s a g e C o d e w o rd 4 6 0 0 4 1 H M e s s a g e C o d e w o rd 1 0 0 4 1 H M e s s a g e C o d e w o rd 4 7 0 0 4 2 H M e s s a g e C o d e w o rd 2 0 0 4 2 H M e s s a g e C o d e w o rd 4 8 0 0 4 3 H M e s s a g e C o d e w o rd 4 9 0 0 4 4 H M e s s a g e C o d e w o rd 5 0 0 0 4 5 H N /A 0 0 6 D H N /A 0 0 6 C H M e s s a g e C o d e w o rd 4 4 0 0 6 D H M e s s a g e C o d e w o rd 4 5 B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 0 0 1 0 1 1 1 0 1 0 0 3 1 H 1 s t D a ta R e a d y In te rru p t 0 0 0 0 1 0 1 0 0 3 1 H 2 n d D a ta R e a d y In te rru p t Example 2 The data ready interrupt will generate when message is terminated, synchronization code P O C S A G D A T A S tru c tu re F ra m e 5 F ra m e 6 word is received or buffer is full. The following figure will show the typical operation. F ra m e 7 S y n c F ra m e 0 F ra m e 1 F ra m e 2 D I N M I D R _ F G M e s s a g e B u ffe r (4 6 b y te s ) V a lid D a ta The timing chart of message buffer 28 April 28, 2000 Preliminary HT9580 HT9580 SPI configure register Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 State on POR 0032H 0032H SPI-CONFIG S/M LEN1 LEN0 REQST SPIFG CLK_EDG SPI_EN START 0111 1000 · S/M: Slave/master mode selection · CLK_EDG: Data sampling edge When S/M is "0", HT9580 HT9580 is in the master mode. Otherwise, HT9580 HT9580 is in the slave mode. 0 S/M 0 1 Master mode (SCK is output) The CLK_EDG will determine the valid MISO and MOSI sampling edge of SCK clock. Slave mode (SCK is input) CLK_EDG 1 Rising edge Falling edge · SPI_EN: The SPI enable 0 · LEN0, LEN1: Data length When the SPI circuit is disabled, the SPI_EN POCSAG decoder I/O pins will be enabled The LEN0 and LEN1 will determine the data length between exchange. LEN1 LEN0 Data Length (Bit) 0 0 4 0 1 8 1 0 16 1 1 32 1 The SPI circuit and SPI I/O pins will be enabled · START: The data exchange start or not 0 START · REQST: SPI request (read only) When FLEXTM decoder wants to exchange data with HT9580 HT9580, the REQST will have low pulse. 1 No data exchange Data exchange start When the bit is set by software, the SPI data exchange will start. After the first bit data exchange is completed, the START bit will clear to low again by hardware. · SPIFG: SPI complete flag 0 (clear): Data transfer to external device has been completed. 1 (set): No valid completion of data transfer. The bit is cleared by hardware and set by software. 29 April 28, 2000 Preliminary HT9580 HT9580 SPI SPEED register (write only) Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 State on POR 0033H 0033H SPI-SPEED SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0000 0000 The register will determine the SCK clock frequency of SPI. When SPEED register are 00H, the SCK clock output is high. The value of the frequency divider, ranging from 1 (SPEED=01H)~255 (SPEED=FFH). If SPEED=00H, the SCK output will be disabled. X 1 - c lo c k 8 - b it S P E E D C o u n te r S C K S P I C o n tro l S P I SPI output buffer register (write only) Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 State on POR 0034H 0034H SPI-OUT3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0035H 0035H SPI-OUT2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0036H 0036H SPI-OUT1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0037H 0037H SPI-OUT0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 The SPI-OUT3~0 are used when transmitting data on the serial bus. Only valid data write to the register SPI-OUT3~0 and "START" initiating will begin the SPI data transmission from HT9580 HT9580 to FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and the internal signal ²REQST² will generate a falling edge signal for NMI. The bit7 of SPI-OUT3 is MSB and bit0 of SPI-OUT0 is LSB. S P IF G R E Q S T (N M I) R E Q S T ( r e g is te r ) L o g ic H ig h S T A R T ( r e g is te r ) S C K (fro m M O S I H T 9 5 8 0 ) S P I-O U T 3 ~ 0 (fro m M IS O d e c o d e r) S P I-IN 3 ~ 0 2 M S B M S B 1 2 1 L S B L S B S S (to d e c o d e r) (fro m S R D Y d e c o d e r) S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0 30 April 28, 2000 Preliminary HT9580 HT9580 SPI input buffer register (read only) Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 State on POR 0038H 0038H SPI-IN3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 0039H 0039H SPI-IN2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 003AH 003AH SPI-IN1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 003BH 003BH SPI-IN0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000 The SPI-IN3~0 are used when receiving data on the serial bus. When SPI transmits only valid data writes to the register SPI-OUT3~0, "START" will initiate the SPI data transmission from HT9580 HT9580 to FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and the internal signal "REQST" will generate a falling edge signal for NMI. The bit7 of SPI-IN3 is MSB and bit0 of SPI-IN0 is LSB. S P IF G R E Q S T (N M I) R E Q S T ( r e g is te r ) S T A R T ( r e g is te r ) S C K (fro m M IS O d e c o d e r) S P I-IN 3 ~ 0 (fro m M O S I H T 9 5 8 0 ) S P I-O U T 3 ~ 0 M S B 2 M S B 1 2 L S B 1 L S B S S (to d e c o d e r) (fro m S R D Y d e c o d e r) S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0 31 April 28, 2000 Preliminary The POCSAG paging code cordance with the following rules (see the following Figure). A transmission using the ²CCIR Radio paging Code No.1² (POCSAG code) is generated in acB A T C H 1 P R E A M B L E HT9580 HT9580 B A T C H 2 L A S T B A T C H 1 0 1 0 .1 0 1 0 1 0 1 0 1 0 S y n c h C W C W B it N u m b e r C W F R A M E 1 2 0 /2 1 1 8 A d d r e s s B its 0 2 F u n c tio n B its 2 0 2 2 to 3 1 3 2 1 0 1 Id le c o d e w o r d 0 3 1 Id le c o d e S y n c h c o d e w o rd 0 3 1 S y n c h c o d e C R C b its 1 0 M e s s a g e B its M e s s a g e c o d e w o rd C W F R A M E 7 2 to 1 9 1 A d d re s s c o d e w o rd C W C W F R A M E 0 C R C b its P P B it p a tte r n B it p a tte r n POCSAG code structure Address code-words are identified by an MSB of logic 0 and are coded as shown in the POCSAG code structure figure. A user address or RIC (Receiver Identity Code) consists of 21 bits. Only the upper 18 bits are encoded in the address code-word (bits 2 to 19). The lower 3 bits designate the frame number in which the address is transmitted. The transmission is started by sending a preamble, consisting of at least 576 continuously alternating bits (10101010.). The preamble is followed by an arbitrary number of batch blocks. Only complete batches are transmitted. Each batch comprises 17 code-words of 32 bits each. The first code-word is a synchronization code-word with fixed pattern. The sync word is followed by 8 frames (0~7) of 2 code-words each, containing message information. A code-word in a frame can either be an address, message or idle code-word. Four different call types can be distinguished on each user address. The call type is determined by two functional bits in the address code-word (bits 20 and 21). The POCSAG standard recommends the use (in Taiwan) of combinations of data formats and function bits, as shown in the following table. Other combinations will be set by SPF16 SPF16~SPF19 SPF19. Idle code-words also have fixed patterns and are used to fill empty frames or separate messages. Bit 20 (MSB) Bit 21 (LSB) Call Type Data Format 0 0 Numeric 4-bit package 0 1 Alert only ¾ 1 0 Alert only ¾ 1 1 Alpha-numeric 7-bit package Data formats and function bits 32 April 28, 2000 Preliminary · On status Alert-only calls consist of a single address code-word. Numeric and alphanumeric calls have message code-words following the address. In the ON status, the decoder pulses the receiver, quick charge and PLL enable outputs (respectively BS1, BS2 and BS3) according to the code structure and the synchronization algorithm. Data received serially at the data input (DI) is processed for call receipt. Message code-words are identified by an MSB of logic 1. The message information is stored in a 20-bit field (bits 2 to 21). The data format is determined by the call type: 4 bits per digit for numeric message and 7 bits per (ASCII) charact e r f o r a l p ha num er i c m es s a g es . E a c h code-word is protected against transmission errors by 10 CRC check bits (bit 22 to 31) and an even parity bit (bit 32). · STB status In the STB status the decoder will neither activate the receiver, quick charge or PLL enable outputs, nor process any data at the data input. The crystal oscillator remains active to permit communication with the microcontroller. This permits correction of a maximum of 2 random errors or up to 4 errors in a burst of 4 bits (a 4-bit burst error) per code-word. · Battery saving · Error correction Item Current consumption is reduced by switching the STB internal decoder sections whenever the receiver is not enabled. To further increase battery efficiency, reception and decoding of an address code-word is stopped as soon as the uncorrected address field differs by more than 3-bits from the enabled RICs. If the next code-word has to be received again, the receiver is re-enabled, thus observing the programmed establishment times tBS1 , tBS2 and tBS3. Description Address code-word two random errors, or 4-bit burst errors (optional) Message code-word two random errors, or 4-bit burst errors (optional) Error correction In the HT9580 HT9580, error correction methods have been implemented as shown in the table above. Random error correction is the default for both address and message code-word. In another method, burst error correction can be switched by SPF programming. Up to 4 erroneous bits in a 4-bit burst can be corrected. The error type detected for each code-word is identified in the message data output to the microcontroller, allowing rejection of calls with too many errors. · Data reception and buffer Reception of a valid paging call is signaled to the microcontroller by means of an interrupt signal. The received address and message code-word can then be read via a 46 bytes message buffer (from 0040H 0040H to 006DH 006DH) for decoder data message. If the mC did not read the previous message within one code-word time from the message buffer, the message buffer data will be overwritten. · Operating states · Bit rates ON status ¨ STANDBY status The operating state is determined by control address (0019H 0019H) bit 0 and monitored by bit 3 of address (0019H 0019H). The HT9580 HT9580 can be configured for data rates of 512, 1200 or 2400 bit/s by SPF programming. These data rates are derived from 32.768kHz, 76.8kHz or 153.6kHz oscillator frequencies. ¨ · Input data processing Truth table for decoder operating status ON Input The input data is noise filtered by means of a digital filter. Data is sampled at 16 times the data rate and averaged by majority decision. Operating Status 0 On state 1 HT9580 HT9580 STANDBY state 33 April 28, 2000 Preliminary HT9580 HT9580 · Message receiving mode The filtered data is used to synchronize an internal clock generator by monitoring transitions. The recovered clock phase can be adjusted in steps of 1/8, 3/32, 1/16, or 1/32 bit period per received bit. The receiving message mode (numeric or alpha-numeric) depends on bits SPF16 SPF16~SPF19 SPF19. If one of these bits from SPF16 SPF16~SPF19 SPF19 is cleared to low, the decoder will be in numeric package receiving mode. Otherwise, the decoder is in the alphanumeric receiving mode. An example is shown below: All step size are used when bit synchronization has not been achieved, the smallest when a valid data sequence has been detected. · Erroneous code-words Function Bits Upon receipt of erroneous uncorrectable code-words, call termination occurs according to the conditions given below: SPF08 SPF08 SPF09 SPF09 0 0 1 Numeric (4-bit) 0 1 Numeric (4-bit) 1 0 Alphanumeric (7-bit) SPF19 SPF19=1 1 1 Alphanumeric (7-bit) The decoder data output format is determined by the value SPF16 SPF16~SPF19 SPF19. When it is logic low, the 4-bit (numeric) package will be selected. Otherwise, the 7-bit (alphanumeric) package is selected. The following tables illustrate the above two different conditions. Any single code-word in error 1 0 SPF18 SPF18=1 1 0 SPF17 SPF17=0 Any two consecutive code-words or the code-word directly following the address code-word in error Bit 21 (LSB) SPF16 SPF16=0 Description X Message Receiving Format Bit 20 (MSB) Any two consecutive code-words in error Message code-word on the message buffer (numeric receiving mode) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Error Flag 0 0 0 D3 D2 D1 D0 Message code-word on the message buffer (alphanumeric receiving mode) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Error Flag D6 D5 D4 D3 D2 D1 D0 · Synch word indication the standard POCSAG synchronization code-word as shown in the following table. The synch word recognized by the HT9580 HT9580 is Bit No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 0 Bit No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 34 April 28, 2000 Preliminary · Idle word indication HT9580 HT9580 standard POCSAG idle code-word as shown in the following table. The idle word recognized by the HT9580 HT9580 is a Bit No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0 1 Bit No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 · Error indication One is the pager control address (0019H 0019H), which controls the operation and configuration of the decoder. The other is the pager message buffer address (from 0040H 0040H to 006DH 006DH), which receives the message data of calls in the parallel mode. The data ready (DR_FG) and battery fail (BF_FG) interrupt flags are in the interrupt flag register (0006H 0006H). After error correction, any code-word containing more than 2-bit random errors or 4-bit burst errors (option) in the address or message code-word may be indicated from the error flag position. · Decoder and mC interface The HT9580 HT9580 has two mC interface available. B it 5 B it 4 D R _ F G (0 0 0 6 H ) B F _ F G (0 0 0 6 H ) 0 0 1 9 H B it 7 B it 6 B it 5 B L B it 4 O R B it 3 B it 2 B it 0 R E S S T B B it 1 O N B it 0 B it 1 B it 2 B it 3 B it 4 P O C S A G D I B A B S B S B S D e c o d e r D e c o d e r D a ta O u tp u t R F C K T . D a ta R e a d y In te rru p t S P I R E Q S T V m C (N M I) 1 m C P A 7 (W a k e u p ) 2 1 3 R S S I B it 5 B it 6 B it 7 M e s s a g e B u ffe r (4 6 B y te s ) L P a g e r S y s te m C L K D e b o u n c e C ir c u it V IL IH = 0 .9 V = 1 .0 V B A F ( B a tte r y F a il In te r r u p t) Note: The value of 0019H-bit3 STB is set when decoder enters the standby mode and cleared when decoder enters the ON mode. The value of 0006H-bit4 BF_FG is dependent on the BAF pin ststus. The value of 0019H-bit5 OR is always changed by an out of range signal. The value of 0019H-bit6 BL is cleared 0" by the decoder Battery low signal and set 1" when the mC sets this bit high. The value of 0006H-bit5 DR_FG is set 1" by the decoder Data-Ready interrupt signal and cleared ²0² when the mC clears DR_FG. 35 April 28, 2000 Preliminary HT9580 HT9580 On the other hand, if the status of the battery fail flag (BF_FG) changes from ²1² to ²0², the internal node PA.7 of the pager controller will supply a wake-up function. After the decoder asserts the data ready request, the data ready interrupt is generated and the DR_FG bit (bit 5 of 0006H 0006H) is set high; then the data ready interrupt subroutine runs to process the call data on the message buffer and resets the DR_FG bit low. The decoder control address (0019H 0019H) contains a battery low flag (BL), an out of range flag (OR), decoder standby flag (STB), a decoder software reset (RES), and a decoder on/off control bit (ON). The data ready and battery fail flag are in the interrupt flag register (0006H 0006H). It not only records the status information but controls the operation of the decoder. If the flag status of the battery fail (BF_FG) changes from ²0² to ²1², the following conditions occur. The functional bits (ON, RES) and indication bits ( STB, OR, BL, BF_FG and DR_FG) are all used to control the status of the decoder which is operated through the pager control address as described in the following table. The pager controller generates an interrupt if the value of the data ready interrupt is ²0². ¨ The pager controller does not generate any interrupt and no data is transmitted to it if the value of the data ready interrupt is ²1². ¨ INT flag register (0006H 0006H) Symbol BF_FG DR_FG Bit R/W Description 4 R Battery fail indication bit Once the decoder detects that the battery fail condition occurred, the BF_FG will go high. R/W Data ready interrupt indication bit When a valid call is detected, data transfers to the message buffer. The DR_FG bit goes high when the message is terminated within 46 bytes, one batch is at the end during the message receiving or the data buffer is full if the data length is more than 46 bytes. The mC software should read the data on the message buffer within one POCSAG message codeword (32-bit) time. The mC software has to clear the DR_FG bit low. 5 Decoder control register (0019H 0019H) Symbol ON RES Bit 0 1 R/W Description R/W On/Off control bit This bit selects the ON or STANDBY state of the decoder 0: ON state 1: STANDBY RES If SPI circuit is enabled, it would be better if this bit is set high to reduce power consumption. R/W Resets the decoder core output The mC has to set the RES bit low and then high after the pager controller is turned on. The reset status must be released before writing data to the decoder configuration RAM. 36 April 28, 2000 Preliminary Symbol STB OR BL Bit 3 5 6 HT9580 HT9580 R/W Description R Standby indication bit When the value of the ON bit is 1, the system goes into the STANDBY state. The STANDBY state allows the mC to execute the configuration RAM setting. R Out-of-range indication bit Whenever the decoder detects an out-of-range hold time, that is selected by the configuration registers SPF06 SPF06 and SPF07 SPF07. The out-of-range indication may be tested for an out-of-range condition whenever the interface enable of the decoder is active; otherwise OR is normally low. The out-of-range indication is set high by detection of valid data transmission. If the out-of-range indication bit changes the status from high to low or low to high, an interrupt will be generated and the out-of-range hold-off time-out counter starts to count. The bit is not valid when the SPI circuit is enabled. R/W Battery low indication bit The battery low indication is periodically tested for a battery low condition. If the decoder encounters a battery low condition, the battery low indication bit is cleared low. The mC can only set the BL bit high. Attempting to clear this bit has no effect. The bit is not valid when the SPI circuit is enabled. Register allocation · User address format A user address in the POCSAG code consists of 21 bits. Three of the 21 bits are coded in the frame number and are therefore not explicitly transmitted. In the decoder, the addresses A, B, C, D, E and F can use six different frames respectively. Every address has to be explicitly enabled by resetting the associated enable bit. Example: Address decimal value: RICA=10535 Binary equivalent (14-bit): 10100100100111 Binary equivalent (18+3-bit): 000000010100100100111 A00 A02 A03 A04 A05 A06 0 0 0 0 0 0 0 A07 A08 A09 A10 A11 A12 A13 1 0 1 0 0 1 0 A14 A15 A16 A17 0 37 A01 1 0 0 FA2 FA1 FA0 1 1 1 April 28, 2000 Preliminary · Test mode HT9580 HT9580 the received data (including address codeword and message codeword) length is terminated within 46 bytes, one batch is over or if the 46 bytes data buffer is full if data length is more than 46 bytes. If the data in the message buffer is terminated, the ²MSG_END² (0031H 0031H) bit will set high. The test mode of the decoder is selected by setting the TS pin low at any time. In the test mode, the RF control outputs BS1 and BS3 are constantly set high, but BS2 is set low. After the TS pin is set high the decoder exits the test mode. The address word indicates call address, functional bit setting, and decoder flags. The message code-words are received and concatenated to a valid call address word. The message words are derived from un-corrected message code-words. · Message data transfer The decoder outputs a deformatted address word and message words upon receipt of a valid call. The message data to be transferred is organized into 8-bit words and transferred to the message buffer address (0040H 0040H to 006DH 006DH). The data ready interrupt flag will be set high when · Address word format Bit7 Bit6 Sync. State Bit5 Bit4 Bit2 Dup. Call Call Address Bit3 Valid Address Bit1 Bit0 Function Code Note: Bit0: Bit21 of the address code-word Bit1: bit20 of the address code-word Bit2: If this bit is ²1², the address word is valid, oterwise the address word is not valid. Bit3: 1 for a duplicate code-word Bit7: 1 if an address code-word is received in the data fail mode Bit6 Bit5 Bit4 0 0 0 RIC A 0 0 1 RIC B 0 1 0 RIC C 0 1 1 RIC D 1 0 0 RIC E 1 0 1 RIC F 1 1 0 ¾ 1 1 1 · Interrupt indication Call Address ¾ The HT9580 HT9580 provides an internal data ready interrupt and a battery fail interrupt. The internal data ready interrupt and battery fail interrupt share the NMI location. Which interrupt occurred can be determined by checking the battery fail interrupt bit (BF_FG; bit 4 of 0006H 0006H) and the data ready interrupt bit (DR_FG; bit 5 of 0006H 0006H). Both interrupt bits are active high. 38 April 28, 2000 Preliminary · Out-of-range indication HT9580 HT9580 Receiver Establishment Time TBS1 The out-of-range condition occurs when the time interval defined by SPF06 SPF06, SPF07 SPF07 is unable to receive sync code words. If sync code words are detected, the timer counter defined by SPF06 SPF06, SPF07 SPF07 will reset. This signal will be seen as a loss of RF signal indication and the power on reset is in an out-of-range condition until the sync code word is detected. Option 512 bps 7.81ms 53.33ms 0 0 15.63ms 6.67ms 0 1 31.25ms 13.33ms 1 0 62.50ms · Duplicate call suppression 1200/2400 bps 26.67ms 1 1 Quick Charge Adjustment Time TBS2 The HT9580 HT9580 provides a duplicate call suppression with time-out facility, to identify duplicate call reception. In the display pager mode, duplicate call indication is achieved only via the mC interface. A call is assumed to be a duplicate if its latest address and function bit setting is equal to the previous received call within the time interval defined by SPF06 SPF06, SPF07 SPF07. SPF00 SPF00 SPF01 SPF01 Option 512 bps 7.81ms 1.67ms 0 0 15.63ms 6.67ms 0 1 15.63ms 11.67ms 1 0 19.53ms · Receiver, Quick charge and PLL signal control 1200/2400 bps 13.33ms 1 1 PLL Establishment Time TBS3 Pager receiver, quick charge circuit, and RF PLL circuit can be controlled independently via enable outputs BS1, BS2, and BS3 respectively. Their operating period are optimized according to the synchronization mode of the decoder. Each enable signal has its own programmable establishment time. SPF02 SPF02 SPF03 SPF03 Option 512 bps 1200/2400 bps SPF04 SPF04 SPF05 SPF05 0ms 0ms 0 0 31.25ms 26.67ms 0 1 46.87ms 40.00ms 1 0 62.50ms 53.33ms 1 1 R.F. timing chart D a ta B its D a ta In T B S 1 B S 1 T B S 2 B S 2 T B S 3 B S 3 39 April 28, 2000 Preliminary memory is mapped 001AH 001AH~002EH 002EH. Decoder configuration RAM The decoder contains a 21-byte RAM to store six user addresses, six frame numbers, and specially programmed function bits (SPF00 SPF00~SPF19 SPF19) for the decoder application configuration. The data Address HT9580 HT9580 to the address The configuration memory mapping table is shown below. Bit Definition Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 001AH 001AH ENA A00 A01 A02 A03 A04 A05 A06 001BH 001BH A07 A08 A09 A10 A11 A12 A13 A14 001CH 001CH A15 A16 A17 FA2 FA1 FA0 X X 001DH 001DH ENB B00 B01 B02 B03 B04 B05 B06 001EH 001EH B07 B08 B09 B10 B11 B12 B13 B14 001FH 001FH B15 B16 B17 FB2 FB1 FB0 X X 0020H 0020H ENC C00 C01 C02 C03 C04 C05 C06 0021H 0021H C07 C08 C09 C10 C11 C12 C13 C14 0022H 0022H C15 C16 C17 FC2 FC1 FC0 X X 0023H 0023H END D00 D01 D02 D03 D04 D05 D06 0024H 0024H D07 D08 D09 D10 D11 D12 D13 D14 0025H 0025H D15 D16 D17 FD2 FD1 FD0 X X 0026H 0026H ENE E00 E01 E02 E03 E04 E05 E06 0027H 0027H E07 E08 E09 E10 E11 E12 E13 E14 0028H 0028H E15 E16 E17 FE2 FE1 FE0 X X 0029H 0029H ENF F00 F01 F02 F03 F04 F05 F06 002AH 002AH F07 F08 F09 F10 F11 F12 F13 F14 002BH 002BH F15 F16 F17 FF2 FF1 FF0 X X 002CH 002CH SPF00 SPF00 SPF01 SPF01 SPF02 SPF02 SPF03 SPF03 SPF04 SPF04 SPF05 SPF05 SPF06 SPF06 SPF07 SPF07 002DH 002DH SPF08 SPF08 SPF09 SPF09 SPF10 SPF10 SPF11 SPF11 SPF12 SPF12 SPF13 SPF13 SPF14 SPF14 SPF15 SPF15 002EH 002EH SPF16 SPF16 SPF17 SPF17 SPF18 SPF18 SPF19 SPF19 X X X X 40 April 28, 2000 Preliminary HT9580 HT9580 · SPF10 SPF10 Description of the special programmed function bits (SPFn) 1: 4-bit burst error correction for address and message code-word The following features can be selected by appropriate programming of the specially programmed function bits: 0: 2-bit random error correction for address and message code-word · SPF00 SPF00~SPF01 SPF01 · SPF11 SPF11 Receiver (BS1) establishment time (for the BS2~BS3 options, refer to SPF02 SPF02~SPF05 SPF05) 1: Out-of-range Hold-off period according to SPF06 SPF06 and SPF07 SPF07 00: 7.81ms/512 53.33ms/1200/2400 0: Out-of-range Hold-off period is 0 regardless of SPF06 SPF06 and SPF07 SPF07 01: 15.63ms/512 6.67ms/1200/2400 10: 31.25ms/512 13.33ms/1200/2400 Baud rate selection bits(SPF12 SPF12,SPF13 SPF13,SPF14 SPF14) 11: 62.50ms/512 26.67ms/1200/2400 Note: The recommendatory setting is 11. SPF12 SPF12 · SPF02 SPF02~SPF03 SPF03 SPF13 SPF13 SPF14 SPF14 Connected Crystal (Hz) Baud Rate (bps) 512 0 0 0 32768 RF dc level adjustment (BS2) enable time 0 0 1 76.8k 512 00: 7.81ms/512 1.67ms/1200/2400 0 1 0 76.8k 1200 0 1 1 76.8k 2400 1 0 0 153.6k 512 10: 15.63ms/512 11.67ms/1200/2400 1 0 1 153.6k 1200 11: 19.53ms/512 13.33ms/1200/2400 1 1 0 153.6k 2400 01: 11.71ms/512 6.67ms/1200/2400 Note: The (SPF12 SPF12, SPF13 SPF13, SPF14 SPF14) = (0, 1, 0) when power on reset · SPF15 SPF15 Non-inverting or inverting data input selection · SPF04 SPF04~SPF05 SPF05 PLL (BS3) establishment time 00: 0ms/512 0ms/1200/2400 01: 31.25ms/512 26.67ms/1200/2400 1: Inverting input selected for DI from RF circuit, referring to DI 10: 46.87ms/512 40.00ms/1200/2400 11: 62.50ms/512 53.33ms/1200/2400 0: Non-inverting input selected for DI from RF circuit reserved, should be 0 · SPF06 SPF06~SPF07 SPF07 · SPF16 SPF16~SPF19 SPF19 The duplicate call suppress time-out and out-of-range hold-off time-out Message receiving mode selection depending on the function code (bit20, bit21) 00: 30s/512/1200 15s/2400 01: 60s/512/1200 30s/2400 0 10: 120s/512/1200 60s/2400 1 SPF16 SPF16 Function Code (0, 0) is Function Code (0, 0) is an a numeric message alpha-numeric message 11: 240s/512/1200 120s/2400 SPF17 SPF17 Function Code (0, 1) is Function Code (0, 1) is an a numeric message alpha-numeric message · SPF08 SPF08~SPF09 SPF09 0x: Any two consecutive code-words or the code-word directly following the address code-word in error SPF18 SPF18 Function Code (1, 0) is Function Code (1, 0) is an a numeric message alpha-numeric message SPF19 SPF19 Function Code (1, 1) is Function Code (1, 1) is a numeric message analpha-numeric message 10: Any single code-word in error 11: Any two consecutive code-words in error 41 April 28, 2000 Preliminary HT9580 HT9580 CPU Core bus memory. In the low state the data bus has valid data from the mC to be stored at the addressed memory location. The HT9580 HT9580 is a high performance pager controller specifically designed for use in new generation radio pagers. It is based on the M6502 M6502 core. The 6502 Microprocessor offers complete hardware and software capability with existing 6500 series of products as well as significant enhancements. Parameter Description tcyc Clock cycle time (min) tad Address delay time Instruction register and decoder tah Address hold time Instructions fetched from memory are gated onto the internal bus. These instructions are latched into the instruction register then decoded, along with timing and interrupt signals, to generate control signals for the various registers. tdis Read data in setup time tdih Read data in hold time tdod Write data out delay time tdoh Write data out hold time tdenbd DATAEN delay time twed WE_N delay time tsyd SYNC delay time tsyh SYNC hold time tvd VPB delay time tvh VPB hold time tsos SOB_N setup time tsoh SOB_N hold time trds RDY setup time trdh RDY hold time tress RES_N setup time tresh RES_N hold time Timing control unit The timing control unit keeps track of the instruction cycle being monitored. The unit is set to 0 each time an instruction fetch is executed and is advanced at the beginning of each input clock pulse for as many cycles as required to complete the instruction. Each data transfer between registers depends upon decoding the contents of both the Instruction Register and the Timing Control Unit. There are three major clocks in the mC as follows: · Phase 2 In (PHI2 (IN) This signal is from the OSC1 input pin of HT9580 HT9580. The PHI1 (OUT) and PHI2 (OUT) are derived from this signal. · Phase 2 Out (PHI2 (OUT) This signal is generated from PHI2 (IN). PHI2 (IN) provides the system timing. There is a slight delay from PHI2 (IN). Timing parameter annotations Arithmetic and logic unit · Phase 1 Out (PHI1 (OUT) All arithmetic and logic operations take place within the ALU including incrementing and decrementing internal registers (except for the program counter). The ALU has no internal memory and is used only to perform logical and transient numerical operations. Inverted PHI2 (OUT) signal. There is a slight delay from PHIN2 (IN). Read/write This signal is normally in a high state indicating that the mC is reading data from the data 42 April 28, 2000 Preliminary tc HT9580 HT9580 y c C L K ta d A D D R ta R D h A d d re s s td W R A d d re s s is R E A D D A T A I td ih td o d W R IT E D A T A O td td e n b d o h D A T A E N tw W E _ N ts ts y h , tv y d , tv e d d h S Y N C , V P B R D Y , R E S _ N S O B _ N trd h , tre trd s , tre s s , ts s h , ts o h o s M6502 M6502 read and write cycle Accumulator Processor status register The Accumulator is a general purpose 8-bit register which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of the two data words used in these operations. The 8-bit processor status register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both by the program and the mC. The HT9580 HT9580 instruction set contains a number of conditional branch instructions which are designed to allow testing of these flags. Index register There are two 8-bit Index Register (X and Y) which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction which specifies indexed addressing, the mC fetches the opcode and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-indexing of indirect addresses is possible. Program counter The 16-bit program counter register provides the addresses which step the mC through sequential program instructions. Each time the HT9580 HT9580 fetches an instruction from the program memory, the lower byte of the program counter (PCL) is placed on the low-order bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order 43 April 28, 2000 Preliminary Status register 8 bits. The counter is incremented each time an instruction or data is fetched from the program memory. N V I: IRQ 1=true 1=negative 0 A c c u m u la to r A 0 In d e x R e g is te r Y 0 X 8 In d e x R e g is te r X 7 0 P C H P C L 7 0 0 1 1=BRK, 0=IRQ N: Negative Y 0 C 1=true V: Overflow 7 0 Z E: Expansion bit (reserved) 7 0 I 1=disable B: BRK command A 0 D 1=true D: Decimal mode 7 0 B 1=true Z: Zero The stack pointer is an 8-bit register which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the microprocessor to perform stack manipulations under direction of either the program or interrupt (NMI and IRQ). The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user¢s software. 1 5 E Note: C: Carry Stack pointer 1 5 HT9580 HT9580 P ro g ra m C o u n te r P C 0 S S ta c k P o in te r T h e w id th o f th e c o r r e s p o n d in g r e g is te r s 44 April 28, 2000 Preliminary HT9580 HT9580 Interrupt System the interrupt vector from locations FFFA (low byte) and FFFB (high byte), thereby transferring program control to the non-maskable interrupt routine. The NMI is generated from data ready interrupt or battery fail interrupt flag (0006H 0006H). However, it should be noted that this is an edge-sensitive input. As a result, another interrupt will occur if there is another negative-going transition and the program has not returned. Also, no interrupt will occur if NMI is low and a negative-going edge has not occurred since the last non-maskable interrupt. The NMI signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first byte is the high byte in the program counter. The second byte is the program counter low byte. The third byte is the status register value. These values are used to return to its original state prior to NMI interrupt. The HT9580 HT9580 is capable of directly addressing 64 Kbytes of memory. The address space has special significance within certain addressing modes, as follows: Reset and interrupt vectors The reset and interrupt vectors use the majority of the fixed addresses between FFFA and FFFF. Stack The stack may use memory from 01D0 to 01FF. The effective address of stack and stack relative addressing modes will always be within this range. Interrupt request - IRQ This CMOS compatible signal requests that an interrupt sequence begin within the mC. The IRQ is sampled during PHI2 operation; if the interrupt flag in the processor status register is 0, the current instruction is completed and the interrupt sequence begins during PHI1. The program counter and processor status register are stored in the stack. The mC will then set the interrupt mask flag high so that no further interrupts may occur. At the end of this cycle, the PCL will be loaded from address FFFE, and PCH from location FFFF, transferring program control to the memory vector located at these addresses. The IRQ signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first byte is the high byte in the program counter. The second byte is the program counter low byte. The third byte is the status register value. These values are used to return the processor to its original state prior to the IRQ interrupt. Data address space The mC internal address bus consists of A0~A15 forming a 16-bit address bus for memory and I/O exchanges on the data bus. The output of each address line is CMOS compatible. The Address output pins of HT9580 HT9580 (A0~A15) derive from mC internal address pins A0~A15. The extended address pins (RA14~RA18) are the combination of bank point registers (0015H 0015H, 0016H 0016H) and internal address. The extended address pins are used to access internal/external SRAM or Mask ROM (Character ROM). The data lines constitute 8-bit bidirectional data bus for use during exchanges between the mC and peripherals. The outputs are three-state buffers capable of driving CMOS load. The Program Address and Data Address space is continuous throughout the 64 Kbyte address space. Words, arrays, records, or any data structures may span the 64 Kbytes address space. The following addressing mode descriptions provide additional detail as to how effective addresses are calculated. Fifteen addressing modes are available for the HT9580 HT9580 as illustrated on the next page. Non-maskable interrupt - NMI A negative-going edge on this input requests that a non-maskable interrupt sequence be generated within the mC. The NMI is sampled during PHI2; the current instruction is completed and the interrupt sequence begins during PHI1. The Program Counter is loaded with 45 April 28, 2000 Preliminary HT9580 HT9580 · A number in parenthesis indicates that the Addressing modes The M6502 M6502 supports fifteen (15) addressing modes, shown in table below. In interpreting this table you should note that: contents of the location pointed to by the number are to be used. For example (12H) indicates the contents of address 12H. · The byte following a 2 byte opcode = IAL (typ.) · The 2 bytes following a 3 byte opcode = BAL · A comma