HT82M75REW/HT82K75REW HT82M75REW HT82K75REW 40QFN 64LQFP HT82K75R 0000H HA0075E - Datasheet Archive

 

2.4GHz Transceiver 8-Bit OTP MCU Features · Operating voltage: · Up to 40 bidirectional I/O lines with pull-high

 

HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW 2.4GHz Transceiver 8-Bit OTP MCU Features · Operating voltage: · Up to 40 bidirectional I/O lines with pull-high options fSYS= 6MHz: 1.8V~3.3V · All I/O pins have falling and rising edge wake-up · Internal 6MHz RC oscillator for fSYS function · Power down and wake-up functions to reduce · Single 16-bit internal timer with overflow interrupt power consumption and timer input · Two bit to define microcontroller system clock · Low voltage reset function (LVR) for DC_DC output (fSYS/1, fSYS/2, fSYS/4) controlled by configuration option · All instructions executed in one or two machine · Built-in DC/DC to provide stable 2.8V, 3.0V, 3.3V with error ±5% selected by configuration options cycles · Table read instructions · Low voltage detector (LVD) with levels 1.78V/2.0V/2.2V/2.5V/2.8V ±5% for battery input (BAT_IN) selected by application program · 63 powerful instructions · 6-level subroutine nesting · Bit manipulation instruction · Wide range of available package types · Program Memory: 4K´15 · EEPROM Memory with 128´8 capacity · Data Memory: 128´8~160´8 · RF Transceiver with 2.4GHz RF frequency · Watchdog Timer function General Description The device is an 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O, mouse/keyboard appliances and SPI control product applications. The advantages of low power consumption, I/O flexibility, Timer functions, Watchdog Rev. 1.10 timer, Power Down, wake-up functions together with the optional peripherals such as EEPROM Memory and RF transceiver provide the devices with versatility for industrial control, consumer products, subsystem controllers, RF module control, etc. 1 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Selection Table DC/DC SPI Converter Interface Program Memory Data Memory Data EEPROM I/O Timer HT82M75REW HT82M75REW 4K´15 128´8 128´8 15 16-bit´1 HT82K75REW HT82K75REW 4K´15 160´8 128´8 31 16-bit´1 Note: Built-in OSC Stack Package Ö Ö 6 40QFN 40QFN (6´6´0.85mm) Ö Ö RF Transceiver Ö Ö Part No. Ö Ö 6 64LQFP 64LQFP 1. There are additional peripherals named RF Transceiver with RF frequency of 2.4GHz and Data EEPROM with capacity of 128 bytes in HT82M75REW HT82M75REW and HT82K75REW HT82K75REW devices. All information related to the RF Transceiver and EEPROM Data Memory will be described in the corresponding section respectively. 2. As devices exist in more than one package format, the table reflects the situation for the package with the most pins. Block Diagram O T P P ro g ra m M e m o ry S ta c k W a tc h d o g T im e r O s c illa to r R e s e t C ir c u it R A M D a ta M e m o ry W a tc h d o g T im e r 8 - b it R IS C C o re E E P R O M D a ta M e m o ry I/O P o rts 1 6 - b it T im e r S P I In te rfa c e R F T r a n s m itte r R C In te rn a l O s c illa to r V o lta g e D e te c to r In te rru p t C o n tr o lle r D C /D C Pin Assignment P B 4 P B 5 P B 6 P B 7 L X V S S L X B A T _ IN V D D V S S R E S P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 V D D _ 3 V /V D D _ G R /V D V X T X T V D D V D V D D L O V D D D _ B D D _ A L _ A L _ _ P L D _ C _ V C O P _ _ R F R F _ G O C N P P A P L 1 1 2 3 0 2 9 3 2 8 4 2 7 5 H T 8 2 M 7 5 R E W 4 0 Q F N -A 6 7 8 2 6 2 5 2 4 2 3 9 1 0 2 2 2 1 _ 2 V 2 _ D 0 1 2 G G N G G V D V D D 3 4 5 6 7 H T 8 2 K 7 5 R E W 6 4 L Q F P -A 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 P B 3 P B 2 P B 1 P E 0 P E 1 P E 2 P E 3 P E 4 P E 5 P E 6 P E 7 V S S V D D V D D _ R F 2 N C R F _ N P _ R F I 2 P _ C _ A _ G R /V D D _ B G _ 3 V P B 6 P B 7 P A 0 P A 1 P A 2 /T M R P A 3 R A 4 P A 5 P A 6 P A 7 Rev. 1.10 2 _ V C O _ C P _ P L L _ P L L L _ P L _ N 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 V D D V D D G P IO G P IO G P IO P B 1 P B 2 P B 3 P B 4 P B 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 R F _ N C V D D D B 5 L O O D B 5 V D D V D D V D D G D N X T A X T A D B 4 V D D V D D V D D R F _ N V D D _ R F 2 N C V D D V S S V D D B A T _ IN V S S L X L X R E S 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 P A 6 P A 7 P D 0 P D 1 P D 2 P D 3 P D 4 P D 5 P D 6 P D 7 P IO 2 D _ D P IO 1 P IO 0 D _ D _ 2 V 2 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Pin Description The following table only includes the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the corresponding section of the datasheet along with the relevant peripheral function functional description. Pin Name Options Description I/O Pull-high Wake-up Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PA2 is shared with the external timer input pin TMR. I/O Pull-high or Wake-up CMOS/NMO S Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Also a configuration option determines if the PB0 is a CMOS output type or NMOS output type. PB0 is shared with SCS of the SPI interface. I/O Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. SoftPull-high or ware instructions determine if the pin is a CMOS output or Schmitt Trigger Wake-up input. Configuration options determine if the pins have pull-high resistors. CMOS/NMO Also a configuration option determines if the PC pins are CMOS output type S or NMOS output type. The INT is shared with PC2, PC5~PC7 are shared with the SPI interface. PD0~PD7 (HT82K75R HT82K75R only) I/O Bidirectional 8-bit input/output port. Each nibble can be configured as Pull-high or wake-up inputs (both falling and rising edge) by a configuration option. SoftWake-up ware instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PE0~PE7 (HT82K75R HT82K75R only) I/O Bidirectional 8-bit input/output port. Each nibble can be configured as Pull-high or wake-up inputs (both falling and rising edge) by a configuration option. SoftWake-up ware instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. VSS ¾ ¾ Negative power supply, ground RES I ¾ Schmitt Trigger reset input. Active low VDD ¾ ¾ Positive power supply BAT_IN I ¾ Battery input LX I ¾ DC/DC LX switch VSSLX I ¾ DC/DC ground PA0~PA1 PA2/TMR PA3~PA7 PB0/SCS PB1~PB7 PC0~PC1 PC2/INT PC3~PC4 PC5/SDI PC6/SDO PC7/SCK Rev. 1.10 I/O 3 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Pin Description for EEPROM Memory Pin Name Type Description VDDP ¾ External Positive power supply for EEPROM Memory VSSP ¾ External Negative power supply for EEPROM Memory, ground SDA I/O Internal Serial data input/output signal Internal connected with MCU I/O line. SCL I Serial clock input signal Internal connected with MCU I/O line. NC ¾ Note: Implies that the pin is ²Not Connected² and can therefore not be used. The pin descriptions for all external pins with the exception of the EEPROM VDDP and VSSP pins are described in the preceding MCU section. VDDP and VSSP should be externally connected to the MCU power supply named VDD and VSS respectively. The SDA and SCL lines here are internal connected to the MCU I/O pins PC0 and PC1 respectively for these devices. Pin Description for RF Transceiver Pin Name Type Description RF_P I/O External Differential RF input/output (+) RF_N I/O External Differential RF input/output (-) VDD_RF1 I External RF transceiver power supply (1) VDD_RF2 I External RF transceiver power supply (1) GPIO0 GPIO1 I/O External General Purpose digital I/O It is also used as an external TX/RX switch control GPIO2 I/O External General Purpose digital I/O It is also used as an external Power Amplifier (P.A.) enable control. VDD_D I External RF transceiver digital circuit power supply (+) GND_D I External RF transceiver digital circuit power supply (-) VDD_2V2 O External RF transceiver DC-DC output voltage It cannot be used. VDD_3V I External RF transceiver 3V input for a DC-DC regulator GND_GR ¾ External RF transceiver Guard-Ring ground VDD_A I External RF transceiver power supply for analog circuits (1) XTAL_P I External RF transceiver 32MHz Crystal input (+) XTAL_N I External RF transceiver 32MHz Crystal input (-) VDD_PLL I External RF transceiver PLL power supply (1) VDD_CP I External RF transceiver Charge pump power supply (1) VDD_VCO I External RF transceiver Voltage-controlled oscillator power supply (1) External RF transceiver PLL loop filter external capacitor It is connected to the external 47pF capacitor. LOOP_C I/O VDD_GR I External RF transceiver Guard-Ring power supply (1) VDD_BG O External RF transceiver Bandgap power supply (1) DB4 I External Test pin It is connected to ground. DB5 I External Test pin It is connected to ground. Rev. 1.10 4 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Pin Name Type Description SI I Internal RF Transceiver Slave SPI Serial Data Input Signal Internally connected to the MCU Master SPI SDO output signal SO O Internal RF Transceiver Slave SPI Serial Data Output Signal Internally connected to the MCU Master SPI SDI input signal SCLK I Internal RF Transceiver Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK output signal SEN I Internal RF Transceiver Slave SPI Serial interface Enable Input Signal Internally connected to the MCU Master SPI SCS output signal INT I Internal RF Transceiver Interrupt Output Signal Internally connected to the MCU INT input signal RST I Internal RF Transceiver global hardware reset input signal, active low. Internally connected to the MCU I/O pin configured as output type. NC ¾ Implies that the pin is ²Not Connected² and can therefore not be used. Notes: (1) Connecting bypass capacitor(s) as close to the pin as possible. (2) The pin descriptions for all external pins except the RF Transceiver pins listed in the above table are described in the preceding MCU section. (3) The INT and RST lines are internally connected to the MCU I/O pins PC2 and PC3 respectively for the HT82M75REW HT82M75REW and HT82K75REW HT82K75REW devices. Absolute Maximum Ratings Supply Voltage .VSS-0.3V to VSS+6.0V Storage Temperature .-50°C to 125°C Input Voltage.VSS-0.3V to VDD+0.3V IOL Total .150mA Total Power Dissipation .500mW Operating Temperature.-40°C to 85°C IOH Total.-100mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions ¾ Min. Typ. Max. Unit 1.78 2.20 3.30 V VBAT BAT_IN Operating Voltage ¾ IDD Operating Current (Crystal OSC) 3V No load, fSYS= 6MHz ¾ 3 6 mA ISTB Standby Current ¾ No load, system HALT WDT disable, LVR disable ¾ ¾ 20 mA VIL1 Input Low Voltage for I/O (Schmitt Trigger) ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O (Schmitt Trigger) ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.3VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V IOL1 Other I/O Pins Sink Current 3V VOL=0.1VDD 4 ¾ ¾ mA IOH1 Other I/O Pins Source Current 3V VOH=0.9VDD -2.5 -4.5 ¾ mA RPH1 Other Pins Internal Pull-high Resistance 3V 10 30 50 kW Rev. 1.10 ¾ 5 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW D.C. Characteristics for EEPROM Memory Symbol Parameter Ta=-40°C~85°C Test Conditions VCC Conditions Min. Typ. Max. Unit ICC1* Operating Current 3V Read at 100kHz ¾ ¾ 1 mA ICC2* Operating Current 3V Write at 100kHz ¾ ¾ 3 mA ISTB* Standby Current 3V VIN=0 or VCC ¾ ¾ 3 mA Note: ²*² The operating current ICC1 and ICC2 listed here are the additional currents consumed when the EEPROM Memory operates in Read Operation and Write Operation respectively. If the EEPROM is operating, the ICC1 or ICC2 should be added to calculate the relevant operating current of the device for different conditions. To calculate the standby current for the whole device, the standby current shown above should also be taken into account. A.C. Characteristics Symbol Ta=-40°C~85°C Parameter Remark Standard Mode* Min. Max. Unit fSK SCL Clock Frequency ¾ ¾ 100 kHz tHIGH Clock High Time ¾ 4000 ¾ ns tLOW Clock Low Time ¾ 4700 ¾ ns tr SDA and SCL Rise Time Note ¾ 1000 ns tf SDA and SCL Fall Time Note ¾ 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ ns tSU:DAT Data Input Setup Time ¾ 200 ¾ ns tSU:STO STOP Condition Setup Time ¾ 4000 ¾ ns tAA Output Valid from Clock ¾ ¾ 3500 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 4700 ¾ ns tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾ 100 ns tWR Write Cycle Time ¾ 5 ms Note: ¾ These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 3.6V For relative timing, refer to timing diagrams Rev. 1.10 6 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW A.C. Characteristics for EEPROM Memory Ta=25°C Test Conditions Symbol Parameter Min. VDD Typ. Max. Unit Conditions fSYS System Clock 3V ¾ 5.7 6 6.3 MHz tRCSYS Watchdog OSC Period 3V ¾ ¾ 71 ¾ ms tWDT1 Watchdog Time-out Period with 6-stage Prescaler 3V ¾ 4.57 ¾ ms tRES ¾ ¾ ms WDTS=1 External Reset Low Pulse Width ¾ ¾ 1 tSST System Start-up Timer ¾ ¾ ¾ 512 ¾ 1/fSYS tLVR Low Voltage Width to Reset ¾ ¾ 0.25 1 2 ms tWake-up MCU Wake-up Timer ¾ ¾ ¾ ¾ 1 ms tconfigure Watchdog Time-out Period ¾ ¾ ¾ 1024 ¾ tRCSYS Power-On Reset Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit ¾ ¾ 1.0 ¾ mA VDD Conditions 1.8V~ 3.3V IPOR Operating current RRVDD VDD Rise Rate to Ensure Power-on Reset ¾ Without 0.1mF between VDD and VSS 0.05 ¾ ¾ V/ms VPOR Maximum VDD Start Voltage to Ensure Power-on Reset ¾ Without 0.1mF between VDD and VSS ,Ta=25°C 0.9 ¾ 1.5 V Without 0.1mF between VDD and VSS 2 ¾ ¾ ms With 0.1mF between VDD and VSS 10 ¾ ¾ ms tPOR V Power-on Reset Low Pulse Width ¾ D D tP O R R R V D D V P O R T im e Rev. 1.10 7 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW RF Transceiver D.C. Characteristics Symbol VDD=3V, Ta=25°C Test Conditions Min. Typ. Max. Unit RF Transceiver TX Active. At 0 dBm output power DC-DC Off* ¾ 21 30 mA RF Transceiver RX Active in Normal Mode (250 Kbps) DC-DC Off* ¾ 19 28 mA RF Transceiver RX Active in Turbo Mode (1M bps) ITX DC-DC Off* ¾ 21 30 mA IRX ISTB RF Transceiver in STANDBY mode. Partial 32MHz clock and Sleep clock remains active. RF/MAC/BB, system clock shutdown. ¾ 60 80 mA IDS RF Transceiver in DEEP_SLEEP mode. Power to digital circuit remains active to retain Registers and FIFOs. All the other power is shutdown. ¾ 3.2 10.0 mA IPD RF Transceiver in POWER_DOWN mode. Minimum wake-up circuit remains active. All power is shutdown. Register and FIFO data are not retained. ¾ 0.6 2.0 mA Note: ²*² The operating current ITX or IRX listed here is the additional current consumed when the RF Transceiver operates in Active TX mode or Active RX mode. If the RF Transceiver is active, either ITX or IRX should be added to calculate the relevant operating current of the device for different operating mode. To calculate the standby current for the whole device, the standby current shown above including ISTB, IDS and IPD should be taken into account for different Power Saving Mode. RF Transceiver A.C. Characteristics VDD=3V, Ta=25°C, LO frequency=2.445GHz, DC-DC Off Receiver Parameters Test Conditions Min. Typ. Max. Unit 2.400 ¾ 2.495 GHz dBm RF Input Frequency ¾ At antenna input with O-QPSK 250Kbps signal, PER £ 0.1% 1 Mbps ¾ -90 RF Sensitivity ¾ ¾ -80 ¾ dBm Maximum RF Input ¾ ¾ 5 ¾ dBm Adjacent Channel Rejection @ ±5MHz, 250Kbps (-82dBm + 20 dB = -62dBm) ¾ 20 -62 ¾ dBc dBm Alternative Channel Rejection @ ±10 MHz, 250Kbps (-82dBm + 40 dB = -42dBm) ¾ 40 -42 ¾ dBc dBm LO Leakage Measured at the balun matching the network with the input frequency at 2.4~2.5GHz ¾ -60 ¾ dBm Noise figure (Including matching) ¾ ¾ 8 ¾ dB Rev. 1.10 8 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Transmitter VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off Parameters Test Conditions Min. Typ. Max. Unit 2.400 ¾ 2.495 GHz RF carrier frequency ¾ Maximum RF output power At 0 dBm output power setting -3 0 ¾ dBm RF output power Accuracy ¾ ¾ ¾ ±4 dBm RF output power control range ¾ ¾ 36 ¾ dB TX gain control resolution ¾ 0.1 ¾ 0.5 dB Carrier suppression ¾ ¾ -30 ¾ dBc ¾ ¾ -30 dBm ¾ ¾ -20 dBc ¾ 30 ¾ % TX spectrum mask for O-QPSK signal Offset frequency > 3.5 MHz At 0 dBm output power ¾ TX EVM Synthesizer VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off Parameters Test Conditions Min. Typ. Max. Unit PLL Stable Time ¾ ¾ 130 ¾ ms PLL Programming resolution ¾ ¾ 1 ¾ MHz Rev. 1.10 9 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and S y s te m C lo c k P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r P ip e lin in g P C P C + 1 F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 ) P C + 2 F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 ) System Clocking and Pipelining 1 C A L L D E L A Y 3 4 E x e c u te In s t. 1 : 5 F e tc h In s t. 1 C P L [1 2 H ] : 6 M O V A ,[1 2 H ] 2 D E L A Y : F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7 N O P Instruction Fetching Rev. 1.10 10 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. P ro g ra m T o p o f S ta c k C o u n te r S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 6 levels and is neither part of the data nor part of the program space, and is neither readable nor B o tto m P ro g ra m M e m o ry S ta c k L e v e l 3 o f S ta c k S ta c k L e v e l 6 Program Counter Bits Mode b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 SPI Interrupt 0 0 0 0 0 0 0 0 0 1 0 0 Timer/Event Counter Overflow 0 0 0 0 0 0 0 0 1 0 0 0 External interrupt 0 0 0 0 0 0 0 0 1 1 0 0 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Skip Program Counter + 2 Loading PCL PC11 PC10 PC9 Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits Rev. 1.10 @7~@0: PCL bits S11~S0: Stack register bits 11 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Arithmetic and Logic Unit - ALU offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: Structure The Program Memory has a capacity of 4K´15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. · Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA Special Vectors · Logic operations: AND, OR, XOR, ANDM, ORM, Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts. XORM, CPL, CPLA · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, · Location 000H RLC This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. · Increment and Decrement INCA, INC, DECA, DEC · Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI · Location 004H This vector is used by serial interface. When 8-bits of data have been received or transmitted success-fully from serial interface. The program will jump to this location and begin execution if the interrupt is enable and the stack is not full. Program Memory The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices 0 0 0 H · Location 008H This vector is used by the timer/event counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. In itia lis a tio n V e c to r 0 0 4 H · Location 00CH This vector is used by the external interrupt. If the INT external input pin on the device receives a high to low transition, the program will jump to this location and begin execution, if the interrupt is enabled and the stack is not full. S P I In te rru p t V e c to r 0 0 8 H T im e r /E v e n t C o u n te r In te rru p t V e c to r 0 0 C H · Table location E x te rn a l In te rru p t V e c to r F F F H Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: ²TABRDC² and ²TABRDL², transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). 1 5 b its Program Memory Structure Table Location Bits Instruction b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC[m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL[m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: PC11~PC8: Current program counter bits when TBHP is disabled TBHP register bit3~bit0 when TBHP is enabled @7~@0: Table Pointer TBLP bits Rev. 1.10 12 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW ¨ The three methods are shown as follows: The instructions ²TABRDC [m]² (the current page, one page=256words), where the table location is defined by TBLP (07H) in the current page. And the configuration option TBHP is disabled (default). ¨ The instructions ²TABRDC [m]², where the table location is defined by registers TBLP (07H) and TBHP (01FH). And the configuration option TBHP is enabled. ¨ The instructions ²TABRDL [m]², where the table location is defined by register TBLP (07H) in the last page (F00H~FFFH). will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction ²TABRDC [m]² reads the ROM data as defined by TBLP and TBHP value. Otherwise, the configuration option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM data as defined by TBLP and the current program counter bits. Table Program Example Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the configuration option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It P ro g ra m C o u n te r H ig h B y te The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is ²F00H² which refers to the start address of the last page within the 4K Program Memory of device. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed. T B H P P ro g ra m M e m o ry T B L P T B L H T a b le C o n te n ts H ig h B y te T B L H S p e c ifie d b y [m ] T a b le C o n te n ts L o w H ig h B y te o f T a b le C o n te n ts B y te S p e c ifie d b y [m ] L o w B y te o f T a b le C o n te n ts Table Read - TBLP/TBHP Table Read - TBLP only Rev. 1.10 P ro g ra m M e m o ry T B L P 13 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW tempreg1 tempreg2 db db : : ? ? ; temporary register #1 ; temporary register #2 mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a : : ; to the last page or present page tabrdl tempreg1 ; ; ; ; dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempregl data at prog. memory address ²F06H² transferred to tempreg1 and TBLH transfers value in table referenced by table pointer to tempreg2 data at prog.memory address ²F05H² transferred to tempreg2 and TBLH in this example the data ²1AH² is transferred to tempreg1 and data ²0FH² to register tempreg2 the value ²00H² will be transferred to the high byte register TBLH : : org F00h ; sets initial address of last page dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.10 14 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory Structure This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value ²00H². The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8-bit wide. The start address of the Data Memory for all devices is the address ²00H². Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. H T 8 2 K 7 5 R E W H T 8 2 M 7 5 R E W 0 0 H 0 0 H S p e c ia l P u r p o s e D a ta M e m o ry S p e c ia l P u r p o s e D a ta M e m o ry 3 F H 4 0 H 3 F H 4 0 H G e n e ra l P u rp o s e D a ta M e m o ry G e n e ra l P u rp o s e D a ta M e m o ry D F H B F H Data Memory Structure Rev. 1.10 15 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW H T 8 2 M 7 5 R E W H T 8 2 K 7 5 R E W 0 0 H IA R 0 0 0 H 0 1 H M P 0 0 1 H M P 0 0 2 H IA R 1 0 2 H IA R 1 0 3 H M P 1 0 3 H M P 1 0 4 H IA R 0 0 4 H A C C 0 5 H A C C 0 5 H 0 6 H P C L 0 6 H P C L 0 7 H T B L P 0 7 H T B L P 0 8 H T B L H 0 8 H T B L H 0 9 H W D T S 0 9 H W D T S 0 A H S T A T U S 0 A H S T A T U S 0 B H IN T C 0 B H IN T C 0 C H 0 D H T M R H T M R H T M R L 0 C H 0 D H 0 E H T M R C 0 E H T M R C 0 F H P T R 0 F H P T R 1 0 H T M R L 1 0 H 1 1 H 1 1 H S p e c ia l P u r p o s e D a ta M e m o ry 1 2 H P A 1 3 H P A C 1 2 H P A 1 3 H P A C 1 4 H P B 1 4 H P B 1 5 H P B C 1 5 H P B C 1 6 H P C 1 6 H P C 1 7 H P C C 1 7 H S p e c ia l P u r p o s e D a ta M e m o ry P C C 1 8 H 1 8 H P D 1 9 H 1 9 H P D C 1 A H 1 A H P E 1 B H 1 C H 1 B H 1 C H P E C 1 D H C T L R 1 D H C T L R 1 E H 1 F H 2 0 H 1 E H T B H P 1 F H 2 0 H 2 1 H T B H P 2 1 H 2 2 H S P IR 2 2 H S P IR 2 3 H 2 4 H S B C R S B C R 4 0 H G e n e ra l P u rp o s e D a ta M e m o ry (1 2 8 B y te s ) 2 3 H 2 4 H 4 0 H B F H S B D R D F H S B D R G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) : U n u s e d , re a d a s "0 0 " Special Purpose Data Memory Structure Rev. 1.10 16 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of 00H. pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from all of the data banks if the Data Memory is divided into 2 or more banks. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation. Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access all data banks if the Data Memory is divided into 2 or more banks. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ org 00h start: mov mov mov mov a,04h ; setup size of block block,a a,offset adres1; Accumulator loaded with first RAM address mp,a ; setup memory pointer with first RAM address clr inc sdz jmp IAR0 mp0 block loop loop: ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.10 17 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Accumulator - ACC Otherwise, the configuration option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM data as defined by TBLP and the current program counter bits. The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. The Z, OV, AC and C flags generally reflect the status of the latest operations. · C is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. · AC is set if an operation results in a carry out of the Look-up Table Registers - TBLP, TBLH, TBHP low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Once TBHP is enabled, the instruction ²TABRDC [m]² reads the ROM data as defined by TBLP and TBHP value. · Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. · OV is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. · PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. · TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. b 7 b 0 T O P D F O V Z A C C S T A T U S R e g is te r A r C a A u Z e ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g S y s te m M P o w e r d o w W a tc h d o g N o t im p le m a n n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 " Status Register Rev. 1.10 18 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW ciated control register known as PAC, PBC, etc., also mapped to specific addresses with the Data Memory. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and Wake-up option for all I/O pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Interrupt Control Registers - INTC The microcontroller provides an internal timer/event counter overflow interrupt. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the ²RETI² instruction. The microcontroller provides 24 or 40 bit bidirectional input/output lines labeled with port names known as PA, PB, etc. These I/O ports are mapped to the Data Memory with addresses as shown in the Special Purpose Data Memory table. All of these I/O lines can be used for input and output operations and one line as an input only. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Timer/Event Counter Registers TMRH, TMRL, TMRC All devices possess a single internal 16-bit count-up timer. An associated register pair known as TMRL/TMRH is the location where the timer 16-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMRC, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. The individual pull-high resistor is selected to be connected to each pin on Port A by a configuration option. A configuration option can determine if the pull-high resistors are connected to the lower significant four pins or higher significant four pins on each I/O port except Port A. Watchdog Timer Register - WDTS The Watchdog function in the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows.To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the port pin changes from high to low. This function is especially suitable for applications that can be woken up via external switches. All of the I/O pins can be configured to have the capability to wake-up the device by high to low and low to high edges using different configuring ways. It means once the I/O pin is configured to have the Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have correspondingly designated registers known as PA, PB, etc. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an asso- Rev. 1.10 19 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW V D a ta B u s W r ite C o n tr o l R e g is te r P u ll- H ig h O p tio n C o n tr o l B it Q D C K D D W e a k P u ll- u p Q S C h ip R e s e t R e a d C o n tr o l R e g is te r W r ite D a ta R e g is te r P A O u tp u t C o n fig u r a tio n R e a d D a ta R e g is te r W a k e -u p fo r a n y I/O I/O P o rt D a ta B it Q D C K S Q M P u ll- L o w U X p o rt W a k e - u p o p tio n fo r a n y I/O P A 2 /T M R p o rt Input/Output Ports · External Timer Clock Input wake-up capability, the device can be woken up by any I/O transition. For more details, refer to the Configuration Option Section later. The external timer pin TMR is pin-shared with the I/O pin PA2. To configure this pin to operate as timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, this pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. I/O Port Control Registers Each I/O port has its own control register known as PAC, PBC, etc., to control the input/output configuration. With this control register, each CMOS/NMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associated port control register. PC and PB can be set CMOS or NMOS output for option. · External Interrupt Input The external interrupt pin INT is pin-shared with the I/O pin PC2. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS/NMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Programming Considerations Pin-shared Functions Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the control registers, known as PAC, PBC, etc., are programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated data registers are first programmed. Selecting which pins are The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. Rev. 1.10 20 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Timer Registers - TMRH, TMRL inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. The TMRH and TMRL registers are two 8-bit special function register locations within the special purpose Data Memory where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA2/TMR pin. The timer will count from the initial value loaded by the preload register to the full count value of FFFFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 0000H 0000H to FFFFH the preload registers must first be cleared to 0000H 0000H. It should be noted that after power-on the preload registers will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload registers during this period will remain in the preload registers and will only be written into the actual counter the next time an overflow occurs. All I/O have the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low and low to high transition of any of the selected wake-up pins. Timer/Event Counters The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The device contains an internal 16-bit count-up timer which has three operating modes. The timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. Accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMRL, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMRH, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register directly will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. There are three registers related to the Timer/Event T 1 S y s te m T 2 T 3 T 4 T 1 T 2 T 3 T 4 C lo c k P o rt D a ta W r ite to P o r t R e a d fro m P o rt Read/Write Timing Counter, TMRL, TMRH and TMRC. The TMRL/TMRH register pair are the registers that contains the actual timing value. Writing to this register pair places an initial starting value in the Timer/Event Counter preload register while reading retrieves the contents of the Timer/Event Counter. The TMRC register is a Timer/Event Counter control register, which defines the timer options, and determines how the timer is to be used. The timer clock source can be configured to come from the internal system clock divided by 4 or from an external clock on shared pin PA2/TMR. Configuring the Timer/Event Counter Input Clock Source Timer Control Register - TMRC The timer clock source can originate from either the system clock divided by 4 or from an external clock source. The system clock divided by 4 is used when the timer is in the timer mode or in the pulse width measurement mode. The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMRC. Together with the TMRL and TMRH registers, these three registers control the full operation of the Timer/Event Counter. Before the timer can be used, it is essential that the TMRC register is fully programmed with the right An external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin PA2/TMR. Depending upon the condition of the TE bit, each high to low, or low to high transition on the PA2/TMR pin will increment the counter by one. Rev. 1.10 21 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Configuring the Timer Mode data to ensure its correct operation, a process that is normally carried out during program initialisation. In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The timer-on bit, TON, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To choose which of the three modes the timer is to operate in, the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the required logic levels. The timer-on bit TON or bit 4 of the TMRC register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register. D a ta B u s L o w B y te B u ffe r T M 1 fS T M R Y S /4 1 6 - B it P r e lo a d R e g is te r T M 0 T im e r /E v e n t C o u n te r M o d e C o n tro l T E H ig h B y te T O N R e lo a d O v e r flo w to In te r r u p t L o w B y te 1 6 - B it T im e r /E v e n t C o u n te r 16-bit Timer/Event Counter Structure b 7 T M 1 b 0 T M 0 T O N T E T im e r /E v e n t C o u n te r C o n tr o l R e g is te r N o t im p le m e n te d , r e a d a s " 0 " T o d e fin e th e a c tiv e e d g e o f T M R 1 : a c tiv e o n h ig h to lo w 0 : a c tiv e o n lo w to h ig h p in in p u t s ig n a l T o e n a b le o r d is a b le tim e r c o u n tin g 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g m o d e T M 0 T M 1 n o 0 0 e v 1 0 tim 0 1 1 1 p u s e le c t m o d e n t c e r m ls e w e a v a o u n te o d e ( id th m ila b r m in te e a le o d e ( e x te r n a l c lo c k ) r n a l c lo c k ) s u re m e n t m o d e Timer/Event Counter Control Register fS Y S /4 In c re m e n t T im e r C o u n te r T im e r + 1 T im e r + 2 T im e r + N T im e r + N + 1 Timer Mode Timing Chart Rev. 1.10 22 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Configuring the Event Counter Mode start counting until the PA2/TMR pin returns to its original high level. At this point the TON bit will be automatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA2/TMR pin and stop counting when the PA2/TMR pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA2/TMR. As the TON bit has now been reset any further transitions on the PA2/TMR pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA2/TMR pin and not by the logic level. In this mode, a number of externally changing logic events, occurring on external pin PA2/TMR, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA2/TMR pin receives a low to high transition. If the TE bit is high, the counter will increment each time PA2/TMR receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To ensure that the external pin PA2/TMR is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. In the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. If the timer interrupt is enabled, an interrupt signal will also be generated. To ensure that the external pin PA2/TMR is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA2/TMR can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA2/TMR pin, the timer will E x te rn a l E v e n t In c re m e n t T im e r C o u n te r T im e r + 1 T im e r + 2 T im e r + 3 Event Counter Mode Timing Chart E x te r n a l T im e r P in In p u t T O N ( w ith T E = 0 ) fS Y S In c re m e n t T im e r C o u n te r T im e r fS Y S + 1 + 2 + 3 + 4 is s a m p le d a t e v e r y fa llin g e d g e o f T 1 . Pulse Width Measure Mode Timing Chart Rev. 1.10 23 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW I/O Interfacing When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA2 pin for correct operation. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register PAC bit 2 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not sync h ro n is ed w i t h t h e i n t e r nal t i m e r c l o ck, t h e microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. Rev. 1.10 When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. But the timer for internal clock overflow can¢t wake up the MCU if MCU is in a Power down condition. 24 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer low register mov tmrl,a; ; load low register first mov a, 0aah ; setup timer high register mov tmrh,a mov a,080h ; setup Timer control register mov tmrc,a ; timer mode is used ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start Timer/Event Counter - note mode bits must be previously setup Interrupts new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Interrupts are an important part of any microcontroller system. When an internal function such as a Timer/Event Counter overflow, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several interrupts generated by internal interrupts events and external interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single interrupt control register, which is located in the Data Memory. By controlling the appropriate enable bits in this register the interrupt can be enabled or disabled. Also when an interrupt occurs, the request flag will be set by the microcontroller. The global enable bit if cleared to zero will disable all interrupts. Once an interrupt subroutine is serviced, other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Interrupt Operation A Timer/Event Counter overflow, will generate an interrupt request by setting its corresponding request flag, if its interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a Rev. 1.10 25 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Timer/Event Counter Interrupt condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and its corresponding timer interrupt enable bit, ETI, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H, will take place. When the interrupt is serviced, the timer interrupt request flag, TF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. Programming Considerations By disabling the interrupt enable bit, the requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this b 7 b 0 E IF T F S IF E E I E T I E S II E M I IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le C o n tr o l S e r ia l in te r fa c e in te r r u p t 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le C o n tro l T h e e x te rn a l In te rru p t 1 : e n a b le 0 : d is a b le S e r ia l In te r fa c e In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e E x te r n a l In te r r u p t R e q u it F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 " Interrupt Control Register A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e P r io r ity S e r ia l In te r fa c e In te r r u p t R e q u e s t F la g S IF E S II T im e r /E v e n t C o u n te r O v e r flo w In te r r u p t R e q u e s t F la g T F E T 0 I E x te rn a l In te rru p t R e q u e s t F la g E IF E E I H ig h In te rru p t P o llin g L o w Interrupt Structure Rev. 1.10 26 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. V D D 0 .9 V R E S tR S T D S S T T im e - o u t In te rn a l R e s e t Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. V D D 1 0 0 k W R E S 0 .1 m F V S S Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. 0 .0 1 m F V D D 1 0 0 k W R E S Reset Functions 1 0 k W There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: 0 .1 m F V S S · Power-on Reset Enhanced Reset Circuit The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be Rev. 1.10 D D More information regarding external reset circuits is located in Application Note HA0075E HA0075E on the Holtek website. · RES Pin Reset This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point. R E S 0 .4 V 0 .9 V D D D D tR S T D S S T T im e - o u t In te rn a l R e s e t RES Reset Timing Chart 27 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW · Low Voltage Reset - LVR Reset Initial Conditions The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options. The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 u RES or LVR reset during normal operation u WDT time-out reset during normal operation 1 S T D RES wake-up HALT 1 tR 1 u S S T T im e - o u t RES reset during power-on 0 L V R 0 1 WDT time-out reset during Power Down Note: ²u² stands for unchanged In te rn a l R e s e t The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Low Voltage Reset Timing Chart Item · Watchdog Time-out Reset during Normal Operation Condition After RESET The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to ²1². Program Counter Reset to zero Interrupts All interrupts will be disabled W D T T im e - o u t WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off tR S T D S S T T im e - o u t In te rn a l R e s e t Input/Output Ports I/O ports will be setup as inputs WDT Time-out Reset during Normal Operation Timing Chart Stack Pointer Stack Pointer will point to the top of the stack · Watchdog Time-out Reset during Power Down The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for tSST details. W D T T im e - o u t tS S T S S T T im e - o u t WDT Time-out Reset during Power Down Timing Chart Rev. 1.10 28 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register Reset (Power-on) WDT time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* PCL 000H 000H 000H 000H 000H ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu STATUS -00 xxxx -1u uuuu -uu uuuu -01 uuuu -11 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMRL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 00-0 1- 00-0 1- 00-0 1- 00-0 1- uu-u u- PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PD * 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC * 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PE * 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC * 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu WDTS - -111 - -111 - -111 - -111 - -uuu MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu CTLR 0100 0x00 0100 0x00 0100 0x00 0100 0x00 uuuu uxuu PTR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TBHP - 0000 - 0000 - 0000 - 0000 0000 uuuu SPIR 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu SBCR 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu SBDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Note: ²*² For the HT82K75REW HT82K75REW only ²-² not implemented ²u² means ²unchanged² ²x² means ²unknown² Rev. 1.10 29 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW Oscillator signer if the power consumption is to be minimised. The clock source for these devices is provided by an integrated oscillator requiring no external components. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. This oscillator has one fixed frequencies of 6MHz. Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 71ms at 3V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. Power Down Mode and Wake-up If the configuration option has enabled the Watchdog Timer internal oscillator, then the Watchdog Timer will continue to run when in the Power Down Mode and will thus consume some power. Power Down Mode Wake-up All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: · An external reset · An external falling or rising edge on any of the I/O pins · A system interrupt · A WDT overflow (if the contents of the PTR are zeros) · A PTR overflow occurs (if the contents of the PTR are not equal to zeros) If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Note that the WDT time-out will not occur if the contents of the Period Timer Register (PTR) are not equal to zeros. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is executed, the following will occur: · The system oscillator will stop running and the appli- cation program will stop at the ²HALT² instruction. · The Data Memory contents and registers will maintain their present condition. Each pin on Port A or any nibble on other ports can be setup via configuration options to permit a negative or positive transition on the pin to wake-up the system. When a port pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction. · The WDT will be cleared and resume counting if the WDT function is enabled. · The I/O ports will maintain their present condition. · In the status register, the Power Down flag, will be set and the Watchdog time-out flag, TO, will be cleared. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction. In this situation, the interrupt will not be immediately serviced, but will rather be serviced later when the related interrupt is Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de- Rev. 1.10 30 August 13, 2010 HT82M75REW/HT82K75REW HT82M75REW/HT82K75REW ternal WDT oscillator and its clock period may vary with VDD, temperature and process variation. The WDT clock is further divided by an internal 6-stage counter followed by a 7-stage prescaler to obtain longer WDT time-out period selected by the WDT prescaler rate selection bits, WS2~WS0, in the associated WDT register known as WDTS. finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 512 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by additional one or more cycles. If the wake-up results in the execution of the next instruction following the ²HALT² instruction, this will be executed immediately after the 512 system clock period delay has ended. There is only one instruction to clear the Watchdog Timer known as ²CLR WDT². As the instruction ²CLR WDT² is executed, all contents of the 6-stage counter and 7-stage prescaler will be clear. It makes the WDT time-out period more accurate relatively. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by its own internal dedicated internal WDT oscillator. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. Although the WDT overflow is a source to wake up the MCU from the Power Down Mode, there are some limitations on the conditions at which the WDT overflow occurs. If the WDT function is enabled and the PTR