HSP43168/883 MIL-STD883 HSP43168 HSP43168GM-25/883 HSP43168GM-33/883 OUT18 - Datasheet Archive

 

S E M I C O N D U C T O R Dual FIR Filter January 1994 Features Description · This Circuit is Processed in Accordance to

 

HSP43168/883 HSP43168/883 S E M I C O N D U C T O R Dual FIR Filter January 1994 Features Description · This Circuit is Processed in Accordance to MIL-STD883 MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HSP43168/883 HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters. · Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR · 10-Bit Data and Coefficients · On-Board Storage for 32 Programmable Coefficient Sets · Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 20-Bit Data and Coefficients The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported. · Programmable Decimation to 16 · Programmable Rounding on Output · Standard Microprocessor Interface · 33MHz, 25.6MHz Versions Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the decimation registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16x16. Applications · Quadrature, Complex Filtering · Correlation · Image Processing The flexibility of the Dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. · PolyPhase Filtering · Adaptive Filtering Ordering Information TEMPERATURE RANGE PART NUMBER o The HSP43168 HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface. PACKAGE o HSP43168GM-25/883 HSP43168GM-25/883 -55 C to +125 C 84 Lead PGA HSP43168GM-33/883 HSP43168GM-33/883 -55oC to +125oC 84 Lead PGA Block Diagram 10 CIN0 - 9 A0 - 8 WR# CSEL0 - 4 CONTROL/ CONFIGURATION 9 COEFFICIENT BANK A COEFFICIENT BANK B 10 INA0 - 9 INB0 - 9/ OUT0 - 8 FIR CELL A 10 FIR CELL B MUX MUX MUX / ADDER 9 19 OUT9 - 27 OEL# OEH# CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1994 3-169 File Number 3177.2 HSP43168/883 HSP43168/883 Pinouts 84 PIN PGA TOP VIEW 11 L 10 9 8 7 6 5 2 1 INB4 INB5 INB6 INB9 L GND INB7 INB8 INA1 K INA0 INA2 J INA4 H K OUT18 OUT18 J OUT19 OUT19 OUT17 OUT17 H OUT21 OUT21 OUT20 OUT20 G OUT24 OUT24 OUT23 OUT23 OUT25 OUT25 INA7 INA5 INA6 G F OUT27 OUT27 OUT22 OUT22 OUT26 OUT26 INA8 INA9 VCC F E OEH# GND CIN2 CIN1 CIN0 E D VCC ACCEN GND CIN3 D C TXFR# CIN6 CIN4 C CIN7 CIN5 B B VCC 3 INA3 GND OUT15 OUT15 OUT14 OUT14 OUT12 OUT12 OUT10 OUT10 OUT11 OUT11 INB1 4 OUT16 OUT16 OUT13 OUT13 VCC INB0 INB2 OUT9 OEL# INB3 CLK FWRD # A5 SHFT EN# MUX0 MUX1 A6 CSEL0 A0 A3 A2 VCC RVRS# WR# GND A1 A4 A7 A8 11 A 10 9 8 7 6 5 CSEL2 CIN9 CSEL1 CSEL3 CSEL4 CIN8 4 3 2 1 4 3 2 A PIN 'A1' ID 1 84 PIN PGA BOTTOM VIEW 11 10 9 8 7 6 5 A RVRS # WR# GND A1 A4 A7 A8 B SHFT EN# A0 A3 A2 VCC A5 A6 CSEL0 C TXFR# CSEL1 CSEL3 CSEL4 CIN8 A PIN 'A1' ID CIN5 B CIN6 CIN4 C CIN3 D CIN2 FWRD # CIN7 GND MUX0 MUX1 CIN1 CIN0 E CSEL2 CIN9 D VCC ACCEN E OEH# GND F OUT27 OUT27 OUT22 OUT22 OUT26 OUT26 INA8 INA9 VCC F G OUT24 OUT24 OUT23 OUT23 OUT25 OUT25 INA7 INA5 INA6 G INA3 INA4 H INA0 INA2 J H OUT21 OUT21 OUT20 OUT20 J CLK OUT19 OUT19 OUT17 OUT17 K OUT18 OUT18 L GND 11 VCC OUT9 VCC INB2 GND INB7 INB8 INA1 K OUT15 OUT15 OUT14 OUT14 OUT12 OUT12 OUT10 OUT10 OUT11 OUT11 INB1 INB4 INB5 INB6 INB9 L 4 3 2 1 10 OUT16 OUT16 OUT13 OUT13 OEL# INB3 9 8 7 INB0 6 3-170 5 HSP43168/883 HSP43168/883 Pin Description NAME PIN NUMBER TYPE DESCRIPTION VCC B5, D11, K10, K7, F1 VCC: +5V power supply pin. GND A9, E10, L11, K4, D2 Ground. CIN0-9 E1-3, D1, C1-2, B1-3, A1 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. A0-8 A5-8, B6-8, C6-7 I Control/Coefficient Address Bus. Processor interface for addressing control and coefficient registers. A0 is the LSB. WR# A10 I Control/Coefficient Write Clock. Data is latched into the control and coefficient registers on the rising edge of WR#. CSEL0-4 A2-4, B4, C5 I Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. INA0-9 K1, J1-2, H1-2, G1-3, F2-3 I Input to FIR A. INA0 is the LSB INB0-9 L1-5, K2-3, K5-6, J5 I/O Bidirectional Input for FIR B. INB0 is the LSB and is input only.When used as output, INB1-9 are the LSB's of the output bus. OUT9-27 OUT9-27 F9-11 F9-11, G9-11 G9-11, H10-11 H10-11, J10-11 J10-11, J7, K11, K8-9, L6-10 L6-10 O 19 MSB's of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 OUT27 is the MSB. SHFTEN# B11 I Shift Enable. This active low input enables shifting of data through the decimation registers. FWRD# C10 I Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALU's through the "a" input. When high, the "a" inputs to the ALUs are zeroed. RVRS# A11 I Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALU's through the "b" input. When high, the "b" inputs to the ALUs are zeroed. TXFR# C11 I Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). MUX0-1 B9-10 B9-10 I Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0 lists the various configurations. CLK E9 I Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR#) and the output enables (OEL#, OEH#) are registered by the rising edge of CLK. OEL# J6 I Output Enable Low. This tristate control enables the LSB's of the output bus to INB1-9 when OEL# is low. OEH# E11 I Output Enable High. This tristate control enables OUT9-27 OUT9-27 when OEH# is low. ACCEN D10 I Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback path in the Accumulator. 3-171 Specifications HSP43168/883 HSP43168/883 Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . .GND-0.5V to VCC+0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance JA JC Ceramic PGA Package . . . . . . . . . . . . 33.5oC/W 7.5oC/W Maximum Package Power Dissipation at +125oC Ceramic PGA Packazge . . . . . . . . . . . . . . . . . . . . . . . . . . 1.49 W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32529 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55o TA + 125oC 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55o TA + 125oC - 0.8 V Logical One Input Voltage Clock VIHC VCC = 5.5V 1, 2, 3 -55o TA + 125oC 3.0 - V Logical Zero Input Voltage Clock VILC VCC = 4.5V 1, 2, 3 -55o TA + 125oC - 0.8 V Output HIGH Voltage VOH IOH = -400µA VCC= 4.5V (Note 1) 1, 2, 3 -55o TA + 125oC 2.6 - V Output LOW Voltage VOL IOL = +2.0mA VCC= 4.5V (Note 1) 1, 2, 3 -55o TA + 125oC - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55o TA + 125oC -10 +10 µA Output Leakage Current IO VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55o TA + 125oC -10 +10 µA Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.5V, Outputs Open 1, 2, 3 -55o TA + 125oC - 500 µA Operating Power Supply Current ICCOP f = 25.6MHz, VIN = VCC or GND, VCC = 5.5V (Note 2) 1, 2, 3 -55o TA + 125oC - 281.6 mA 7, 8 -55o TA + 125oC - - - Functional Test FT (Note 3) NOTES: 1. Interchanging of force and sense conditions is permitted. 2. Operating Supply Current is proportional to frequency, typical rating is 11mA/MHz. 3. Tested as follows: f = 1MHz, VIH(clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, VIL = 0.4V, VOH 1.5V, and VOL 1.5V. 3-172 Specifications HSP43168/883 HSP43168/883 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested PARAMETER SYMBOL (NOTE 1) CONDITIONS GROUP A SUBGROUPS (-33MHz) (-25MHz) TEMPERATURE MIN MAX MIN MAX UNITS CLK Period TCP 9, 10, 11 -55o TA +125oC 30 - 39 - ns CLK High TCH 9, 10, 11 -55o TA +125oC 12 - 15 - ns CLK Low TCL 9, 10, 11 -55o TA +125oC 12 - 15 - ns WR# Period TWP 9, 10, 11 -55o TA +125oC 30 - 39 - ns WR# High TWH 9, 10, 11 -55o TA +125oC 12 - 15 - ns WR# Low TWL 9, 10, 11 -55o TA +125oC 12 - 15 - ns Set-up Time; A0-8 to WR# Low TAWS 9, 10, 11 -55o TA +125oC 10 - 10 - ns Hold Time; A0-8 to WR# High TAWH 9, 10, 11 -55o TA +125oC 1 - 1 - ns Set-up Time; CIN0-9 to WR# High TCWS 9, 10, 11 -55o TA +125oC 12 - 15 - ns Hold Time; CIN0-9 to WR# High TCWH 9, 10, 11 -55o TA +125oC 1.5 - 1.5 - ns Set-up Time; WR# Low to CLK Low TWLCL Note 3 9, 10, 11 -55o TA +125oC 5 - 8 - ns Set-up Time; CIN0-9 to CLK Low TCVCL Note 3 9, 10, 11 -55o TA +125oC 8 - 8 - ns Set-up Time; CSEL0-5, SHFTEN#, FWRD#, RVRS#, TXFR#, MUX0-1 to CLK High TECS 9, 10, 11 -55o TA +125oC 15 - 17 - ns Hold Time; CSEL0-5, SHFTEN#, FWRD#, RVRS#, TXFR#, MUX0-1 to CLK High TECH 9, 10, 11 -55o TA +125oC 0 - 0 - ns CLK to Output Delay OUT0-27 OUT0-27 TDO 9, 10, 11 -55o TA +125oC - 15 - 17 ns Output Enable Time TOE 9, 10, 11 -55o TA +125oC - 12 - 12 ns Note 2 NOTES: 1. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 3.0V and 0V; Timing reference levels (CLK) 2.0V; All others 1.5V. VCC = 4.5V and 5.5V. Output load per test load circuit with CL = 40 pF. Output transition is measured at VOH > 1.5V and V OL < 1.5V. 2. Transition is measured at ±200mV from steady state voltage, Output loading per test load circuit, CL = 40pF. 3. Set-up time requirements for loading of data on CIN0-9 to guarantee recognition on the following clock. 3-173 Specifications HSP43168/883 HSP43168/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (-33MHz) PARAMETER Input Capacitance (-25MHz) SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX MIN MAX UNITS CIN VCC = Open, f=1 MHz All measurements are referenced to device GND. 1 TA = +25oC - 12 - 12 pF 1 TA = +25oC - 12 - 12 pF 1, 2 -55o TA +125oC - 12 - 12 ns Output Capacitance COUT Output Disable Time TOD Output Rise Time TR From 0.8V to 2.0V 1, 2 -55o TA +125oC - 8 - 8 ns Output Fall Time TF From 2.0V to 0.8V 1, 2 -55o TA +125oC - 8 - 8 ns NOTE: 1. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 2. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D AC Test Load Circuit S1 DUT *CL IOH ± 1.5V * INCLUDES STRAY AND JIG CAPACITANCE EQUIVALENT CIRCUIT SWITCH S1 OPEN FOR ICCSB AND ICCOP TEST 3-174 IOL HSP43168/883 HSP43168/883 Waveforms TCP TCH TCL CLK TECS TECH CSEL0-4, MUX0-1 SHFTEN#, FWRD#, RVRS#, TXFR#, INA0-9, INB0-9 TDO OUT0-27 OUT0-27 TWLCL TWP TWH TWL WR# TAWS TAWH A0-8 TCWS TCWH CIN0-15 CIN0-15 TCVCL 1.5V OEL#, OEH# 1.5V TOD TOE 1.7V OUT0-27 OUT0-27 HIGH IMPEDANCE 1.3V HIGH IMPEDANCE OUTPUT ENABLE, DISABLE TIMING 2.0V 2.0V 0.8V 0.8V TRF TRF OUTPUT RISE AND FALL TIMES 3-175 HSP43168/883 HSP43168/883 Burn-In Circuit 84 PIN PGA BOTTOM VIEW 11 10 9 8 7 6 5 4 A RVRS # WR# GND A1 A4 A7 A8 B SHFT MUX0 MUX1 EN# A0 A3 A2 VCC C TXFR# FWRD # A5 A6 3 2 CSEL0 1 CSEL1 CSEL3 CSEL4 CIN8 A PIN 'A1' ID CSEL2 CIN9 CIN7 CIN5 B CIN6 CIN4 C GND CIN3 D CIN2 CIN1 CIN0 E D VCC ACCEN E OEH# GND F OUT27 OUT27 OUT22 OUT22 OUT26 OUT26 INA8 INA9 VCC F G OUT24 OUT24 OUT23 OUT23 OUT25 OUT25 INA7 INA5 INA6 G H OUT21 OUT21 OUT20 OUT20 INA3 INA4 H J OUT19 OUT19 OUT17 OUT17 INA0 INA2 J K OUT18 OUT18 L CLK VCC OEL# INB3 OUT9 VCC INB2 GND INB7 INB8 INA1 K GND OUT15 OUT15 OUT14 OUT14 OUT12 OUT12 OUT10 OUT10 OUT11 OUT11 INB1 INB4 INB5 INB6 INB9 L 4 3 2 1 11 OUT16 OUT16 OUT13 OUT13 10 9 8 INB0 7 6 5 5. F0 = 100KHz ±10%, F1 = F0/2, F2 = F1/2. . . , F16 = F15/2 F15/2, 40 to 60% duty cycle. NOTES: 1. VCC/2 (2.7V ±10%) used for outputs only. 2. 47K (±20%) resistor connected to all pins except VCC and GND 3. VCC = 5.5 ±0.5V. 6. Input voltage limits: VIL = 0.8V Max, VIH = 4.5 ±10% 4. 0.1µf (Min) capacitor between VCC and GND per position. PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 PIN NAME CIN8 CSEL4 CSEL3 CSEL1 A8 A7 A4 A1 GND WRB RVRS CIN5 CIN7 CIN9 CSEL2 VCC A2 A3 A0 MUX1 MUX0 BURN-IN SIGNAL F9 F12 F11 F9 F12 F10 F11 F12 GND F6 F12 F8 F10 F10 F10 VCC F11 F10 F13 F13 F12 PGA PIN B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 PIN NAME SHFTEN CIN4 CIN6 CSEL0 A6 A5 FWRD TXFR CIN3 GND ACCEN VCC CIN0 CIN1 CIN2 CLK GND OEHB VCC INA9 INA8 BURN-IN SIGNAL F14 F7 F9 F8 F11 F12 F13 F11 F10 GND F13 VCC F7 F8 F9 F0 GND F14 VCC F10 F9 PGA PIN F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 3-176 PIN NAME SUM26 SUM26 SUM22 SUM22 SUM27 SUM27 INA6 INA5 INA7 SUM25 SUM25 SUM23 SUM23 SUM24 SUM24 INA4 INA3 SUM20 SUM20 SUM21 SUM21 INA2 INA0 INB3 OELB SUM9 SUM17 SUM17 SUM19 SUM19 INA1 BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 F7 F6 F8 VCC/2 VCC/2 VCC/2 F5 F4 VCC/2 VCC/2 F3 F1 F4 F13 VCC/2 VCC/2 VCC/2 F2 PGA PIN K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 PIN NAME INB8 INB7 GND INB2 INB0 VCC SUM13 SUM13 SUM16 SUM16 VCC SUM18 SUM18 INB9 INB6 INB5 INB4 INB1 SUM11 SUM11 SUM10 SUM10 SUM12 SUM12 SUM14 SUM14 SUM15 SUM15 BURN-IN SIGNAL F9 F8 GND F3 F1 VCC VCC/2 VCC/2 VCC VCC/2 F10 F7 F6 F5 F2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 L11 GND GND HSP43168/883 HSP43168/883 Metallization Topology DIE DIMENSIONS: 314 x 348 x 19 ± 1mils GLASSIVATION: Type: Nitrox Thickness: 10kÅ METALLIZATION: Type: Si-Al or Si-Al-Cu Thickness: 8kÅ WORST CASE CURRENT DENSITY: 1.93 x 105 A/cm2 Metallization Mask Layout MUX0 WR# MUX1 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 VCC CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 CIN8 CIN9 HSP43168/883 HSP43168/883 CIN7 RVRS# CIN6 FWD# CIN5 SHIFTEN# CIN4 TXFR# GND ACCEN CIN3 VCC CIN2 CLK CIN1 CIN0 GND INA9 OEH# INA8 OUT27 OUT27 INA7 OUT26 OUT26 INA6 OUT25 OUT25 INA5 OUT24 OUT24 VCC OUT23 OUT23 INA4 OUT22 OUT22 INA3 OUT21 OUT21 OUT20 OUT20 INA2 OUT19 OUT19 INA1 OUT18 OUT18 INA0 OUT17 OUT17 INB9 3-177 GND OUT16 OUT16 OUT15 OUT15 OUT14 OUT14 OUT13 OUT13 OUT12 OUT12 OUT11 OUT11 VCC OUT9 OUT10 OUT10 OEL# INB0 INB1 INB2 INB3 INB4 GND INB5 INB6 INB7 INB8 VCC HSP43168/883 HSP43168/883 Packaging 85 PIN GRID ARRAY (PGA) LEAD MATERIAL: Type B LEAD FINISH: Type C PACKAGE MATERIAL: Ceramic, AI2O3 90% PACKAGE SEAL: Material: Gold/Tin Temperature: 320oC ± 10oC Method: Furnace Braze NOTE: All Dimensions are Min Max INTERNAL LEAD WIRE: Material: Aluminum Diameter: 1.25 Mil Bonding Method: Ultrasonic Wedge COMPLIANT OUTLINE: 38510-P-AC 38510-P-AC Mil-M-38510 Compliant Materials, Finishes and Dimensions , Dimensions are in inches. 3-178 S E M I C O N D U C T O R HSP43168/883 HSP43168/883 DESIGN INFORMATION Dual FIR Filter April 1995 The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. Functional Description As shown in Figure 1.0, the HSP43168 HSP43168 consists of two 4-multiplier FIR filter cells which process 10 bit data and coefficients. The FIR cells can operate as two independent 8-tap FIR filters or two 4-tap asymmetric filters at maximum I/O rates. A single filter mode is provided which allows the FIR cells to operate as one 16-tap FIR filter or one 8-tap asymmetric filter. On board coefficient storage for up to 32 sets of 8 coefficients is provided. The coefficient sets are user selectable and are programmed through a microprocessor interface. Programmable decimation to 16 is also provided. By utilizing decimation registers together with the coefficient sets, polyphase filters are realizable which allow the user to trade data rate for filter taps. The MUX/ Adder can be configured to either add or multiplex the outputs of the filter cells depending upon whether the cells are operating in single or dual filter mode. In addition, a shifter in the MUX/Adder is provided for implementation of filters with 10 bit data and 20 bit coefficients or vice versa. The 4 LSB's of the control word loaded at address 001H are used to configure the format of the FIR cell's data and coefficients. Bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the backward shifting decimation registers. Bits 5-9 are used to support programmable rounding on the output. TABLE 1 CONTROL ADDRESS 000H BITS DESCRIPTION The Dual has a 20 pin write only microprocessor interface for loading data into the Control Block and Coefficient Bank. The interface consists of a 10-bit data bus (CIN0-9), a 9 bit address bus (A0-8), and a write input (WR#) to latch the data into the on-board registers. The control and coefficient data can be loaded asynchronously to CLK. Decimation Factor 0000=No Decimation 1111=Decimation by 16 4 Mode Select 0 = Single FIlter Mode 1 = Dual FIlter Mode 5 Odd/Even Symmetry 0 = Even symmetric coefficients 1 = Odd symmetric coefficients 6 Microprocessor Interface 3-0 FUNCTION FIR A odd/even taps 0 = Odd number of taps in filter 1 = Even number of taps in filter 7 FIR B odd/even taps (Defined same as FIR A above) 8 FIR B Input Source 0 = Input from INA0-91 INA0-91 = Input from INB0-9 9 Not Used Set to 0 for proper operation Control Block TABLE 2 The Dual FIR is configured by writing to the registers within the Control Block. These registers are memory mapped to address 000H (H = Hexadecimal) and 001H on A0-8. The format of these registers is shown in Table 1 and Table 2. Writing the Control/Configuration registers causes a reset which lasts for 6 CLK cycles following the assertion of WR#. The reset caused by writing registers in the Control Block will not clear the contents of the Coefficient Bank. The 4 LSBs of the control word loaded at address 000H are used to select the decimation factor. For example, if the 4 LSBs are programmed with a value of 0010, the forward and reverse shifting decimation registers are each configured with a delay of 3. Bit 4 is used to select whether the FIR cells operate as two independent filters or one extended length filter. Coefficient symmetry is selected by bit 5. Bits 6 and 7 are programmed to configure the FIR cells for odd or even filter lengths. Bit 8 selects the FIR B input source when the FIR cells are configured for independent operation. Bit 9 must be programmed to 0. 3-179 CONTROL ADDRESS 001H BITS FUNCTION DESCRIPTION 0 FIR A Input Format 0 = Unsigned 1 = Two's Complement 1 FIR A Coefficient Format (Defined same as FIR A input) 2 FIR B Input Format (Defined same as FIR A input) 3 FIR B Coefficient (Defined same as FIR A input) 4 Data Reversal Enable 0 = Enabled 1 = Disabled 8-5 Round Position 0000 = 2-10 1011 = 21 9 Round Enable 0 = Enabled 1 = Disabled HSP43168 HSP43168 FIGURE 1. DUAL FIR FILTER 3-180 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. FIR Filter Cells Each FIR filter cell is based on an array of four 11x10 bit two's complement multipliers. The multipliers get one input from the ALUs which combine data shifting through the forward and backward decimation registers. The second input comes from the user programmable coefficient bank. The multiplier outputs feed an accumulator whose result is passed to the output section where it is multiplexed or added. Decimation Registers The forward and backward shifting registers are configurable for decimation by 1 to 16 (see Table 1). The backward shifting registers are used to take advantage of symmetry in linear phase filters by aligning data at the ALU's for preaddition prior to multiplication by the common coefficient. When the FIR cells are configured in single filter mode, the decimation registers in each cell are cascaded. This lengthened delay path allows computation of a filter which is twice the size of that capable in a single cell. The decimation registers also provide data storage for poly-phase or 2-D filtering applications (See Applications Examples section). The Data Feedback Circuitry in each FIR cell is responsible for transferring data from the forward to the backward shifting decimation registers. This circuitry feeds blocks of samples into the backward shifting decimation path in either reversed or non-reversed sample order. The MUX/DEMUX structure at the input to the Feedback Circuitry routes data to the LIFO's or the delay stage depending on configuration. The MUX on the Feedback Circuitry Output selects the storage element which feeds the backward shifting decimation registers. In applications requiring reversal of sample order, such as FIR filtering with decimation, the FIR cells are configured with data reversal enabled (see Table 2). In this mode, data is transferred from the forward to the backward shifting registers through a ping-ponged LIFO structure. While one LIFO is being read into the backward shifting path, the other is written with data samples. The MUX/DEMUX controls which LIFO is being written, and the MUX on the Feedback Circuitry output controls which LIFO is being read. A low on TXFR# and SHIFTEN#, switches the LIFO's being read and written, which causes the block of data read from the structure to be reversed in sample order (See Example 4 in the Application Examples section). The frequency with which TXFR# is asserted determines size of the data blocks in which sample order is reversed. For example, if TXFR# is asserted once every three CLK's, blocks of 3 data samples with order reversed, would be fed into the backward decimation registers. Note: altering the frequency or phase of TXFR# assertion once a filtering operation has been started will cause unknown results. In applications which do not require sample order reversal, the FIR cells must be configured with data reversal disabled (see Table 2). In addition, TXFR# must be asserted to ensure proper data flow. In this configuration, data to the backward shifting decimation path is routed though a delay stage instead of the ping-pong LIFO's. The number of registers in the delay stage is based on the programmed decimation factor. Note: data reversal must be disabled and TXFR# must be asserted for filtering applications which do not use decimation. The shifting of data through the forward and reverse decimation registers is enabled by asserting the SHFTEN# input. When SHFTEN# transitions high, data shifting is disabled, and the data sample latched into the part on the previous clock is the last input to the forward decimation path. When SHFTEN# is asserted, shifting of data through the decimation paths is enabled. The data sample at the part input when SHFTEN# is asserted will be the next data sample into the forward decimation path. When operating the FIR cells as two independent filters, FIR A receives input data via INA0-9 and FIR B receives data from either INA0-9 or INB0-9 depending on the configuration (Table 1). When the FIR cells are configured as a single extended length filter, the forward and backward decimation paths are cascaded. In this mode, data is transferred from the forward decimation path to the back- ward decimation path by the Data Feedback Circuitry in FIR B. Thus, the manner in which data is read into the backward shifting decimation path is determined by FIR B's configuration. When the decimation paths are cascaded, data is routed through the delay stage in FIR A's Data Feedback Circuitry. The configuration of the FIR cells as even or odd length filters determines the point in the forward decimation path from which data is multiplexed to the Data Feedback Circuitry. For example, if the FIR cell is configured as an odd length filter, data prior to the last register in the third forward decimation stage is routed to the Feedback Circuitry. If the FIR cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed to the Feedback Circuitry. This is required to insure proper data alignment with symmetric filter coefficients (See Application Examples). ALUs Data shifting through the forward and reverse decimation path feeds the "a" and "b" inputs of the ALUs respectively. The ALU's perform an "b+a" operation if the FIR cell is configured for even symmetric coefficients or an "b-a" operation if configured for odd symmetric coefficients. For applications in which a pre-add or subtract is not required, the "a" or "b" input can be zeroed by disabling FWRD# or RVRS# respectively. This has the effect of pro- 3-181 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. ducing an ALU output which is either "a", "-a", or "b" depending on the filter symmetry chosen. For example, if the FIR cell is configured for an even symmetric filter with FWRD# low and RVRS# high, the data shifting through the forward decimation registers would appear on the ALU output. Coefficient Bank The output of the ALU is multiplied by a coefficient from one of 32 user programmable coefficient sets. Each set consists of 8 coefficients (4 coefficients for FIR A and 4 for FIR B). The active coefficient set is selected using CSEL0-4. The coefficient set may be switched every clock to support polyphase filtering operations. The coefficients are loaded into on-board registers using the microprocessor interface, CIN0-9, A0-8, and WR#. Each multiplier within the FIR Cells is driven by a coefficient bank with one of 32 coefficients. These coefficients are addressed as shown in Table 3. The inputs A0-1 specify the Coefficient Bank for one of the four multipliers in each FIR Cell; A2 specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in which the coefficient is to be stored. For example, an address of 10dH would access the coefficient for the second multiplier in FIR B in the second coefficient set. the Mux/Adder is controlled by the MUX0-1 inputs as shown in Table 4. Applications requiring 10 bit data and 20 bit coefficients or 20 bit data and 10 bit coefficients are made possible by configuring the MUX/Adder to scale FIR B's output by 2-10 prior to summing with FIR A. When the Dual FIR is configured as two independent filters, the MUX0-1 inputs would be used to multiplex the filter outputs of each cell. For applications in which FIR A and B are configured as a single filter, the MUX/Adder is configured to sum the output of each FIR cell. TABLE 4 MUX0-1 DECODING MUX0-1 OUT0-27 OUT0-27 00 FIRA + FIRB (FIR B Scaled by 2-10) 01 FIRA + FIRB 10 FIRA 11 FIRB Input/Output Formats The Dual FIR supports mixed mode arithmetic with both unsigned and two's complement data and coefficients. The input and output formats for both data types is shown be low. If the Dual FIR is configured as an even symmetric filter with unsigned data and coefficients, the output will be unsigned. Otherwise, the output will be two's complement. TABLE 3 A8 A7-3 A2 A0-1 FIR BANK 1 xxxxx 0 00 A 0 1 xxxxx 0 01 A 1 1 xxxxx 0 10 A 2 1 xxxxx 0 11 A 3 1 xxxxx 1 00 B 0 9 8 7 6 5 4 3 2 1 0 1 xxxxx 1 01 B 1 -2o .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 1 xxxxx 1 10 B 2 1 xxxxx 1 11 B 3 INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL TWO'S COMPLEMENT OUTPUT DATA FORMAT OUT9-27 OUT9-27 FRACTIONAL TWO'S COMPLEMENT FIR Cell Accumulator 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 The registered outputs from the multipliers in each FIR cell feed the FIR cell's accumulator. The ACCEN input controls each accumulator's running sum and the latching of data from the accumulator into the Output Holding Registers. When ACCEN is low, feedback from the accumulator adder is zeroed which disables accumulation. Also, output from the accumulator is latched into the Output Holding Registers. When ACCEN is asserted, accumulation is enabled and the contents of the Output Holding Registers remain unchanged. 29 Output MUX/Adder The contents of each FIR Cell's Output Holding Register is summed or multiplexed in the Mux/Adder. The operation of 3-182 28 27 26 24 25 23 22 21 9 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL TWO'S COMPLEMENT 8 7 6 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL UNSIGNED HSP43168 HSP43168 9 8 7 6 5 4 3 2 1 0 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 INA0-9 FIR A INB0-9 FIR B M U X OUT9-27 OUT9-27 OUTPUT DATA FORMAT OUT9-27 OUT9-27 FRACTIONAL UNSIGNED 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FIGURE 2. USING HSP43168 HSP43168 AS TWO INDEPENDENT FILTERS 29 -9 In Figure 4, the order of the data samples within the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is given by the equation at the bottom of each block diagram. Figure 4a shows the data sample alignment at the pre-adders for the data/coefficient alignment shown in Figure 3. 8 2 7 2 6 4 2 2 5 2 3 2 2 2 1 2 0 2 -1 .2 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL UNSIGNED 8 7 6 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 C3 C3 C2 The MUX/Adder can be configured to implement programmable rounding at bit locations 2-10 through 21. The round is implemented by adding a 1 to the specified location (see Table 2.0). For example, to configure the part such that the output is rounded to the 10 MSBs, OUT18-27 OUT18-27, the round position would be chosen to be 2-1. The HSP43168 HSP43168 may be configured as two independent 8-tap symmetric filters as shown by the block diagram in Figure 2. Each of the FIR cells takes advantage of symmetric filter coefficients by pre-adding data samples common to a given coefficient. As a result, each FIR cell can implement an 8-tap symmetric filter using only four multipliers. Similarly, when the HSP43168 HSP43168 is configured in single filter mode a 16-tap symmetric filter is possible by using the multipliers in both cells. C0 x(n) X9 Example 1. Even-Tap Symmetric Filter Example C1 C0 Application Examples In this section a number of examples which show even, odd, symmetric, asymmetric and decimating filters are presented. These examples are intended to show different operational modes of the HSP43168 HSP43168. The examples are all based on a dual filter configuration. However, the same principles apply when the part is configured with both FIR cells operating as a single filter. C2 C1 h(n) X8 X7 X6 X5 X4 X3 X2 X1 X0 FIGURE 3. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP EVEN SYMMETRIC FILTER The dual filter application is configured by writing 1d0H to address 000H via the microprocessor interface, CIN0-9, A08, and WR#. Since this application does not use decimation, the 4th bit of the control register at address 001H must be set to disable data reversal (see Table 2). Failure to disable data reversal will produce erroneous results. A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED FORWARD STAGE. The operation of the FIR cell is better understood by comparing the data and coefficient alignment for a given filter output, Figure 3, with the data flow through the FIR cell, as shown in Figure 4. The block diagrams in Figure 4 are a simplification of the FIR cell shown in Figure 1. For simplicity, the ALU's and FIR Cell Accumulators were replaced by adders, and the pipeline delay registers were omitted. 3-183 0 2 6 7 1 5 4 + C0 X + C1 X + C2 X 3 + C3 X + (X7+X0)C0+(X6+X1)C1+(X5+X2)C2+(X4+X3)C3 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. Example 2. Odd-Tap Symmetric Filter Example B. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE. 1 6 5 + C0 X The HSP43168 HSP43168 may be configured as two independent 7-tap symmetric filters with a functional block diagram resembling Figure 2. As in the 8-tap filter example, the HSP43168 HSP43168 implements the filtering operation by summing data samples sharing a common coefficient prior to multiplication by that coefficient. However, for odd length filters the pre-addition requires that the center coefficient be scaled by 1/2. 4 3 7 8 2 + C1 X + C2 X + C3 The operation of the FIR cell for odd length filters is better understood by comparing the data/coefficient alignment in Figure 5 with the data flow diagrams in Figure 6. The block diagrams in Figure 6 are a simplification of the FIR cell shown in Figure 1. X + (X8+X1)C0+(X7+X2)C1+(X6+X3)C2+(X5+X4)C3 C3 C2 C. DATA FLOW AS DATA SAMPLE 9 IS CLOCKED INTO THE FEED FORWARD STAGE. 2 3 4 8 7 C2 C1 h(n) C1 C0 C0 5 6 x(n) 9 + + + + X9 C0 X C1 X C2 X C3 X X8 X7 X6 X5 X4 X3 X2 X1 X0 FIGURE 5. DATA/COEFFICIENT ALIGNMENT FOR 7-TAP SYMMETRIC FILTER + (X9+X2)C0+(X8+X3)C1+(X7+X4)C2+(X6+X5)C3 FIGURE 4. DATA FLOW DIAGRAMS FOR 8-TAP SYMMETRIC FILTER Using this architecture, only the unique coefficients need to be stored in the Coefficient Bank. For example, the above filter would be stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. For odd length filters, proper data/coefficient alignment is ensured by routing data entering the last register in the third forward decimation stage to the backward shifting registers. In this configuration, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from both the forward and backward shifting registers. A. DATA FLOW AS DATA SAMPLE 6 IS CLOCKED INTO THE FEED FORWARD STAGE. To operate the HSP43168 HSP43168 in this mode, TXFR# is tied low to ensure proper data flow; both FWRD# and RVRS# are tied low to enable data samples from the forward and reverse data paths to the ALU's for pre-adding; ACCEN is tied low to prevent accumulation over multiple CLK's; SHFTEN# is tied low to allow shifting of data through the decimation registers; MUX0-1 is programmed to multiplex the output the of either FIR A or FIR B; CSEL0-4 is pro- grammable to access the stored coefficient set, in this ex- ample CSEL = 0000. 3-184 0 4 3 + C0 X 3 2 5 6 1 + C1 X + + C2 X C3/2 X + (X6+X0)C0+(X5+X1)C1+(X4+X2)C2+(X3+X3)C3/2 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. example, only the unique coefficients need to be stored in the Coefficient Bank. These coefficients are stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. The control signals TXFR#, FWRD#, RVRS#, ACCEN, SHFTEN#, and CSEL0-4 are controlled as described in Example 1. B. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED FORWARD STAGE. 1 7 2 6 + 4 3 5 + 4 + + Example 3. Asymmetric Filter Example C0 X C1 X C2 X C3/2 X The FIR cells within the HSP43168 HSP43168 can each calculate 4 asymmetric taps on each clock. Thus, a single FIR cell can implement an 8-tap asymmetric filter if the HSP43168 HSP43168 is clocked at twice the input data rate. Similarly, if the Dual is configured as a single filter, a 16- tap asymmetric filter is realizable. + (X7+X1)C0+(X6+X2)C1+(X5+X3)C2+(X4+X4)C3/2 For this example, the FIR cells are configured as two 8-tap asymmetric filters which are clocked at twice the input data rate. New data is shifted into the forward and backward decimation paths every other CLK by the assertion of SHFTEN#. The filter output is computed by passing data from each decimation path to the multipliers on alternating clocks. Two sets of coefficients are required, one for data on the forward decimation path, and one for data on the reverse path. The filter output is generated by accumulating the multiplier outputs for two CLKs. C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE. 2 6 5 + C0 X 5 4 7 8 3 + C1 X + + C2 X C3/2 The operation of this configuration is better understood by comparing the data/coefficient alignment in Figure 7 with the data flow diagrams in Figure 8. The ALU's have been omitted from the FIR cell diagrams because data is fed to the multipliers directly from the forward and reverse decimation paths. The data samples within the FIR cell are shown by the numbers in the decimation paths. X + (X8+X2)C0+(X7+X3)C1+(X6+X4)C2+(X5+X5)C3/2 FIGURE 6. DATA FLOW DIAGRAMS FOR 7-TAP SYMMETRIC FILTER. In the data flow diagrams of Figure 6, the order of the data samples input in to the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is given by the equation at the bottom of the block. The diagram in Figure 6a shows data sample alignment at the pre-adders for the data/coefficient alignment shown in Figure 5. This dual filter application is configured by writing 110H to address 000H via the microprocessor interface, CIN0-9, A08, and WR#. Also, data reversal must be disabled by setting bit 4 of the control register at address 0001H 0001H. As in the 8-tap 3-185 C7 C6 C5 C4 C3 h(n) C2 C1 C0 x(n) X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 FIGURE 7. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP ASYMMETRIC FILTER HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. A. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS. 0 2 6 C0 1 5 1 4 C1 X D. SHIFTING OF DATA SAMPLE 8 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS X C2 X 2 3 7 3 6 5 8 C3 C7 X C6 X X C5 X 4 C4 X ACCUMULATOR ACCUMULATOR (X0)C0+(X1)C1+(X2)C2+(X3)C3 (X1)C0+(X2)C1+(X3)C2+(X4)C3 +(X8)C7+(X7)C6+(X6)C5+(X5)C4 B. SHIFTING OF DATA SAMPLE 7 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS. 0 C7 2 6 7 1 5 4 C6 X X C5 X 3 C4 X ACCUMULATOR FIGURE 8. DATA FLOW DIAGRAMS FOR 8-TAP ASYMMETRIC FILTER CONTINUED For this application, each filter cell is configured as an odd length filter by writing 110H to the control register at address 000H. Even though an even tap filter is being implemented, the filter cells must be configured as odd length to ensure proper data flow. Also, the 4th bit at control address 001H must be set to disable data reversal, and TXFR# must be tied low. Since an 8-tap asymmetric filter is being implemented, two sets of coefficients must be stored. These eight coefficients could be loaded into the first two coefficient sets for FIR A by writing C0, C1, C2, C3, C7, C6, C5, and C4 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, and 10bH respectively. The sum of products required for this 8-tap filter require dynamic control over FWRD#, RVRS#, ACCEN, and CSEL0- 4. The relative timing of these signals is shown in Figure 9. (X0)C0+(X1)C1+(X2)C2+(X3)C3 +(X7)C7+(X6)C6+(X5)C5+(X4)C4 0 C. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS. INA0-9 1 X 3 7 C0 2 6 5 C1 X C2 X C3 1 2 3 13 14 15 16 CLK 4 CSEL0-4 X0 1 X6 X1 0 1 0 X7 0 1 X8 0 1 0 ACCEN FWRD# X RVRS# ACCUMULATOR SHFTEN# FIGURE 9. CONTROL TIMING FOR 8-TAP ASYMMETRIC FILTER (X1)C0+(X2)C1+(X3)C2+(X4)C3 3-186 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. Example 4. Even-Tap Decimating Filter Example The HSP43168 HSP43168 supports filtering applications requiring decimation to 16. In these applications the output data rate is reduced by a factor of N. As a result, N clock cycles can be used for the computation of the filter output. For example, each FIR cell can calculate 8 symmetric or 4 asymmetric taps in one clock. If the application requires decimation by two, the filter output can be calculated over two clocks thus boosting the number of taps per FIR cell to 16 symmetric or 8 asymmetric. For this example, each FIR cell is configured as an independent 24-tap decimate x3 filter. The alignment of data relative to the 24 filter coefficients for a particular output is depicted graphically in Figure 10. As in previous examples, the HSP43168 HSP43168 implements the filtering operation by summing data samples prior to multiplication by the common coefficient. In this example an output is required every third CLK which allows 3 CLK's for computation. On each CLK, one of three sets of coefficients are used to calculate 8 of the filter taps. The block diagrams in Figure 12 show the data flow and accumulator output for the data/ coefficient alignment in Figure 10. A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE 2 1 0 17 16 15 14 13 12 + C2 X + C5 h(n) C0 C1 C2 C3 C4 C5 C6 C7 C6 C5 C4 C3 C2 C1 X C11 X B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED FORWARD STAGE 1 0 5 10 9 7 6 11 4 3 8 12 22 18 17 16 21 20 19 X + C4 15 14 13 + C7 X C0 X + C10 X ACCUMULATOR (X1+X22)C1+(X4X19 X4X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 x(n) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 C8 X + (X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 C1 C7 + ACCUMULATOR + C11 C11 C10 C10 C9 C8 C8 C9 11 10 9 8 7 6 20 19 18 21 5 4 3 6 5 4 3 2 1 0 C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 10. DATA/COEFFICIENT ALIGNMENT FOR 24-TAP 24-TAP DECIMATE BY 3 FIR FILTER 0 5 4 9 6 11 10 3 8 7 13 12 Proper data and coefficient alignment is achieved by asserting TXFR# once every three CLK's to switch the LIFO's which are being read and written. This has the effect of feeding blocks of three samples into the backward shifting decimation path which are reversed in sample order. In addition, ACCEN is de-asserted once every three clocks to allow accumulation over three CLK's. The three sets of coefficients required in the calculation of a 24-tap symmetric filter are cycled through using CSEL0-4. The timing relationship between the CSEL0-4, ACCEN, and TXFR# are shown in Figure 12. 3-187 23 + C0 19 18 17 22 21 20 X + C3 X 16 15 14 + C6 X + C9 X ACCUMULATOR (X0+X23)C0+(X3+X20)C3+(X6+X17)C6+(X9+X14)C9 +(X1+X22)C1+(X4+X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. To operate in this mode the Dual is configured by writing 1d2 to address 000H via the microprocessor interface, CIN0-9, A0-8, and WR#. Data reversal must be enabled see (Table 2.0). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing C2, C5, C8, C11, C1, C4, C7, C10, C0, C3, C6, and C9 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, and 113H respectively. As in the 24-tap example, an output is required every third CLK which allows 3 CLK's for computation. On each CLK, one of three sets of coefficients are used to calculate the filter taps. Since this is an odd length filter, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from the forward and backward shifting decimation paths.The block diagrams in Figure 14 show the data flow and accumulator output for the data coefficient alignment in Figure 13. D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED FORWARD STAGE Proper data and coefficient alignment is achieved by asserting TXFR# once every three CLK's to switch the LIFO's which are being read and written. For odd length filters, data prior to the last register in the forward decimation path is routed to the Feedback Circuitry. As a result, TXFR# should be asserted one cycle prior to the input data samples which align with the center tap. The timing relationship between the CSEL0-5, ACCEN, and TXFR# are shown in Figure 15. 5 4 3 8 7 11 10 9 6 14 13 12 24 + C2 20 19 18 23 22 21 X 17 16 15 + C5 + C8 X + C11 X X h(n) ACCUMULATOR C0 C1 C2 C3 C4 C5 C6 C7 C11 C10 C10 C9 C8 C8 C9 C7 C6 C5 C4 C3 C2 C1 C0 (X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11 x(n) FIGURE 11. DATA FLOW DIAGRAMS FOR 24-TAP 24-TAP DECIMATE BY 3 FIR FILTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FIGURE 13. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP 23-TAP DECIMATE BY 3 SYMMETRIC FILTER 0 1 2 3 4 21 5 22 23 A. COMPUTATIONAL FLOW AS DATA SAMPLE 20 IS CLOCKED INTO THE FEED FORWARD STAGE CLK INA0-9 0 1 0 1 2 3 4 5 21 22 23 2 0 1 2 2 1 0 CSEL0-4 2 0 1 19 18 17 20 8 5 4 3 16 15 14 11 10 9 7 6 13 12 11 ACCEN + + + + TXFR# C2 FIGURE 12. CONTROL SIGNAL TIMING FOR 24-TAP 24-TAP DECIMATE X3 FILTER X C5 X C8 X C11/2 C11/2 X ACCUMULATOR Example 5. Odd-Tap Decimating Symmetric Filter This example highlights the use of the HSP43168 HSP43168 as two in dependent, 23-tap, symmetric, decimate by 3 filters. In this example, the operational differences in the control signals and data reversal structure may be compared to the previously discussed even-tap decimating filter. 3-188 (X2+X20)C2+(X5+X17)C5+(X8+X14)C8+(X11+X11)C11/2 C11/2 HSP43168 HSP43168 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied. B. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE 1 0 5 10 9 7 6 11 4 3 8 D. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE 5 4 3 11 10 9 8 7 6 14 13 12 12 21 + C1 17 16 15 21 19 18 X + C4 + C7 X 23 14 13 12 X + C10 + C2 X 19 18 17 22 21 20 X + C5 + X 0 18 17 16 2 3 INA0-9 0 1 2 3 CSEL0-5 9 6 11 10 1 4 5 20 21 22 CLK 13 12 21 20 19 X FIGURE 14. DATA FLOW DIAGRAMS FOR 23-TAP 23-TAP DECIMATE BY 3 SYMMETRIC FILTER C. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED FORWARD STAGE 22 C11/2 C11/2 X (X5+X23)C2+(X8+X20)C5+(X11+X17)C8+(X14+X14)C11/2 C11/2 (X1+X21)C1+(X4X18 X4X18)C4+(X7+X15)C7+(X10+X12)C10 +(X2+X20)C2+(X5+X17)C5+(X8+X14)C8+(X11+X11)C11/2 C11/2 3 8 7 C8 + ACCUMULATOR ACCUMULATOR 0 5 4 16 15 14 1 2 0 1 4 2 5 0 20 21 22 0 1 2 15 14 13 ACCEN + C0 X + C3 X + C6 X + C9 TXFR# X ACCUMULATOR (X0+X22)C0+(X3+X19)C3+(X6+X16)C6+(X9+X13)C9 +(X1+X21)C1+(X4+X18)C4+(X7+X15)C7+(X10+X12)C10 +(X2+X20)C2+(X5+X17)C5+(X8+X14)C8+(X11+X11)C11/2 C11/2 FIGURE 15. CONTROL SIGNAL TIMING FOR 23-TAP 23-TAP SYMMETRIC FILTER To operate in this mode, the Dual is configured by writing 132H to address 000H via the microprocessor interface, CIN0-9, A0-8, and WR#. Data reversal must be enabled (see Table 2.0). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing C2, C5, C8, (C11)/ 2, C1, C4, C7, C10, C0, C3, C6, and C9 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, and 113H respectively. 3-189