ADE-203-053F HN58V257 HN58V257T-35 TFP-32DA HN58V257T HN58V256A HN58V257A - Datasheet Archive

 

HN58V257 Series 32768-word × 8-bit Electrically Erasable and Programmable CMOS ROM Rev. 6.0 May. 25, 1995 The Hitachi

 

ADE-203-053F ADE-203-053F (Z) HN58V257 HN58V257 Series 32768-word × 8-bit Electrically Erasable and Programmable CMOS ROM Rev. 6.0 May. 25, 1995 The Hitachi HN58V257 HN58V257 is a electically erasable and programmable ROM organized as 32768-word × 8-bit. It realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 64-byte page programming function to make its erase and write operations faster. Features · · · · · · · · · · · · · Single 3 V supply On-chip latches: address, data, CE, OE, WE Automatic byte write: 15 ms max Automatic page write (64 bytes): 15 ms max Fast access time: 350 ns max Low power dissipation: 20 mW/MHz typ (active) 110 µW max (standby) Data polling, RDY/Busy Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 years data retention Write protection by RES pin Ordering Information Type no. Access time Package HN58V257T-35 HN58V257T-35 350 ns 32-pin plastic TSOP (TFP-32DA TFP-32DA) HN58V257 HN58V257 Series Pin Arrangement HN58V257T HN58V257T Series A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC CE A10 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) Pin Description Pin name Function A0­A14 Address inputs I/O0­I/O7 Data input/output OE Output enable CE Chip enable WE Write enable VCC Power (+3 V) VSS Ground RES Reset RDY/Busy Ready /Busy 2 A3 A4 A5 A6 A7 A12 A14 RDY/Busy VCC RES WE A13 A8 A9 A11 OE HN58V257 HN58V257 Series Block Diagram I/O0 VCC RDY/Busy I/O7 High Voltage Generator VSS RES I/O Buffer and Input Latch OE CE Control Logic and Timing WE A0 Y Gating Y Decoder A5 Address Buffer and Latch Memory Array X Decoder A6 A14 Data Latch Mode Selection Pin Mode CE (31) OE (1) WE (6) RDY/Busy (9) RES (7) I/O (21-23, 25-29) Read VIL VIL VIH High-Z VH*1 Dout Standby VIH ×*2 × High-Z × High-Z Write VIL VIH VIL High-Z to VOL VH Din Deselect VIL VIH VIH High-Z VH High-Z Write inhibit × × VIH High-Z × - × VIL × Data polling VIL VIL VIH VOL VH Data out (I/O7) Program reset × × × High-Z VIL High-Z Note: 1. Refer to the recommended DC operating condition. 2. × = Don't care 3 HN58V257 HN58V257 Series Absolute Maximum Ratings Parameter Symbol Supply voltage Input voltage V ­0.5*2 V Topr Storage temperature range ­0.6 to +7.0 0 to +70 °C Tstg Operationg temperature range *3 Unit Vin *1 Value VCC *1 ­55 to +125 °C to +7.0 Notes: 1. With respect to VSS 2. Vin min = ­3.0 V for pulse width 50 ns 3. Including electrical characteristics and data retention Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 5.5 V Input voltage VIL ­0.3 - 0.8 V VIH 1.9 - VCC + 0.3 V VH VCC ­ 0.5 - VCC + 1.0 V Topr 0 - 70 °C Operating temperature DC Characteristics (Ta=0 to +70°C, VCC = 2.7 to 5.5V) Parameter Symbol Min Typ Max Unit Test conditions µA VCC = 5.5 V, Vin = 5.5 V Input leakage current ILI - - 2*1 Output leakage current ILO - - 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V VCC current (standby) ICC1 - - 20 µA CE = VCC ICC2 - - 1 mA CE = VIH ICC3 - - 8 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs at VCC = 3.6 V - - 20 mA Iout = 0 mA, Duty = 100%, Cycle = 350 ns at VCC = 3.6 V VCC current (active) Input low voltage VIL ­0.3*2 - 0.8 V Input high voltage VIH 1.9*3 - VCC + 0.3 V VH VCC­0.5 - VCC + 1.0 V Output low voltage VOL - - 0.4 V IOL = 2.1 mA Output high voltage VOH VCC × 0.8 - - V IOH = ­400 µA Note: 4 1. 2. 3. ILI on RES = 100 µA max VIL min = ­1.0 V for pulse width 50 ns VIH min = 2.2 V for VCC = 3.6 to 5.5 V. HN58V257 HN58V257 Series Capacitance (Ta = 25°C, f = 1 MHz) Parameter Input Symbol Min Typ Max Unit Test condition Cin - - 6 pF Vin = 0 V Cout capacitance*1 - - 12 pF Vout = 0 V Output capacitance*1 Note: 1. This parameter is periodically sampled and not 100% tested. AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5V) Test Conditions · Input pulse levels : 0.4 V to 2.4 V 0 V to VCC (RES pin) · Input rise and fall time : 20 ns · Output load : 1TTL Gate +100 pF · Reference levels for measuring timing : 0.8 V, 1.8 V Read Cycle Parameter Symbol Min Max Unit Test conditions Address to output delay tACC - 350 ns CE = OE = VIL, WE = VIH CE to output delay tCE - 350 ns OE = VIL, WE = VIH tOE 10 150 ns CE = VIL, WE = VIH tDF 0 90 ns CE = VIL, WE = VIH tDFR 0 350 ns CE = OE = VIL, WE = VIH Data output hold tOH 0 - ns CE = OE = VIL, WE = VIH RES to output delay tRR 0 600 ns CE = OE = VIL, WE = VIH OE to output delay OE (CE) high to output RES low to output Note: float*1 float*1 1. tDF, tDFR are defined at which the outputs achieve the open circuit conditions and are no longer driven. 5 HN58V257 HN58V257 Series Read Timing Waveform Address t ACC CE tOH tCE OE tOE WE tDF High Data Out Data Out Valid t RR RES 6 t DFR HN58V257 HN58V257 Series Write Cycle Parameter Symbol Min*1 Typ Max Unit Address setup time tAS 0 - - ns Address hold time tAH 200 - - ns CE write setup time (WE controlled) tCS 0 - - ns CE hold time (WE controlled) tCH 0 - - ns WE to write setup time (CE controlled) tWS 0 - - ns WE hold time (CE controlled) tWH 0 - - ns OE to write setup time tOES 0 - - ns OE hold time tOEH 0 - - ns Data setup time tDS 150 - - ns Data hold time tDH 0 - - ns WE pulse width (WE controlled) tWP 250 - - ns CE pulse width (CE controlled) tCW 250 - - ns Data latch time tDL 300 - - ns Byte load cycle tBLC 0.55 - 30 µs Byte load window tBL 100 - - µs Write cycle time tWC - - 15*2 ms Time to device busy tDB 120 - - ns Write start time tDW 250*3 - - ns Reset protect time tRP 100 - - µs Reset low time tRES 1 - - Test conditions µs Note: 1. Use this device in longer cycle than this value. 2. tWC must be longer than this value unless polling technique or RDY/Busy are used. This device automatically completes the internal write operation within this value. 3. Next read or write operation can be initiated after tDW if polling technique or RDY/Busy are used. 7 HN58V257 HN58V257 Series Byte Write Timing Waveform(1) (WE Controlled) t WC Address t CS t AH t CH CE t AS t BL t WP WE t OES t OEH OE t DS t DH Din t DW High-Z RDY/Busy tRP tRES RES V CC 8 t DB High-Z HN58V257 HN58V257 Series Byte Write Timing Waveform(2) (CE Controlled) Address t WS t AH t BL t WC t CW CE t WH t AS WE t OES t OEH OE t DS t DH Din t DW RDY/Busy t DB High-Z High-Z t RP t RES RES V CC 9 HN58V257 HN58V257 Series Page Write Timing Waveform(1) (WE Controlled) Address A6 to A14 Address A0 to A5 t AS WE t AH t BLC t WP t BL t DL t CS t WC t CH CE t OEH t OES OE t DS Din t DH RDY/Busy High-Z t RP RES t RES VCC 10 t DB t DW High-Z HN58V257 HN58V257 Series Page Write Timing Waveform(2) (CE Controlled) Address A6 to A14 Address A0 to A5 t AS CE t AH t BLC t CW t BL t DL t WS t WC t WH WE t OEH t OES OE t DS Din t DH RDY/Busy High-Z t DB t DW High-Z t RP RES t RES VCC 11 HN58V257 HN58V257 Series Data Polling Timing Waveform Address An An An CE t CE WE t OES t BL OE t DW t OE I/O7 Din X Dout X Dout X t WC 12 HN58V257 HN58V257 Series Functional Description WE, CE Pin Operation Automatic Page Write During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. The endurance is 105 cycles in case of the page programming and 10 4 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Polling Data Protection polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. 1.Data Protection against Noise on Control Pins (CE, OE, WE) during Operation Data RDY/Busy Signal RDY/ Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal Write/Erase Endurance and Data Retention Time During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE 3V 0V When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function. 3V OE VCC Read inhibit 0V Read inhibit 20 ns max RES Program inhibit Program inhibit 13 HN58V257 HN58V257 Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may turn the EEPROM to programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in unprogrammable state by using a CPU reset signal to RES pin. RES pin should be kept at VSS level when VCC is turned on or off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 15 ms after the last data input. VCC RES Program inhibit WE or CE 14 1 µs min 100 µs min Program inhibit 15 ms min HN58V257 HN58V257 Series Package Dimensions HN58V257T HN58V257T Series (TFP-32DA TFP-32DA) Unit : mm 8.0 8.2 Max 17 1 16 12.4 32 0.50 0.08 M 0.10 0­5° 0.08 Min 0.18 Max 1.2 Max 0.45 Max 0.17 ± 0.05 0.20 ± 0.10 0.5 ± 0.1 14.0 ± 0.2 15 HN58V256A HN58V256A Series HN58V257A HN58V257A Series Preliminary 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM Rev. 0.0 Mar. 15, 1995 The Hitachi HN58V256A HN58V256A and HN58V257A HN58V257A are a electrically erasable and programmable EEPROM's organized as 32768-word × 8-bit. Employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features · · · · · · · · · · · · · · · Single 2.7 to 5.5 V supply On-chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms max Automatic page write (64 bytes): 10 ms max Fast access time: 120 ns max Low power dissipation: 20 mW/MHz, typ (active) 110 µW max (standby) Ready/Busy ()*1 Data polling and Toggle bit Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105erase/write cycles (in page mode) 10 years data retention Software data protection Write protection by RES pin ()*1 Notes: 1. All through this datasheet, the mark () indicates the function supported by only the HN58V257A HN58V257A series (32 pin package). Preliminary: This document contains information on a new product. Specifiactions and information contained herein are subject to chang without notice. ADE-203-357 ADE-203-357(Z) HN58V256A HN58V256A, HN58V257A HN58V257A Series Ordering Information Operating Temperature Access Compatible Type No. Voltage Range Time Package Type No.*1 -­ HN58V256AP-12/-15 HN58V256AP-12/-15 2.7 to 5.5 V 0 to 70°C 120/150 ns 600 mil 28-pin HN58C256P-20 HN58C256P-20 plastic DIP(DP-28 DP-28) -­ HN58V256AFP-12/-15 HN58V256AFP-12/-15 2.7 to 5.5V 0 to 70°C 120/150 ns 400 mil 28-pin HN58C256FP-20 HN58C256FP-20 -­ plastic SOP - HN58V256AFPI-12/-15 HN58V256AFPI-12/-15 2.7 to 5.5 V ­40 to 85°C (FP-28D FP-28D) HN58C256FPI-20 HN58C256FPI-20 -­ HN58V256AT-12/-15 HN58V256AT-12/-15 2.7 to 5.5 V 0 to 70°C 120/150 ns 28-pin -­ plastic HN58V256AT-12SR HN58V256AT-12SR 2.7 to 5.5 V ­20 to 85°C TSOP /-15SR /-15SR (-)*2 -­ HN58V257AT-12/-15 HN58V257AT-12/-15 2.7 to 5.5 V 0 to 70°C 120/150 ns 8 × 14 mm 32-pin HN58C257T-20 HN58C257T-20 plastic TSOP HN58V257T-35 HN58V257T-35 -­ (TFP-32DA TFP-32DA) - HN58V257AT-12SR HN58V257AT-12SR 2.7 to 5.5 V ­20 to 85°C HN58C257T-20SR HN58C257T-20SR /-15SR /-15SR HN58V257T-35SR HN58V257T-35SR -­ Notes: 1. This type No. can be replaced by the corresponding A­version. (ex. HN58C256P HN58C256P to HN58V256AP HN58V256AP) 2. Package type and dimension are under development. 2 HN58V256A HN58V256A, HN58V257A HN58V257A Series Pin Arrangement HN58V256AP/AFP HN58V256AP/AFP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 · HN58V256AT HN58V256AT Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE (Top View) (Top View) · HN58V257AT HN58V257AT Series A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC CE A10 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A4 A5 A6 A7 A12 A14 RDY/Busy VCC RES WE A13 A8 A9 A11 OE (Top View) Pin Description Pin name Function -­ A0 to A14 Address -­ I/O0 to I/O7 Input/output - OE Output enable -­ CE Chip enable -­ Pin name Function -­ WE Write enable -­ VCC Power (+2.7 ~ 5.5 V) -­ VSS Ground -­ RDY/Busy () Ready busy -­ RES () Reset -­ 3 HN58V256A HN58V256A, HN58V257A HN58V257A Series Block Diagram VCC VSS I/O0 () RES RDY/Busy () I/O Buffer and Input Latch OE CE I/O7 High Voltage Generator Control Logic and Timing WE () RES A0 Y Decoder Y Gating A5 Address Buffer and Latch X Decoder Memory Array A6 A14 Data Latch Mode Selection Pin Mode CE OE WE RES () RDY/Busy () I/O -­ Read VIL VIL VIH VH*1 High-Z Dout -­ Standby VIH ×*2 × × High-Z High-Z -­ Write VIL VIH VIL VH High-Z to VOL Din -­ Deselect VIL VIH VIH VH High-Z High-Z -­ Write Inhibit × × VIH × - - -­ × VIL × × - - -­ Data Polling VIL VIL VIH VH VOL Data out (I/O7) -­ Program reset × × × VIL High-Z High-Z -­ Note: 1. Refer to the recommended DC operating condition. 2. × : Don't care 4 HN58V256A HN58V256A, HN58V257A HN58V257A Series Absolute Maximum Ratings Device Parameter Symbol Value Unit Group*4 -­ Supply voltage *1 VCC ­0.6 to +7.0 V A, B, C -­ Input voltage *1 Vin ­0.5*2 to +7.0 V A, B, C -­ Operating temperature range *3 Topr 0 to +70 °C A - ­20 to 85 °C B - ­40 to 85 °C C -­ Storage temperature range Tstg ­55 to +125 °C A, B, C -­ Recommended DC Operating Conditions Device Parameter Symbol Min Typ Max Unit Group*4 -­ Supply voltage VCC 2.7 3.0 5.5 V A, B, C -­ Input voltage VIL ­0.3*5 - 0.6 V A, B, C - VIH 2.4*6 - VCC + 0.3*7 V A, B, C - VH() VCC ­ 0.5 - VCC + 1.0 V A, B, C -­ Operating temperature Topr 0 - 70 °C A -­ ­20 - 85 °C B -­ ­40 - 85 °C C -­ Notes: 1. With respect to VSS. 2. Vin min : ­3.0 V for pulse width < 50 ns. 3. Including electrical characteristics and data retention. 4. Group A includes HN58V256AP/AFP HN58V256AP/AFP, HN58V257AT HN58V257AT and HN58V256AT HN58V256AT. Group B includes HN58V256AT-SR HN58V256AT-SR and HN58V257AT-SR HN58V257AT-SR. Group C includes HN58V256AFPI HN58V256AFPI. 5. VIL min: ­1.0 V for pulse width 50 ns. 6. VIH min for VCC = 3.6 to 5.5 V is 3.0 V. 7. VIH max: VCC + 1.0 V for pulse width 50 ns. 5 HN58V256A HN58V256A, HN58V257A HN58V257A Series DC Characteristics Supply voltage range (VCC), temperature range (Topr) and input voltage (VIH/VIL/VH) are referred to the table of Recommended DC Operating Conditions. Parameter Symbol Min Typ Max Unit Test conditions -­ Input leakage current ILI - - 2*1 µA VCC = 5.5 V, Vin = 5.5 V -­ Output leakage current ILO - - 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V -­ VCC current (standby) ICC1 - - 20 µA CE = VCC -­ ICC2 - - 1 mA CE = VIH -­ VCC current (active) ICC3 - - 8 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs at VCC = 3.6 V -­ - - 12 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs at VCC = 5.5 V -­ - - 20 mA Iout = 0 mA, Duty = 100%, Cycle = 120 ns at VCC = 3.6 V -­ - - 30 mA Iout = 0 mA, Duty = 100%, Cycle = 120 ns at VCC = 5.5 V -­ Output low voltage VOL - - 0.4 V IOL = 2.1 mA -­ Output high voltage VOH VCC × 0.8 - - V IOH = ­400 µA -­ Note: 1. ILI on RES : 100 µA max () Capacitance (Ta = 25°C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test condition -­ Input capacitance Cin*1 - - 6 pF Vin = 0 V -­ Output capacitance Cout*1 - - 12 pF Vout = 0 V -­ Note: 1. This parameter is periodically sampled and not 100% tested. 6 HN58V256A HN58V256A, HN58V257A HN58V257A Series AC Characteristics Supply voltage (VCC) and temperature range (Topr) are referred to the table of 'Recommended DC Operating Conditions'. Test Conditions · Input pulse levels : 0 V to 3.0 V 0 V to VCC (RES pin) · Input rise and fall time : < 20 ns · Input timing reference levels : 0.8, 1.8 V · Output load : 1TTL Gate +100 pF · Output reference levels : 1.5 V, 1.5 V Read Cycle -12 -15 -­ -­ Parameter Symbol Min Max Min Max Unit Test conditions -­ Address to output delay tACC - 120 - 150 ns CE = OE = VIL, WE = VIH -­ CE to output delay tCE - 120 - 150 ns OE = VIL, WE = VIH -­ OE to output delay tOE 10 60 10 60 ns CE = VIL, WE = VIH -­ Address to output hold tOH 0 - 0 - ns CE = OE = VIL, WE = VIH -­ OE (CE) high to output float*1 tDF 0 40 0 40 ns CE = VIL, WE = VIH -­ RES low to output float*1() tDFR 0 350 0 350 ns CE = OE = VIL, WE = VIH -­ RES to output delay() tRR 0 600 0 600 ns CE = OE= VIL, WE = VIH -­ Note: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 7 HN58V256A HN58V256A, HN58V257A HN58V257A Series Read Timing Waveform Address t ACC CE tOH tCE OE tOE WE tDF High Data Out Data Out Valid t RR RES () t DFR 8 HN58V256A HN58V256A, HN58V257A HN58V257A Series Write Cycle Test Parameter Symbol Min*1 Typ Max Unit conditions -­ Address setup time tAS 0 - - ns -­ Address hold time tAH 50 - - ns -­ CE to write setup time (WE controlled) tCS 0 - - ns -­ CE hold time (WE controlled) tCH 0 - - ns -­ WE to write setup time (CE controlled) tWS 0 - - ns -­ WE hold time (CE controlled) tWH 0 - - ns -­ OE to write setup time tOES 0 - - ns -­ OE hold time tOEH 0 - - ns -­ Data setup time tDS 50 - - ns -­ Data hold time tDH 0 - - ns -­ WE pulse width (WE controlled) tWP 200 - - ns -­ CE pulse width (CE controlled) tCW 200 - - ns -­ Data latch time tDL 100 - - ns -­ Byte load cycle tBLC 0.3 - 30 µs -­ Byte load window tBL 100 - - µs -­ Write cycle time tWC - - 10*2 ms -­ Time to device busy tDB 120 - - ns -­ Write start time tDW 0*3 - - ns -­ Reset protect time () tRP 100 - - µs -­ Reset high time () tRES 1 - - µs -­ Note: 1. Use this device in longer cycle than this value. 2. tWC must be longer than this value unless polling techniques or RDY/Busy () are used. This device automatically completes the internal write operation within this value. 3. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy () are used. 9 HN58V256A HN58V256A, HN58V257A HN58V257A Series Byte Write Timing Waveform(1) (WE Controlled) t WC Address t CS t AH t CH CE t AS t BL t WP WE t OES t OEH OE t DS t DH Din t DW High-Z RDY/Busy () t DB High-Z tRP tRES RES () V CC 10 HN58V256A HN58V256A, HN58V257A HN58V257A Series Byte Write Timing Waveform(2) (CE Controlled) Address t WS t AH t BL t WC t CW CE t WH t AS WE t OES t OEH OE t DS t DH Din t DW RDY/Busy () t DB High-Z High-Z t RP t RES RES () V CC 11 HN58V256A HN58V256A, HN58V257A HN58V257A Series Page Write Timing Waveform(1) (WE Controlled) *1 Address A0 to A14 t AS WE t AH t BL t WP t DL t CS t BLC t WC t CH CE t OEH t OES OE t DH t DS Din t DW RDY/Busy () High-Z t DB High-Z t RP RES () t RES VCC Note: 1. A6 through A14 are page addresses and these address are latched at the first falling edge of WE. 12 HN58V256A HN58V256A, HN58V257A HN58V257A Series Page Write Timing Waveform(2) (CE Controlled) *1 Address A0 to A14 t AS CE t AH t BL t CW t DL t WS t BLC t WC t WH WE t OEH t OES OE t DH t DS Din t DW RDY/Busy () High-Z t DB High-Z t RP RES () t RES VCC Note: 1. A6 through A14 are page addresses are these address are latched at the first falling edge of CE. 13 HN58V256A HN58V256A, HN58V257A HN58V257A Series Data Polling Timing Wavefome Address An An An CE t CE*1 WE t OES t OEH OE *1 t OE Dout X Din X I/O7 t DW Dout X t WC Note: 1. See AC read characteristics. Toggle bit cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming Toggle bit Wavefome Next mode Address t CE *1 CE WE *1 t OE OE t OEH t OES *1 I/O6 Din Dout *2 Dout Dout t WC *2 Dout t DW Note: 1. I/O6 beginning state is "1". 2. I/O6 ending state will vary. 3. See AC read characteristics. 14 HN58V256A HN58V256A, HN58V257A HN58V257A Series Software Data Protection Timing Waveform(1) (in protection mode) VCC CE WE tBLC Address Data 5555 AA 2AAA 55 5555 A0 tWC Write Address Write Data Software Data Protection Timing Waveform(2) (in non-protection mode) VCC tWC Normal active mode CE WE Address Data 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20 15 HN58V256A HN58V256A, HN58V257A HN58V257A Series Functional Description WE , CE Pin Operation Automatic Page Write During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Polling Data Protection polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation Data RDY/Busy Signal () RDY/ B u s y signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in programming mode. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE RES Signal () VIH 0V When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when V CC is switched. RES should be high during read and programming because it doesn't provide a latch function. VIH OE VCC Read inhibit 0V Read inhibit RES 20 ns max Program inhibit Program inhibit 16 HN58V256A HN58V256A, HN58V257A HN58V257A Series 2. Data protection at VCC on/off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. VCC RES Program inhibit WE or CE 1 µs min 100 µs min Program inhibit 10 ms min 3. Software data protection VCC CPU RESET * Unprogrammable * Unprogrammable *The EEPROM should be kept in unprogrammable state during V CC on/off by using CPU RESET signal. (1)Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below. -­- CE VCC × × -­- OE × VSS × -­- WE × × VCC -­- ×: Don't care. VCC: Pull-up to VCC level. VSS: Pull-down to VSS level. (2) Protection by RES () The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept V SS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input. To prevent unintentional programming caused by noise generated by external circuits, This device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode. Address Data 5555 AA 2AAA 55 5555 A0 Write address Write data } Normal data input Software data protection mode can be canceled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the canceling cycle, the data cannot be written. Address Data 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20 The software data protection is not enabled at the shipment. 17 HN58V256A HN58V256A, HN58V257A HN58V257A Series Package Dimensions HN58V256AP HN58V256AP Series (DP-28 DP-28) Unit : mm 35.6 36.5 Max 15 13.4 14.6 Max 28 1 14 1.2 15.24 0.51 Min 2.54 ± 0.25 2.54 Min 5.7 Max 1.9 Max 0.48 ± 0.10 + 0.11 0.25 ­ 0.05 0° ­ 15° HN58V256AFP HN58V256AFP Series (FP-28D FP-28D) Unit : mm 18.3 18.75 Max 15 2.5 Max 14 0.895 0.17 ­ 0.07 1 + 0.08 8.4 28 11.8 ± 0.3 + 0.10 0.40 ­ 0.05 0.1 Min 0 ­ 10 ° 1.27 ± 0.10 1.0 18 HN58V256A HN58V256A, HN58V257A HN58V257A Series Package Dimensions HN58V257AT HN58V257AT Series (TFP-32DA TFP-32DA) Unit : mm 8.0 8.2 Max 17 1 16 12.4 32 0.50 0.08 M 0.10 0­5° 0.08 Min 0.18 Max 1.2 Max 0.45 Max 0.17 ± 0.05 0.20 ± 0.10 0.5 ± 0.1 14.0 ± 0.2 HN58V256AT HN58V256AT Series ( - ) Unit : mm (To be determined) 19