HMC-C070 - Datasheet Archive

 

MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Applicable Products: HMC-C070 General Description This operating

 

v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Applicable Products: HMC-C070 HMC-C070 General Description This operating guide applies to the family of MicroSynthTM synthesizer modules operating up to 20 GHz output frequency. The purpose of this guide is to describe features common to all of the synthesizer modules. The MicroSynthTM modules contain phase locked loops consisting of various Hittite die. Additionally, the voltage inputs are internally regulated with low dropout linear voltage regulators that can each handle a maximum input voltage of 20V, provided the module has adequate heatsinking. OPERATING GUIDE A A-2 Each of the MicroSynthTM modules features frequency hopping and frequency sweep functions. The built-in linear sweeper function performs frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external, automatic or software driven sweep trigger. The external trigger signal is sent to the module via the GPIO3 pin. Functional Diagram For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Pin Descriptions Function Description 1-3 GPIO1, GPIO2, GPIO3 General Purpose I/O with Tristate 4 SEN Serial port Enable Input 5 SDI Serial port Data input 6 SCK Serial port Clock input 7 LD Lock Detect 8, 12, 14 Vd3, Vd2, Vd1 Voltage Supply Pins 9, 13 GND Ground 10, 11 N/C No connection 15 REFIN AC coupled reference input, SMA field replaceable. 16 RFOUT Interface Schematic AC coupled signal output, SMA field replaceable Reference Input The crystal reference input stage is shown in Figure 1. This is a common emitter single ended bipolar buffer. Expected input is a 0 dBm sinusoid from a 50 Ohm source. The buffer input impedance is dominated by a 25 Ohm shunt resistor in series with a 50 pF on chip cap. The reference path phase noise floor is approximately equivalent to -159 dBc/Hz. For best performance care should be taken to provide a crystal reference source with equivalent or better phase noise floor. 11 OPERATING GUIDE Pin Number Figure 1. REFIN Sine Input For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A-3 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE BASIC OPERATION Frequency Tuning The frequency of the synthesizer is given by: f VCO = fREF · Nint · M + fREF · Nfrac · M (EQ 1) 224 Where: Nint Nfrac OPERATING GUIDE is the functional division ratio between 0 and 224-1 fREF A is the integer division ratio, between 36 and 65531 in fractional mode between 32 and 65535 in integer mode is the frequency of the reference M is the prescaler coefficient for the particular synthesizer As an example, for a synthesizer with M = 2 and fREF = 10 MHz, the output frequency of 4,600,000,001.19 Hz is achieved using Nint and Nfrac = 1. These are set by programming the 16-bit binary value of 230d =00E6h = 0000 0000 1110 0110 into dsm_intg in (RegOFh Table 18). Similarly the 24 bit binary value of 1d = 000001h = 0000 0000 0000 0000 0000 0001 into dsm_frac in (Reg10h Table 19). In integer mode the synthesizer step size is fixed to M times the reference frequency, fREF. Integer mode typically has lower phase noise for a given reference frequency than fractional mode. In integer mode the digital modulator is normally shut off. To run in integer mode set dsm_integer_mode (Reg12h Table 21) and clear dsm_rstb (Reg01h Table 4). Then program the integer portion of the frequency, Nint, as explained by (EQ 1), ignoring the fractional part. From the above example, operation in integer mode would result in a frequency of 4600 MHz. Frequency Hopping If the synthesizer is in fractional mode, a write to the fractional frequency register, (Reg10h Table 19), will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 5). If the integer frequency register, (Reg0Fh Table 26), is written when in fractional mode, the information will be buffered and only executed when the fractional frequency register is written. If the synthesizer is in integer mode, a write to the integer frequency register, (Reg0Fh Table 26), will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 5). A-4 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE CW Sweeper Mode The internal PLL features a built in frequency sweeper function. This function supports external or automatic triggered sweeps. Sweeper Modes include: a. 2-Way Sweep Mode: alternating positive and negative frequency ramps. b. 1-Way Sweep Mode c. Single Step Ramp Mode Applications include test instrumentation, FMCW sensors, automotive radars and others. The parameters of the sweep function are illustrated in Figure 2. The sweep generator is enabled with ramp_enable in (Reg14h Table 22). The sweep function cycles through a series of discrete frequency values, which may be: a. Stepped by an automatic sequencer, or 11 Triggering of each sweep, or step, may be configured to operate: a. Via a serial port write to Reg14h ramp_trigg (if Reg 14h = 0 ) b. Automatically generated internal trigger c. Triggered via TTL input on GPIO3, and Reg14h = 1. Sweep parameters are set as follows: Initial Frequency, fo = Current frequency value of the synthesizer. Final Frequency, ff = Frequency of the synthesizer at the end of the ramp The frequency step size while ramping is controlled by rampstep, (Reg15h Table 23). Frequency Step Size fstep = rampstep · fREF / 2 24 Clearing or setting ramp_startdir_dn, (Reg14h Table 22), sets the initial ramp direction to be increasing or decreasing in frequency respectively. Setting ramp_singledir (Reg14h Table 22), restricts the direction of the sweep to the initial sweep direction only. OPERATING GUIDE b. Single stepped by individual triggers in Single Step Mode. The sweeper timebase Tref is the period of the divided reference, fPFD, at the phase detector The total number of ramp steps taken in a single sweep is given by ramp_steps_number in Reg16h Table 24. The total time to ramp from fo to ff is given by Tramp = Tref · ramp_steps_number The final ramp frequency, ff, is given by ff = fo + fstep · ramp_steps_number Sweeper action at the end of sweep depends upon the mode of the sweep: a. with both ramp_singledir and ramp_repeat_en (Reg14h Table 22) disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. The next trigger will reverse the current sequence, starting from ff, and stepping back to fo. Odd triggers will ramp in the same direction as the initial ramp, even triggers will ramp in the opposite direction. b. with ramp_singledir enabled and ramp_repeat_en disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. The second trigger will hop the synthesizer back to the initial frequency, fo. The third trigger will restart the sweep from fo. Hence all odd numbered triggers will start a new ramp in the same direction as the initial ramp, even numbered triggers will hop the synthesizer from the current frequency to fo, where it will wait for a trigger to start a sweep. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A-5 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Ramp Busy In all types of sweeps ramp_busy will indicate an active sweep and will stay high between the 1st and nth ramp step. ramp_busy may be monitored one of two ways. ramp_busy is readable via read only register (Reg1Fh Table 33). ramp_busy may also be monitored on GPIO2, hardware pin 2, by setting (Reg1Bh =8h Table 29). Autosweep Mode The Autosweep mode is similar to Figure 2 except that once started, triggers are not required. Once enabled, (ramp_ repeat_en=1 Reg14h Table 22) the Autosweep mode initiates the first trigger, steps n times, one step per ref clock cycle, and then waits for the programmed dwell period and automatically triggers the ramp in the opposite direction. The sweep process continues alternating sweep directions until disabled. ramp_dwell_time (Reg17h Table 25) controls the number of Tref periods to wait at the end of the ramp before automatically retriggering a new sweep. A 2-Way Sweeps OPERATING GUIDE If ramp_repeat_en (Reg14h Table 22) is cleared, then the ramps are triggered by: a. writing to ramp_trigg (Reg14h Table 22), if bit = 0, or b. by rising edge TTL signal input on GPIO3, if ramp_trig_ext_en is set, and GPIO3 is enabled. All functions are the same in Figure 2 for Autosweep or 2-Way Triggered sweeps, the only difference is the trigger source is generated internally for autosweep, and is input via serial port or GPIO3 for triggered sweeps. Sweep_busy will go high at the start of every ramp and stay high until the nth step in the ramp. Figure 2. 2-Way Sweep Control via Trigger A-6 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Triggered 1-Way Sweeps 1-Way sweeps are shown in Figure 3. Unlike 2-Way sweeps, 1-Way sweeps require that the VCO hop back to the start frequency after the dwell period. Triggered 1-Way sweeps also require a 3rd trigger to start the new sweep. The 3rd trigger must be timed appropriately to allow the VCO to settle after the large frequency hop back to the start frequency. Subsequent odd numbered triggers will start the 1-Way sweep and repeat the process. Figure 3. 1-Way Sweep Control For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com OPERATING GUIDE 11 A-7 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Single Step Ramp Mode A Single Step 1-Way Ramp is shown in Figure 4. In this mode, a trigger is required for each step of the ramp. Single step will function in either 1-Way or 2-Way ramps. Similar to autosweep, the ramp_busy flag will go high on the first trigger, and will stay high until the nth trigger. The n+1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. The n+2 trigger will restart the 1-way ramp. OPERATING GUIDE A Figure 4. Single Step Ramp Mode The user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. If the loop bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a staircase shape. As the update rate approaches the loop bandwidth, then the loop will not fully settle before a new frequency step is received. Hence the swept output will have a small lag and will sweep in a near continuous fashion. Charge Pump The up and down charge pumps of the synthesizer can each be adjusted to trade between fractional mode spurious levels and phase noise performance. Optimal values will vary across frequency and are best determined empirically for a particular application. Charge Pump Gain Up and down charge pump gains are set by cp_UPcurrent_sel and cp_DNcurrent_sel respectively (Reg07 Table 10). Normally the registers are set to the same value. Each of the UP and DN charge pumps consist of 5-bit charge pumps with lsb of 125 A. The current gain of the pump, in Amps/radian, is equal to the gain setting of this register divided by 2. For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to '01000' h the output current of each pump will be 1mA and the gain Kp = 1mA/2 radians, or 159 uA/rad. Charge Pump Gain Trim In most applications Gain Trim is not used. However it is available for special applications. Each of the UP and DN pumps may be trimmed separately to more precise values to improve current source matching of the UP and DN values, or to allow finer control of pump gain. A-8 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Charge Pump Gain Trim (Continued) The pump trim controls are 3-bits, binary weighted for UP and DN, in cp_UPtrim_sel and cp_DNtrim_sel respectively (Reg 08h Table 11). LSB weight is 14.7 uA, 000h = 0 trim, 001h = 14.7 ua added trim, 111h = 100uA. Charge Pump Phase Offset Phase noise in fractional mode is strongly affected by charge pump offset. Either of the UP or DN charge pumps may have a DC leakage or "offset" added. The leakage forces the phase detector to operate with a phase offset between the reference and the divided VCO inputs. It is recommended to operate with a phase offset when using fractional mode to reduce non-linear effects from the UP and DN pump mismatch. DC leakage or "offset" may be added to the UP or DN pumps using cp_UPoffset_sel and cp_DNoffset_sel (Reg08 Table 11). These are 4 bit registers with 28.7uA LSB. Maximum offset is 430uA. Charge Pump Operation Near the Minimum and Maximum Output Frequency It should be noted that the charge pump is a non-ideal device. Operation of the module tuned to values near the minimum or maximum output frequency results in degradation of the phase noise performance. When operating near the minimum or maximum frequencies, it is recommended to operate the MicroSynthTM module with a DC leakage that mirrors the direction of frequency offset from center frequency. For example, if the particular MicroSynthTM module operates from 5 GHz to 10 GHz , with a center frequency of 7.5 GHz, and the desired frequency of operation is 5.5 GHz, it is recommended to operate with a DC leakage in the down direction. The converse is also true. If operating the module near its maximum frequency, then a DC leakage in the UP direction is recommended. The appropriate leakage value is application dependent and it is left to the user to determine the appropriate setting based on the particular application requirements. Power On Reset (POR) Normally all logic cells in the internal PLL are reset when the device digital power supply, Vd1, is applied. This is referred to as Power On Reset, or just POR. POR normally takes about 500us after the Vd1 supply exceeds 1.5V, guaranteed to be reset in 1msec. Once the Vd1 supply exceeds 1.5V, the POR will not reset the digital again unless the supply drops below 100mV. 11 OPERATING GUIDE As an example, if the main pump gain was set at 1mA, an offset of 373uA would represent a phase offset of about (392/1000)*360 = 133degrees. Soft Reset The SPI registers may also be soft reset by an SPI write to strobe global_swrst_regs (Reg00h Table 3). All other digital, including the fractional modulator, may be reset with an SPI write to strobe global_swrst_dig (Reg00h Table 3). Power Down The internal PLL chip may be powered down by writing a zero to Reg01h Table 4. In power down state, VD1 will draw less than 1mA. Note that a signal will still be present at the output (frequency may be anywhere in the VCO time range) It should be noted that Reg01h is the Enable and Reset Register which controls 16 separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the functions may be enabled when in operation. Hence power up of the chip requires a selective write to Reg01 bits. An easy way to return the chip to its prior state after a power down is to first read Reg01h and save the state, then write a zero to Reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A-9 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE SERIAL PORT Typical serial port operation can be run with SCLK at speeds up to 50MHz. Serial Port WRITE Operation Table 1. Timing Characteristics Parameter Conditions Min Typ Max Units t1 SEN to SCLK Setup Time 8 nsec t2 SDI to SCLK Setup Time 10 nsec t3 SDI to SCLK Setup Time 10 nsec t4 SCLK High Duration 8 nsec nsec t5 OPERATING GUIDE A SCLK Low Duration 8 t6 SEN High Duration 640 nsec t7 SEN Low Duration 20 nsec A typical WRITE cycle is shown in Figure 5. a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle, followed by a rising edge of SCLK. b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI low initiates the Write cycle (/WR). c. Host places the six address bits on the next six falling edges of SCLK, MSB first. d. Slave reads the address bits in the next six rising edges of SCLK (2-7). e. Host places the 24 data bits on the next 24 falling edges of SCLK, MSB first . f. Slave reads the data bits on the next 24 rising edges of SCLK (8-31). g. SEN is de-asserted on the 32nd falling edge of SLCK. h. The 32nd falling edge of SLCK completes the cycle. Figure 5. Serial Port Timing Diagram - Write Serial Port WRITE Operation A - 10 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Main Serial Port READ Operation The synthesizer uses the multi-purpose pin, LD, for both Lock Detect and Serial Data Out (SDO) functions. The registers lkd_to_sdo_automux_en (Reg1A) and lkd_to_sdo_always (Reg1A Table 28) determine how the Data Output pin is muxed with the Lock Detect function. If both of the registers are cleared, then the pin is exclusively SDO. If automux is enabled, the pin switches to SDO when the RD function is sensed on the 1st rising edge of SCLK. If lkd_to_sdo_always is set, then the pin LD is dedicated for Lock Detect only, and it is not possible to read from the synthesizer. A typical READ cycle is shown in Figure 6. a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed by a rising edge SCLK b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI high initiates the READ cycle (RD) c. Host places the six address bits on the next six falling edges of SCLK, MSB first. 11 e. Slave places the 24 data bits on the next 24 rising edges of SCK (8-31), MSB first . f. Host reads the data bits on the next 24 falling edges of SCK (8-31). g. SEN is de-asserted on the 32nd falling edge of SCLK. h. The 32nd falling edge of SCLK completes the cycle OPERATING GUIDE d. Slave reads the address bits on the next six rising edges of SCLK (2-7). Figure 6. Serial Port Timing Diagram - READ For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A - 11 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE ADVANCED OPERATION Cycle Slip Prevention (CSP) When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD varies rapidly over a range much greater than ±2 radians. Since the gain of the PFD varies linearly with phase up to ±2, the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. This phenomena is known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in Figure 7. Cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal Laplace analysis. OPERATING GUIDE A The synthesizer features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as the frequency difference is near zero. CSP allows significantly faster lock times as shown in Figure 7. The use of the CSP feature is enabled with pfds_rstb (Reg01 Table 4). The CSP feature may be optimized for a given set of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting pfds_sat_deltaN (Reg1C Table 30). Figure 7. Cycle Slip Prevention (CSP) A - 12 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE PFD Jitter & Lock Detect Background In normal phase locked operation the divided VCO signal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the VCO signal and the reference signal vary in time due to the phase noise of the crystal and VCO oscillators, the loop bandwidth used and the presence of fractional modulation or not. The total integrated noise on the VCO path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. If we wish to detect if the VCO is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. Figure 8. Synthesizer Phase Noise & Jitter With this simplification the single sideband integrated VCO phase noise, 2 , in rads2 at the phase detector is given by 2 2 2 (EQ 2) where SSB = ( (fo) B 2 ) / N 11 OPERATING GUIDE The standard deviation of the arrival time of the VCO signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked VCO has a constant phase noise, 2 (fo), at offsets less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. The simple locked VCO phase noise approximation is shown on the left of Figure 8. 2 SSB (fo) is the single sideband phase noise in rads2/Hz inside the loop bandwidth, B is the 3-dB corner frequency of the closed loop PLL, and N is the division ratio of the prescaler. The rms phase jitter of the VCO in rads, , results from the power sum of the two sidebands: 2 = 2SSB (EQ 3) Since the simple integral of (EQ 3) is just a product of constants, we can easily do the integral in the log domain. For example if the VCO phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is 100 kHz, and the division ratio N=100, then the integrated single sideband phase noise at the phase detector in dB 2 is given by dB = 10log (2 (fo)B / N2) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently = 10 -82/20 = 56 urads rms or 3.2 milli-degrees rms. While the phase noise reduces by a factor of 20logN after division to the reference, the jitter is a constant. The rms jitter from the phase noise is then given by Tjpn = Tref / 2 In this example if the reference was 50 MHz, Tref = 20 nsec, and hence Tjpn = 178 femtoseconds. A normal 3 sigma peak-to-peak variation in the arrival time therefore would be ±3 2 Tjpn = 0.756 ps For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A - 13 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE PFD Jitter & Lock Detect Background (Continued) If the synthesizer was in fractional mode, the fractional modulation of the VCO divider will dominate the jitter. The exact standard deviation of the divided VCO signal will vary based upon the modulator chosen, however a typical modulator will vary by about ±3 VCO periods, ±4 VCO periods, worst case. If, for example, a nominal VCO at 5 GHz is divided by 100 to equal the reference at 50 MHz, then the worst case division ratios will vary by 100±4. Hence the peak variation in the arrival times caused by modulation of the fractional synthesizer at the reference will be Tjpk = ±TVCO · Nmax - Nmin) / 2 OPERATING GUIDE A (EQ 4) In this example, Tjpk = ±200 ps(104-96)/2 = ±800 psec. If we note that the distribution of the delta sigma modulation is approximately gaussian, we could approximate Tjpk as a 3 sigma jitter, and hence we could estimate the rms jitter of the modulator as about 1/3 of Tjpk or about 266 psec in this example. Hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the VCO would be given by the rms sum , where 2 Tj = Tjpn + (Tjpk)2 (EQ 5) 3 In this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation. Bottom line, we have to expect about ±0.8 nsec of normal variation in the phase detector arrival times when in fractional mode. In addition, lower VCO frequencies with high reference frequencies will have much larger variations. For example, a 1 GHz VCO operating at near the minimum nominal divider ratio of 36, would, according to (EQ 4), exhibit about ±4 nsec of peak variation at the phase detector, under normal operation. The lock detect circuit must not confuse this modulation as being out of lock. PFD Lock Detect pfd_lkd_en (Reg01h Table 4) enables the lock detect functions of the Internal PLL. The Lock Detect circuit in the Internal PLL places a one shot window around the reference. The one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. Clearing lkd_ringosc_mono_select (Reg1Ah Table 28) will result in a nominal ±10nsec `analog' window of fixed length, as shown in Figure 3. Setting lkd_ringosc_mono_select will result in a variable length 'digital' widow. The digital one shot window is controlled by lkd_ringosc_cfg (Reg1Ah). The resulting lock detect window period is then generated by the number of ring oscillator periods defined in lkd_monost_duration Reg1Ah (Table 28). The lock detect ring oscillator may be observed on the GPO2 port by setting ringosc_testmode (Reg1Ah Table 28) and configuring the gpo_sel = 0111 in (Reg1Bh Table 29). Lock detect does not function when this test mode is enabled. lkd_wincnt_max (Reg1Ah Table 28) defines the number of consecutive counts of the VCO that must land inside the lock detect window to declare lock. If for example we set lkd_wincnt_max = 1000 , then the VCO arrival would have to occur inside the selected lock widow 1000 times in a row to be declared locked. When locked the Lock Detect flag ro_lock_detect (Reg1Fh Table 33) will be set. A single occurrence outside of the window will result in clearing the Lock Detect flag, ro_lock_detect. The Lock Detect flag ro_lock_detect (Reg1Fh Table 33) is a read only register, readable from the serial port. The Lock Detect flag is also output to the LD pin according to lkd_to_sdo_always (Reg1Ah) and lkd_to_sdo_ automux_en (Reg1Ah), both in Table 28. Setting lkd_to_sdo_always will always display the Lock Detect flag on LD. Clearing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the Lock Detect flag on LD except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data Out pin, and returns to the lock detect function after the read is completed. A - 14 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE PFD Lock Detect (Continued) Lock Detect with Phase Offset When operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. The phase detector linearity is worse when operated with zero phase offset. Hence in fractional mode it is necessary to offset the phase of the reference and the VCO at the phase detector. In such a case, for example with an offset delay, as shown in Figure 10, the mean phase of the VCO will always occur after the reference. The lock detect circuit window can be made more selective with a fixed offset delay by setting win_asym_enable and win_asym_up_select (Reg1Ah Table 28). Similarly the offset can be in advance of the reference by clearing win_asym_up_select while leaving win_asym_enable Reg1Ah set both in Table 28. 11 OPERATING GUIDE Figure 9. Normal Lock Detect Window Figure 10. Delayed Lock Detect Window For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A - 15 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE REGISTER MAP Table 2. Reg 00h Chip ID (Read Only) Register Bit Type [23:0] Ro Name Chip ID Default 581502 Description Chip ID Table 3. Reg 00h Strobe (Write Only) Register Bit STR global_swrst_regs 1 STR global_swrst_dig 0 Strobe to soft reset the rest of digital 2 STR mcnt_resynch 0 Reserved 3 A Type 0 Name Default STR tsens_spi_strobe 0 Strobe to clock the temp measurement on demand 0 Description Strobe to soft reset the SPI registers Table 4. Reg 01h Enable & Reset Register OPERATING GUIDE Bit Type 0 R/W malg_vcobug_en Name Default 1 VCO Buffer Enable 1 R/W mag_bias_en 1 Bias enable 10:2 R/W Reserved 11 R/W pfd_lkd_en 1 12 R/W cp_en 1 Charge Pump Enable, disable is tri-stated output 479 Description Reserved Enable / Resetb to digital lockdetect circuit and PFD's lockdetect output gates 13 R/W dsm_rstb 0 1 - Enables fractional modulator see also dsm_integer_mode Reg12h 14 R/W lkd_rstb 1 1 - enables lock detect circuit 15 R/W pfds_rstb 1 CSP PFD FF rstb 1 - Enables the Cycle Slip Prevention (CSP) feature of the PFD Table 5. Reg 02h Serial Data Out Force Register Bit Type Name Default Description 0 R/W malg_sdo_driver_force_ val 1 Serial Data Out Force value This value may be forced onto LD_SDO by setting malg_sdo_driver_force_en 1 R/W malg_sdo_driver_force_ en 1 Serial Data Out EN Force enable Places value from malg_sdo_driver_force_val on SDO Default Description Table 6. Reg 03h Reserved Bit Type 16:0 R/W Name Reserved 114689 Reserved Table 7. Reg 04h Prescaler Duty Cycle Register Bit 0 A - 16 Type R/W Name vcop_dutycycmode Default 1 Description Extends the low time from 15 to 47 VCO cycles for large divide ratios For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Table 8. Reg 05h Reserved Bit Type 2:0 R/W Name Reserved Default 7 Description Reserved Table 9. Reg 06h Phase Freq Detector Delay Register Bit Type 2:0 R/W Name pfd_del_sel Default 2 Description Delay line setpoint to PFD Table 10. Reg 07h Charge Pump UP/DN Control Register Bit Type Name Default Description R/W cp_UPcurrent_sel 16 9:5 R/W cp_DNcurrent_sel 16 Sets Charge-Pump Dn gain, 125uA lsb, binary, 4mA max Table 11. Reg 08h Charge Pump Trim & Offset Register Bit Type 3:0 R/W cp_UPtrim_sel Name Default 0 Trim Up gain, 14.3uA lsb, binary, 100uA max Description 7:4 R/W cp_DNtrim_sel 0 Trim Dn gain, 14.3uA lsb, binary, 100uA max 11:8 R/W cp_UPoffset_sel 3 Up Offset leakage current, 28.7uA lsb, binary, 430uA max 15:12 R/W cp_DNoffset_sel 0 Dn Offset leakage current, 28.7uA , binary, 430uAmax 17:16 R/W cp_amp_bias_sel 2 Charge Pump Dummy Branch Op amp bias selection, 100uA Table 12. Reg 09h Charge Pump EN Register Bit Type 0 R/W cp_pull_updn_en Name Default 0 Enables CP UP/Down Control Reg09 [1] Description 1 R/W cp_pull_dn_upb 0 11 OPERATING GUIDE 4:0 Sets Charge-Pump Up gain, 125uA lsb, binary, 4mA max 0 - Forces Charge Pump Up when Reg09[0]=1 1 - Forces Charge Pump DN when Reg09[0]=1 Table 13. Reg 0Ah Reserved Bit Type 11:0 R/W Name Reserved Default 68 Description Reserved Table 14. Reg 0Bh Reserved Bit Type 15:0 R/W Name Reserved Default 0 Description Reserved Table 15. Reg 0Ch Reserved Bit Type 13:0 R/W Name Reserved Default 256 Description Reserved For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A - 17 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Table 16. Reg 0Dh Reserved Bit Type 6:0 R/W Name Reserved Default 32 Description Reserved Table 17. Reg 0Eh Reserved Bit Type 23:0 R/W Name Reserved Default 0 Description Reserved Table 18. Reg 0Fh Integer Division Register Bit 15:0 A Type R/W dsm_intg Default 200 Description unsigned integer portion of VCO divider value, also known as NINT, see (EQ 12) Table 19. Reg 10h Fractional Division Register Bit OPERATING GUIDE Name 23:0 Type R/W Name dsm_frac Default 0 Description unsigned fractional portion of VCO divider also known as NFRAC, see (EQ 12) Table 20. Reg 11h Seed Register Bit 23:0 Type R/W Name dsm_seed Default 3A1953h Description unsigned seed value for modulator sets the start phase of the modulator Table 21. Reg 12h Delta Sigma Modulator Register Bit Type 0 R/W dsm_ref_clk_select Name Default 0 use reference instead of divider Description 1 R/W dsm_invert_clk_sd3 0 invert clk 2 R/W dsm_invert_clk_rph 1 inverts the ref clock phase 1- enables Integer Mode, bypasses the modulator, leaves it running see also dsm_rstb Reg01h to disable the modulator 3 R/W dsm_integer_mode 0 4 R/W Reserved 0 5 R/W Reserved 0 6 R/W dsm_xref_sin_select 1 when xref is selected specifies that the sine source is used 7 R/W dsm_autoseed 1 automatic seed load when changing the frac part, uses value in seed 9:8 R/W dsm_order 2 00-first order 01-second 10-third fb 11-third ff 13:10 dsm_quant_max 4'b0011 17:14 A - 18 R/W max value allowed out of modulator quantizer limits are +7 to -8, typ ±3 or ±4 R/W dsm_quant_min 4'b1100 min value allowed out of modulator quantizer limits are +7 to -8, typ ±3 or ±4 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Table 22. Reg 14h CW Sweep Control Register Type 0 R/W clear_ovf_undf 0 asynchronous clear for ovf/undf flags 1 R/W ramp_enable 0 Ramp En/rstb 1= enables the CW Ramp Function 2 R/W ramp_trigg 0 Write always triggers ramps if bit = 0, if bit = 1, Ramp will not trigger, bit must be reset to 0 first 3 R/W ramp_repeat_en 0 Ramp Repeat Seq enable 1= enables autotrigger of ramps 0 = ramp_trigg starts each ramp 4 R/W ramp_startdir_dn 0 Ramp start direction 1= Start with Ramp Down 0= Start with Ramp Up 5 R/W ramp_trig_ext_en 0 Enable hardware trigger on GPO3 pin 6 R/W ramp_singlestep 0 Ramp single step, advances the ramp to the next step, and holds frequency 0 Ramps in one direction only with hop to start at end of ramp 7 R/W Name ramp_singledir Default Description Table 23. Reg 15h CW Sweep Ramp Step Register Bit Type 23:0 R/W Name ramp_step Default 2048 Description Ramp Step size Table 24. Reg 16h CW Sweep Ramp Step Number Register Bit Type 23:0 R/W Name ramp_steps_number Default 2048 Description Ramp Number of steps in ramp Table 25. Reg 17h CW Sweep Dwell Time Register Bit 23:0 Type R/W Name ramp_dwell_time Default 2048 Description Ramp Number of cycles to hold at top/bottom in repeat mode 11 OPERATING GUIDE Bit Table 26. Reg 18h Reserved Bit Type 22:0 R/W Name Reserved Default 144 Description Reserved Table 27. Reg 19h Reserved Bit Type 4:0 R/W Name Reserved Default 15 Description Reserved For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com A - 19 v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Table 28. Reg 1Ah Lock Detect Register Bit Type Name Default 9:0 lkd_wincnt_max R/W lkd_win_asym_enable 0 Enables asymmetric lock detect window (nominal 10nsec) 11 R/W lkd_win_asym_up_select 0 Sets polarity of the window 12 R/W lkd_to_sdo_automux_en 1 Muxes the lkd output signal to SDO when SDO is not being used for Main Serial Port Data Outputs (Read Operation) 13 R/W lkd_to_sdo_always 0 Muxes the lkd output signal to SDO always, not possible to do Main Serial Port Read in this state 14 R/W lkd_ringosc_mono_select 0 1 select ringosc based oneshot for lock detect window 0 selects analog based oneshot 16:15 R/W lkd_ringosc_cfg 3 "0" fastest "3" slowest 18:17 R/W lkd_monost_duration 3 "0" shortest "3" longest 19 R/W lkd_ringosc_testmode 0 enables the ring osc by itself for testing OPERATING GUIDE R/W 10 A 248 Description threshold count in the timer window to declare lock (reference cycles) A - 20 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com v00.0809 MicroSynthTM INTEGRATED HERMETIC SYNTHESIZER, OPERATING GUIDE Table 29. Reg 1Bh GPO Control Register Type Name gpo_sel Default 0 Description Selects data to be driven on GPO ports gpo_sel = 0000 gpo_sel = 0001 GPO3