HM6287 HM6287H HM6287/HM6287H HM6287P-45 HM6287P-55 HM6287P-70 HM6287LP-45 - Datasheet Archive

 

65536-word × 1-bit High Speed CMOS Static RAM The Hitachi HM6287/HM6287H is a high speed 64 k static RAM organized as

 

HM6287 HM6287, HM6287H HM6287H Series 65536-word × 1-bit High Speed CMOS Static RAM The Hitachi HM6287/HM6287H HM6287/HM6287H is a high speed 64 k static RAM organized as 64-kword × 1-bit. It realizes high speed access time (25/35/45/55/70 ns) and low power consumption, employing CMOS process technology and high speed circuit design tech-nology. it is most advantageous for high speed and high density memory, such as cache memory for mainframes or 32-bit MPUs. The HM6287/HM6287H HM6287/HM6287H is packaged in a 300-mil plastic DIP and SOJ, and is available for high density mounting. The low power version retains data with battery back up. Ordering Information · Single 5 V supply and high density 22-pin DIP and 24-pin SOJ · High speed: Fast access time 25/35/45/55/70 ns (max) · Low power - Operation: 300 mW (typ) - Standby: 100 µW (typ)/10 µW (typ) (L-version) · Completely static memory · No clock or timing strobe required · Equal access and cycle times · Directly TTL compatible: All inputs and outputs · Battery back up capability (L-version) Access time HM6287P-45 HM6287P-45 45 ns HM6287P-55 HM6287P-55 55 ns HM6287P-70 HM6287P-70 70 ns HM6287LP-45 HM6287LP-45 45 ns HM6287LP-55 HM6287LP-55 Features Type No. 55 ns HM6287LP-70 HM6287LP-70 70 ns HM6287HP-25 HM6287HP-25 25 ns HM6287HP-35 HM6287HP-35 35 ns HM6287HLP-25 HM6287HLP-25 25 ns HM6287HLP-35 HM6287HLP-35 35 ns HM6287HJP-25 HM6287HJP-25 25 ns HM6287HJP-35 HM6287HJP-35 35 ns Package 300-mil, 22-pin plastic DIP (DP-22N DP-22N) 300-mil, 22-pin plastic DIP (DP-22NB DP-22NB) 300-mil, 24-pin SOJ (CP-24D CP-24D) HM6287HLJP-25 HM6287HLJP-25 25 ns HM6287HLJP-35 HM6287HLJP-35 35 ns 1 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Pin Arrangement HM6287P/HP HM6287P/HP Series HM6287HJP HM6287HJP Series A0 1 24 VCC A1 23 A2 2 3 22 A15 A14 A3 4 21 A13 A0 1 22 VCC A1 21 A2 2 3 20 A15 A14 A3 4 19 A13 A4 5 20 A12 A12 A5 6 19 NC 7 18 A11 A4 5 18 A5 6 17 A11 NC A6 7 16 A10 A6 8 17 A10 9 16 A9 A7 8 15 A9 A7 Dout 9 14 A8 Dout 10 15 14 A8 11 12 13 CS WE 10 13 Din WE VSS 11 12 CS VSS (Top view) Pin Description Pin Name Function A0­A15 Address Din Input Dout Output CS Chip select WE Write enable VCC Power supply VSS Ground 2 (Top view) Din HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Block Diagram A0 A1 A2 A3 A4 A5 A6 VCC VSS Memory array 128 × 512 Row decoder Dout Column I/O Din Column decoder CS WE A7 A15 Truth Table CS WE Mode VCC current Dout pin Cycle H × Standby ISB, ISB1 High-Z - L H Read ICC Dout Read cycle 1, 2 L L Write ICC High-Z Write cycle 1, 2 Note: ×: Don't care. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage any pin relative to VSS VT ­0.5* to +7.0 V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg ­55 to +125 °C Storage temperature under bias Tbias ­10 to +85 °C Note: VT min: ­3.5 V for pulse width 20 ns (HM6287 HM6287 Series) VT min: ­2.0 V for pulse width 10 ns (HM6287H HM6287H Series) 3 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input high (logic 1) voltage VIH 2.2 - 6.0 V Input low (logic 0) voltage VIL ­0.5*1 - 0.8 V Note: 1. VIL min: ­3.0 V for pulse width 20 ns (HM6287 HM6287 Series) VIL min: ­2.0 V for pulse width 10 ns (HM6287H HM6287H Series) DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM6287 HM6287 - Symbol Min Typ*1 Max HM6287H HM6287H - Min Typ*1 Max Unit Test conditions Input leakage current |ILI| - - 2.0 - - 2.0 µA VCC = Max Vin = VSS to VCC Output leakage current |ILO| - - 2.0 - - 2.0 µA CS = VIH, VI/O = VSS to VCC Operating VCC current ICC - 60 100 - 60 120 mA CS = VIL, Iout = 0 mA, min cycle Standby VCC current ISB - 10 30 - 15 30 mA CS = VIH, min. cycle Standby VCC current (1) ISB1 - - 0.02 0.02*2 2.0 0.1*2 - - 0.02 0.02*2 2.0 0.1*2 mA mA CS VCC ­ 0.2 V 0 V Vin 0.2 V or VCC ­ 0.2 V Vin Output low voltage VOL - - 0.4 - - 0.4 V IOL = 8 mA Output high voltage VOH 2.4 - - 2.4 - - V IOH = ­4.0 mA Parameter Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. 2. These characteristics are guaranteed only for L-version. 4 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Capacitance (Ta = 25°C, f = 1.0 MHz)*1 Parameter Symbol HM6287 HM6287 - Min Max Input capacitance Cin - 5 - 6 pF Vin = 0 V - 7.5 - 8 pF Vout = 0 V Output capacitance Cout Note: HM6287H HM6287H - Min Max Unit Test conditions 1. These parameters are sampled and not 100% tested. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions: · · · · Input pulse levels: VSS to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall times: 5 ns Output load: See figure Output Load +5V +5V 480 Dout 255 480 Dout 30 pF *1 Output load (A) 255 5 pF *1 Output load (B) (for tHZ, tLZ, tWZ and tOW ) Note: 1. Including scope and jig 5 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Read Cycle HM6287H-25 HM6287H-25 HM6287H-35 HM6287H-35 - - Parameter Symbol Min Max Min Max HM6287-45 HM6287-45 HM6287-55 HM6287-55 HM6287-70 HM6287-70 -­ -­ -­ Min Max Min Max Min Max Unit Notes Read cycle tRC time 25 - 35 - 45 - 55 - 70 - ns Address tAA access time - 25 - 35 - 45 - 55 - 70 ns Chip select tACS access time - 25 - 35 - 45 - 55 - 70 ns Output hold tOH from address change 3 - 5 - 5 - 5 - 5 - ns Chip selec- tLZ tion to output in low-Z 5 - 5 - 5 - 5 - 5 - ns 1, 3, 4 Chip detHZ selection to output in high-Z 0 12 0 20 0 30 0 30 0 30 ns 1, 3, 4 Chip select tPU ion to powerup time 0 - 0 - 0 - 0 - 0 - ns 4 Chip detPD selection to power down time - 25 - 30 - 40 - 40 - 40 ns 4 2 Notes: 1. Transistion is measured +200 mV from steady state voltage with load (B). 2. All read cycle timing is referenced from last valid address to the first transitioning address. 3. At any given temperature and voltage condition, tHZ max, is less the tLZ min both for a given device and from device to device. 4. These parameters are sampled and not 100% tested. 6 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Read Timing Waveform (1) tRC Address tAA tOH tOH Dout Previous data valid Valid Data Notes: 1. WE is high for read cycle. 2. Device is continously selected, CS = VIL. 3. All read cycle timing is referred from last valid address to the first transitioning address. Read Timing Waveform (2) tRC CS tHZ tACS tLZ Dout VCC supply current High impedance tPU ICC 50% Valid Data tPD High impedance 50% ISB Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transistion low. 7 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Write Cycle HM6287H-25 HM6287H-25 HM6287H-35 HM6287H-35 - - Parameter Symbol Min Max Min Max HM6287-45 HM6287-45 HM6287-55 HM6287-55 HM6287-70 HM6287-70 -­ -­ -­ Min Max Min Max Min Max Unit Notes Write cycle tWC time 25 - 35 - 45 - 55 - 70 - ns Chip select tCW ion to end of write 20 - 30 - 40 - 50 - 55 - ns Address tAW valid to end of write 20 - 30 - 40 - 50 - 55 - ns Address setup time 0 - 0 - 0 - 0 - 0 - ns Write pulse tWP width 20 - 30 - 25 - 35 - 40 - ns Write retWR covery time 0 - 0 - 0 - 0 - 0 - ns Data valid to end of write tDW 15 - 20 - 25 - 25 - 30 - ns Data hold time tDH 0 - 0 - 0 - 0 - 0 - ns Write enabled to output in high-Z tWZ 0 8 0 10 0 25 0 25 0 30 ns 2 Output tOW active from end of write 5 - 5 - 0 - 0 - 0 - ns 2 tAS 1 Notes: 1. All write cycle timing is referenced from the last valid address to first transitioning address. 2. Transition is measured ±200 mV from steady state voltage with load B. These parameters are sampled and not 100% tested. 8 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS tWR *2 tWP *1 WE tDW tDH Valid Data Din tWZ tOW tOH *3 High impedance Dout Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. Dout is the same phase of write data of this write cycle, if tWR is long enough. 9 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tWR *2 tAS tCW CS tWP *1 WE tDW Din tDH Valid Data High impedance *3 Dout Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedence state. 10 HM6287 HM6287, HM6287H HM6287H Series HM6287 HM6287, HM6287H HM6287H Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) (These specifications are guaranteed only for L-version.) Parameter Symbol Min Typ Max Unit Test condition VCC for data retention VDR 2.0 - - V Data retention current ICCDR - - 50*2 35*3 µA CS VCC ­ 0.2 V, 0 V Vin ­ 0.2 V, or 0 V Vin 0.2V Chip deselect to data retention time tCDR 0 - - ns Operation recovery time tRC*1 - - ns tR See retention waveform Notes: 1. tRC = Read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V Low VCC Data Retention Waveform Data retention mode VCC 4.5 V tCDR 2.2 V CS VDR ­ 0.2 V CS 0V 11 tR VDR