HM628127HB ADE-203-350B HM628127HBJP-15 HM628127HBJP-20 CP-32DB - Datasheet Archive

 

131072-word × 8-bit High Speed CMOS Static RAM ADE-203-350B (Z) Rev. 2.0 Jun. 27, 1996 Description The HM628127HB is an

 

HM628127HB HM628127HB Series 131072-word × 8-bit High Speed CMOS Static RAM ADE-203-350B ADE-203-350B (Z) Rev. 2.0 Jun. 27, 1996 Description The HM628127HB HM628127HB is an asyncronous high speed static RAM organized as 128-k word × 8-bit. It realize high speed access time (15/20 ns) with employing 0.8 µm shrink CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM628127HB HM628127HB is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features · · · · · · · Single 5 V supply Access time 15/20 ns (max) Completely static memory No clock or timing strobe required Equal access and cycle times Directly TTL compatible All inputs and outputs 400-mil 32-pin SOJ package Center VCC and VSS type pinout Ordering Information Type No. Access time Package HM628127HBJP-15 HM628127HBJP-15 HM628127HBJP-20 HM628127HBJP-20 15 ns 20 ns 400-mil 32-pin plastic SOJ (CP-32DB CP-32DB) HM628127HBLJP-15 HM628127HBLJP-15 HM628127HBLJP-20 HM628127HBLJP-20 15 ns 20 ns HM628127HB HM628127HB Series Pin Arrangement HM628127HBJP/HBLJP HM628127HBJP/HBLJP Series A3 1 32 A4 A2 2 31 A5 A1 3 30 A6 A0 4 29 A7 CS 5 28 OE I/O1 6 27 I/O8 I/O2 7 26 I/O7 VCC 8 25 VSS VSS 9 24 VCC I/O3 10 23 I/O6 I/O4 11 22 I/O5 WE 12 21 A8 A16 13 20 A9 A15 14 19 A10 A14 15 18 A11 A13 16 17 A12 (Top View) Pin Description Pin Name Function A0 to A16 Address input I/O1 to I/O8 Data input/output CS Chip select OE Output enable WE Write enable VCC Power supply VSS Ground HM628127HB HM628127HB Series Block Diagram (LSB) A3 A2 A1 A0 A7 A6 A5 A4 (MSB) VCC VSS Memory matrix 256 rows × 512 columns × 8 bit (1,048,576 bits) Row decoder CS Column I/O I/O1 . . . I/O8 Input data control Column decoder CS (LSB) A13 A12 A11 A14 A15 A16 A10 A9 A8 (MSB) WE CS OE CS Function Table CS OE WE Mode VCC current I/O Ref. cycle H × × Standby ISB , ISB1 High-Z - L H H Output disable ICC High-Z - L L H Read ICC Dout Read cycle (1) to (3) L H L Write ICC Din Write cycle (1) L L Write ICC Din Write cycle (2) L Note: ×: H or L HM628127HB HM628127HB Series Absolute Maximum Ratings Parameter Symbol Value Unit Supply voltage relative to VSS VCC ­0.5 to +7.0 V Voltage on any pin relative to VSS 1 VT ­0.5* to VCC+0.5 2 3 V Power dissipation PT 1.0* /1.5* W Operating temperature Topr 0 to +70 °C Storage temperature Tstg ­55 to +125 °C Storage temperature under bias Tbias ­10 to +85 °C Notes: 1. VT min = ­2.5 V for pulse width (under shoot) 10 ns 2. At still air condition 3. At air flow 1.0 m/s Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Typ Max Unit 4.5 5.0 5.5 V VSS * Input voltage Min 2 3 Supply voltage Symbol 0 0 0 V VIH 2.2 - VCC + 0.5 V - 0.8 V VCC* VIL 1 ­0.5* Notes: 1. VIL min = ­2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level. HM628127HB HM628127HB Series DC Characteristics (Ta = 0 to +70°C, VCC = 5V ± 10%, VSS = 0V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current IILII - - 2 µA Vin = VSS to VCC Output leakage current IILO I - - 2 µA Vin = VSS to VCC 15 ns cycle ICC - 120 180 mA CS = VIL, lout = 0 mA Other inputs = VIH/VIL 20 ns cycle ICC - 100 150 15 ns cycle ISB - 55 100 mA CS = VIH, Other inputs = VIH/VIL 20 ns cycle ISB - 45 80 - - 2 mA VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V -*2 -*2 0.2*2 VOL - - 0.4 V IOL = 8 mA VOH 2.4 - - V IOH = ­4 mA Operation power supply current Standby power supply current ISB1 Output voltage Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter Symbol Input capacitance* 1 Input/output capacitance* Note: Min Typ Max Unit Test conditions Cin 1 - - 6 pF Vin = 0 V CI/O - - 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. HM628127HB HM628127HB Series AC Characteristics (Ta = 0 to +70°C, VCC = 5V ± 10%, unless otherwise noted.) Test Conditions · · · · Input pulse levels: 0 V to 3.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5V Output load: See figures 5V 5V 480 480 Dout Dout 255 255 30 pF* 5 pF* Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Output load (A) *Including scope and jig Read Cycle HM628127HB-15 HM628127HB-15 HM628127HB-20 HM628127HB-20 Parameter Symbol Min Max Min Max Unit Notes Read cycle time tRC 15 - 20 - ns Address access time tAA - 15 - 20 ns Chip select access time tACS - 15 - 20 ns Output enable to outpput valid tOE - 8 - 10 ns Output hold from address change tOH 5 - 5 - ns Chip select to output in low-Z tCLZ 3 - 3 - ns 1 Output enable to output in low-Z tOLZ 1 - 1 - ns 1 Chip deselect to output in high-Z tCHZ - 7 - 7 ns 1 Output disable to output in high-Z tOHZ - 7 - 7 ns 1 Chip selection to power up time tPU 0 - 0 - ns Chip selection to power down time tPD - 15 - 20 ns HM628127HB HM628127HB Series Write Cycle HM628127HB-15 HM628127HB-15 HM628127HB-20 HM628127HB-20 Parameter Symbol Min Max Min Max Unit Write cycle time tWC 15 - 20 - ns Address valid to end of write tAW 12 - 15 - ns Chip select to end of write tCW 10 - 12 - ns 9 Write pulse width tWP 10 - 12 - ns 8 Address setup time tAS 0 - 0 - ns 6 Write recovery time tWR 0 - 0 - ns 7 Data to write time overlap tDW 8 - 10 - ns Data hold from write time tDH 0 - 0 - ns Write disable to output in low-Z tOW 3 - 3 - ns 1 Output disable to output in high-Z tOHZ - 7 - 7 ns 1 Write enable to output in high-Z tWHZ - 7 - 7 ns 1 Note: Notes 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS transition low. 3. WE and/or CS must be high during address transition time. 4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 6. tAS is measured from the latest address transition to the later of CS or WE going low. 7. tWR is measured from the earlier of CS or WE going high to the first address transition. 8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. tWP is measured from the beginnig of write to the end of write. 9. tCW is measured from the later of CS going low to the the end of write. HM628127HB HM628127HB Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) t RC Address Valid address t OH t AA t CHZ t ACS CS t OE t OHZ OE t OLZ t CLZ Dout High Impedance Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) t RC Address Valid address t OH t AA t OH Dout Valid data HM628127HB HM628127HB Series Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2 tRC CS tASC tCHZ tCLZ High Impedance Dout ICC VCC supply current ISB High Impedance Valid data tPD tPU 50% 50% Write Timing Waveform (1) (WE Controlled) t WC Valid address Address t WR t AW OE t CW CS*3 t AS t WP WE*3 t OHZ High impedance*5 Dout t DW Din *4 t DH Valid data *4 HM628127HB HM628127HB Series Write Timing Waveform (2) (CS Controlled) t WC Valid address Address t WR t CW CS *3 t AW t WP WE *3 t AS t WHZ t OW High impedance*5 Dout t DW Din *4 t DH Valid data *4 HM628127HB HM628127HB Series Low VCC Data Retention Characteristics (Ta = 0 to 70°C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ*1 Max Unit Test conditions VCC for data retention VDR 2.0 - - V VCC CS VCC ­ 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC ­ 0.2 V Data retention current ICCDR - 2 80 µA VCC = 3 V, VCC CS VCC ­ 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC ­ 0.2 V Chip deselect to data retention time tCDR 0 - - ns See retention waveform Operation recovery time tR 5 - - ms Note: 1. Typical values are at VCC = 3.0 V, Ta = 25°C, and not guaranteed. Low V CC Data Retention Timing Waveform t CDR Data retention mode V CC 4.5 V 2.2 V V DR CS 0V VCC CS VCC ­ 0.2 V tR HM628127HB HM628127HB Series Package Dimensions HM628127HBJP/HBLJP HM628127HBJP/HBLJP Series (CP-32DB CP-32DB) 0.43 ± 0.10 1.27 0.10 2.85 ± 0.12 1.30 Max 0.63 Min 16 0.74 3.50 ± 0.26 1 11.18 ± 0.13 17 10.16 ± 0.13 32 20.71 21.08 Max Unit: mm 9.40 ± 0.25 HM628127HB HM628127HB Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HM628127HB HM628127HB Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Sep. 9, 1995 Initial issue Y. Saitou K. Yoshizaki 1.0 Nov. 15, 1995 Dletion of HM628127HB-25 HM628127HB-25 series Y. Saitou K. Yoshizaki 1.0 Jun. 27 1996 Change of format Change of Block Diagram Function Table Addition of Mode parameter Recommended DC Operating Conditions Change of note 2. Addition of note 3. AC Characteristics Change order of notes Change of Timing Waveform Addition of Read timing waveform(2), (3) Low VCC Data Retention Charactristics Change of Test conditions for ICCDR