ADE-203-186A HM5241605 HM5241605TT-20 HM5241605TT-17 HM5241605TT-15 TTP-50D - Datasheet Archive

 

HM5241605 Series 131,072-word × 16-bit × 2-bank Synchronous Dynamic RAM Rev. 1.0 Nov. 18, 1994 All inputs and outputs

 

ADE-203-186A ADE-203-186A (Z) HM5241605 HM5241605 Series 131,072-word × 16-bit × 2-bank Synchronous Dynamic RAM Rev. 1.0 Nov. 18, 1994 All inputs and outputs are referred to the rising edge of the clock input. The HM5241605 HM5241605 is offered in 2 banks for improved performance. Features · 3.3V Power supply · Clock frequency 66 MHz/57 MHz/50 MHz · LVTTL interface · Single pulsed RAS · 2 Banks can operates simultaneously and independently · Burst read/write operation and burst read/single write operation capability · Programmable burst length 1/2/4/8/full page · Programmable burst sequence Sequential/interleave · Full page burst length capability Sequential burst burst stop capability · Programmable CAS latency 1/2/3 · Byte control by DQMU and DQML · 1024 refresh cycles: 16 ms · 2 variations of refresh - Auto refresh - Self refresh Ordering Information Type No. Frequency Package HM5241605TT-20 HM5241605TT-20 HM5241605TT-17 HM5241605TT-17 HM5241605TT-15 HM5241605TT-15 50 MHz 57 MHz 66 MHz 400-mil 50-pin plasticTSOP II (TTP-50D TTP-50D) HM5241605 HM5241605 Series Pin Arrangement Pin Description Pin name Function A0 ­ A9 Address input - Row address A0 ­ A8 - Column address A0 ­ A7 - Bank select address A9 HM5241605TT HM5241605TT Series VCC 1 50 VSS I/O0 2 49 I/O15 I/O15 I/O0 ­ I/O15 I/O15 Data-input/output I/O1 3 48 I/O14 I/O14 CS Chip select VSSQ 4 47 VSSQ RAS I/O2 5 46 I/O13 I/O13 Row address strobe command I/O3 6 45 I/O12 I/O12 CAS VCCQ 7 44 VCCQ Column address strobe command I/O4 8 43 I/O11 I/O11 WE Write enable command I/O5 9 42 I/O10 I/O10 VSSQ 10 41 VSSQ DQMU DQML Upper byte input/output mask Lower byte input/output mask I/O6 11 40 I/O9 CLK Clock input I/O7 12 39 I/O8 CKE Clock enable VCCQ 13 38 VCCQ DQML 14 37 NC VCC Power for internal circuit (3.3 V) WE 15 36 DQMU Ground for internal circuit 35 VSS CAS 16 CLK RAS 17 34 CKE VCCQ Power for I/O pin (3.3 V) CS 18 33 NC VSSQ Ground for I/O pin A9 19 32 NC NC No connection A8 20 31 NC A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 VSS (Top View) 2 HM5241605 HM5241605 Series Block Diagram A0 ­ A9 A0 ­ A7 Column address counter A0 ­ A9 Column address buffer 512 row X 256 column X 16 bit Input buffer Sense amplifier & I/O bus Bank 0 Row decoder Column decoder Memory array Bank 1 512 row X 256 column X 16 bit Output buffer Control logic & timing generator DQMU DQML WE CAS RAS CS CKE I/O0 ­ I/O15 I/O15 CLK Sense amplifier & I/O bus Column decoder Row decoder Memory array Refresh counter Row address buffer 3 HM5241605 HM5241605 Series Pin Functions · CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. · CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. · RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. · CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. · DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers. Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the output buffer becomes Low-Z. Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If DQMU/DQML is Low, the data is written. · I/O0 to I/O15 I/O15 (I/O pins): · A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A8 defines the precharge mode. When A8 = High at the precharge command cycle, both banks are precharged. But when A8 = Low at the precharge command cycle, only the bank that is selected by A9 (BS) is precharged. · A9 (input pin): A9 is a bank select signal (BS). The memory array of the HM5241605 HM5241605 is divided into bank 0 and bank 1, both which contain 512 row × 256 column × 16 bits. If A9 is Low, bank 0 is selected, and if A9 is High, bank 1 is selected. 4 Data is input to and output from these pins. These pins are the same as those of a conventional DRAM. · VCC and VCCQ (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) · VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) HM5241605 HM5241605 Series Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Function Symbol CKE n-1 n CS RAS CAS WE A9 A8 A7 -0 Ignore command DESL H X H X X X X X X No operation NOP H X L H H H X X X Burst stop in full page BST H X L H H L X X X Column address and read command READ H X L H L H V L V Read with auto-precharge READ A H X L H L H V H V Column address and write command WRIT H X L H L L V L V Write with auto-precharge WRIT A H X L H L L V H V Row address strobe and bank act. ACTV H X L L H H V V V Precharge select bank PRE H X L L H L V L X Precharge all bank PALL H X L L H L X H X Refresh REF/SELF H V L L L H X X X Mode register set MRS X L L L L L L V Note: H H: VIH. L: VIL. X: VIH or VIL. V: Valid address input · Ignore command [DESL]: When this command is set ( CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. · No operation [NOP]: This command is not an execution command. However, the internal operations continue. ·Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page(256), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (256), it automatically returns to the start address, and input/output is performed repeatedly. · Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0-AY7) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. · Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page(256), this command is illegal. 5 HM5241605 HM5241605 Series · Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A9) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7) and the bank select address (A9). · Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A9. If A9 is Low, bank 0 is selected. If A9 is High, bank 1 is selected. · Precharge all banks [PALL]: This command starts a precharge operation for all banks. · Refresh [REF/SELF]: · Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is fullpage(256), this command is illegal. This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. · Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0-A9) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. · Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A9(BS) and determines the row address (AX0-AX8). When A9 is Low, bank 0 is activated. When A9 is High, bank 1 is activated. DQM Truth Table Function Symbol CKE n-1 n DQM U L Upper byte write enable/output enable ENBU H X L X Lower byte write enable/output enable ENBL H X X L Upper byte write inhibit/output disable MASKU H X H X Lower byte write inhibit/output disable MASKL H X X H Note: H: VIH. L: VIL. X: VIH or VIL. The HM5241605 HM5241605 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. 6 During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5241605 HM5241605 operating instructions. HM5241605 HM5241605 Series CKE Truth Table Current state Function CKE n-1 n CS RAS CAS WE Address Active Clock suspend mode entry H L X X X X X Any Clock suspend L L X X X X X Clock suspend Clock suspend mode exit L H X X X X X Idle Auto-refresh command REF H H L L L H X Idle Self-refresh entry SELF H L L L L H X Idle Power down entry H L L H H H X H L H X X X X L H L H H H X L H H X X X X L H L H H H X L H H X X X X Self refresh Power down Note: Self refresh exit SELFX Power down exit H: VIH. L: VIL. X: VIH or VIL. · Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. · ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. · READ suspend and READ A suspend: The data being output is held (and continues to be output). · WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. · Clock suspend: During clock suspend mode, keep the CKL to Low. · Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. · IDLE: In this state, all banks are not selected, and completed precharge operation. · Auto-refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 1,024 times are required to refresh the entire memory. Before executing the autorefresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after autorefresh, no precharge command is required after auto-refresh. 7 HM5241605 HM5241605 Series · Self-refresh entry [SELF]: · Self-refresh exit: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. When this command is executed during selfrefresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from selfrefresh mode, the synchronous DRAM enters the IDLE state. · Power down exit: · Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state CS RAS CAS WE Address Command Operation Precharge H X X X X DESL Enter IDLE after tRP L H H H X NOP Enter IDLE after tRP L H H L X BST ILLEGAL L H L H BA, CA, A8 READ/READ A ILLEGAL L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A8 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A8 READ/READ A ILLEGAL L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Bank and row active L L H L BA, A8 PRE, PALL NOP Idle 8 HM5241605 HM5241605 Series Function Truth Table (cont) Current state CS RAS CAS WE Address Command Operation Idle L L L H X REF, SELF Refresh L L L L MODE MRS Mode register set H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A8 READ/READ A Begin read L H L L BA, CA, A8 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank L L H L BA, A8 PRE, PALL Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop to full page L H L H BA, CA, A8 READ/READ A Continue burst read to CAS latency and New read L H L L BA, CA, A8 WRIT/WRIT A Term burst read/start write L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank L L H L BA, A8 PRE, PALL Term burst read and Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and precharge L H H H X NOP Continue burst to end and precharge L H H L X BST ILLEGAL L H L H BA, CA, A8 READ/READ A ILLEGAL L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank L L H L BA, A8 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Row active Read Read with auto-precharge 9 HM5241605 HM5241605 Series Function Truth Table (cont.) Current state CS RAS CAS WE Address Command Operation Write H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop on full page L H L H BA, CA, A8 READ/READ A Term burst and New read L H L L BA, CA, A8 WRIT/WRIT A Term burst and New write L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank L L H L BA, A8 PRE, PALL Term burst write an Precharge*2 L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and precharge L H H H X NOP Continue burst to end Write with auto-precharge and precharge L H L X BST L H L H BA, CA, A8 READ/READ A ILLEGAL L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active*3 L L H L BA, A8 PRE, PALL ILLEGAL on same bank ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Enter IDLE after tRC L H H H X NOP Enter IDLE after tRC L H H L X BST Enter IDLE after tRC L H L H BA, CA, A8 READ/READ A ILLEGAL L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A8 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L Refresh (auto-refresh) H ILLEGAL L L L MODE MRS ILLEGAL Notes 1. H: VIH. L: VIL. X: VIH or VIL. The other combinations are inhibit. 2. An interval of tRWL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 10 HM5241605 HM5241605 Series From [PRECHARGE] · To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From [IDLE] · To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. · To [ACTV]: The bank specified by the address pins and the ROW address is activated. · To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self- refresh). · To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. · To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of tRAS is required.) From [READ] · To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. · To [BST]: This command stops a full-page burst. · To [READ], [READ A]: · To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] · To [DESL], [NOP] or [BST]: These commands result in no operation. · To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) · To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. · To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. · To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. · To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. 11 HM5241605 HM5241605 Series From [READ with AUTO-PRECHARGE] · To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. · To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. · To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. · To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. From [WRITE with AUTO-PRECHARGE] · To [DESL], [NOP]: From [WRITE] · To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. · To [BST]: This command stops a full-page burst. · To [READ], [READ A]: These commands stop a burst and start a read cycle. · To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. 12 These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. · To [ACTV]: This command makes the other bank activ. (However, an interval of t RC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t RC ), the synchronous DRAM automatically enters the IDLE state. HM5241605 HM5241605 Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE CLOCK SUSPEND CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE READ WRITE WITH AP READ WRITE CKE READ WITH AP WRITE WITH AP WRITEA READ CKE CKE POWER ON READ SUSPEND READ WITH AP CKE_ READA CKE PRECHARGE POWER APPLIED WRITE WITH AP Read CKE_ PRECHARGE CKE_ WRITEA SUSPEND READ WITH AP READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 13 HM5241605 HM5241605 Series · A7 Mode Register Configuration Keep this bit Low at the mode register set cycle. The mode register is set by the input to the address pins (A0 to A9) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. · A6, A5, A4: (LMODE) These pins specify the CAS latency. · A9 and A8: (OPCODE) · A3: (BT) The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. A burst type is specified. When full-page burst is performed, only "sequential" can be selected. · A2, A1, A0: (BL) · Burst read and BURST WRITE These pins specify the burst length. Burst write is performed for the specified burst length starting from the column address specified in the write cycle. · Burst read and SINGLE WRITE Data is only written to the column address specified during the write cycle, regardless of the burst length. A9 A8 A7 OPCODE A6 0 A5 A4 LMODE A3 A2 BT A6 A5 A4 CAS Latency 0 0 0 R 0 0 1 1 A1 A0 BL A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 Burst Length BT=0 BT=1 0 0 0 1 1 0 0 0 0 1 2 2 0 1 1 3 0 1 0 4 4 1 X X R 0 1 1 8 8 1 A9 A8 1 2 0 0 R R 1 0 1 R R 1 1 0 R R 1 1 1 F.P. R Write mode Burst read and burst write 0 0 1 1 0 Burst read and SINGLE WRITE F.P. =Full Page (256) 1 14 0 1 R is Reserved(inhibit) R R HM5241605 HM5241605 Series Burst Sequence Burst length = 2 Stating Ad. A0 Burst length = 4 Addressing(decimal) Sequence Interleave Stating Ad. A1 A0 Addressing(decimal) Sequence Interleave 0 0, 1, 0, 1, 0 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 0, 1, 0, 0 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Burst length = 8 Addressing(decimal) Stating Ad. A2 A1 A0 Sequence Interleave 0 0 0 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, 15 HM5241605 HM5241605 Series Operation of HM5241605 HM5241605 Series Read/Write Operations · Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A9 pin, and the row address (AX0 to AX8) is activated by the A0 to A8 pins at the bank active command cycle. An interval of t RCD is required between the bank active command input and the following read/write command input. · Read operation A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. HM5241605 HM5241605 series can perform a burst read operation. The burst length can be set to 1,2,4,8 or fullpage(256). The start address for a burst read is specified by the column address (AY0 to AY7) and the bank select address (A9) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 1,2,3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page(256), data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register. CAS Latency CLK t RCD Command Address Active Row CL = 1 Dout CL = 2 CL = 3 16 Read Column out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 CL: CAS latency Burst length = 4 HM5241605 HM5241605 Series Read/Write Operations (cont) Burst Length CLK t RCD Command Active Read Address Row Column BL = 1 out 0 out 0 out 1 BL = 2 Dout out 0 out 1 out 2 out 3 BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 5 out 6 out 7 out 8 BL = 8 out 0 out 1 out 2 out 3 out 4 out 255 out 0 out 1 BL = full page (256) BL: Burst length CAS latency = 2 · Write operation Burst write or single write mode is selected by the OPCODE (A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE(A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7) and the bank select address (A9) at the write command set cycle. 2. Single write: A single write operation is enabled by setting OPCODE(A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A9) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). 17 HM5241605 HM5241605 Series Read/Write Operations (cont) Burst Write CLK t RCD Command Active Write Address Row Column BL = 1 in 0 in 0 in 1 in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 BL = 2 Din BL = 4 BL = 8 BL = full page (256) in 8 in 255 in 0 in 1 CAS latency = 1, 2, 3 Single Write CLK t RCD Command Address Din Active Row Write Column in 0 CAS latency = 1, 2, 3 Burst length = 1, 2, 4, 8, full page 18 HM5241605 HM5241605 Series Read/Write Operations (cont) The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. · Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. CAS latency Precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output 1 same cycle as the final data is output CLK CL=1 Command Read Active out0 Dout out1 out2 out3 lAPR CL=2 Command Read Active out0 Dout out1 out2 out3 lAPR CL=3 Command Dout Read Active out0 out1 out2 out3 lAPR Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 33 MHz (IAPR changes depending on the operating frequency. 19 HM5241605 HM5241605 Series Read/Write Operations (cont) · Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of the next command. Burst Write (Burst Length = 4) CLK Command I/O(input) Write in0 Active in1 in2 in3 lAPW Single Write CLK Command Write I/O(input) in Active lAPW 20 HM5241605 HM5241605 Series Full-page Burst Stop The timing from command input to the last data changes depending on the CAS latency setting. When the CAS latency is 3, the data becomes invalid two cycles after the BST command. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths of 1, 2, 4, and 8. · Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. CAS latency BST to valid data BST to high impedance 1 0 1 2 1 2 3 1 3 CAS Latency = 1, Burst Length = full page CLK Burst stop Command I/O(output) out out out out out l BSR l BSH 0 cycle 1 cycle CAS Latency = 2, Burst Length = full page CLK Burst stop Command I/O(output) out out out out out out l BSH = 2 cycle l BSR = 1 cycle 21 HM5241605 HM5241605 Series Full-page Burst Stop (cont) CAS Latency = 3, Burst Length = full page CLK Burst stop Command I/O (output) out out out out out out l BSR = 2 cycle · Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. Data is still written in the same cycle as the BST command, but no data is written in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4, and 8. And an interval of tRWL is required between the BST command and the next precharge command. Burst Length = full page CLK Burst stop Command I/O(input) in in Precharge in l BSW = 1 cycle t RWL 22 out l BSH = 3 cycle HM5241605 HM5241605 Series Command Intervals · Read command to Read command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) CLK Command ACTIVE Address (A0-A8) Row READ A READ B Column A Column B BS(A9) Dout out A0 out B0 out B1 out B2 out B3 Bank0 Active 2. CAS latency = 3 Burst length = 4 Bank0 Column =A Column =B Column =A Column =B Dout Read Read Dout Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. 23 HM5241605 HM5241605 Series Command Intervals (cont) READ to READ Command Interval (different bank) CLK Command Address (A0-A8) ACTIVE 0 Row 0 ACTIVE 1 READ A Row 1 READ B Column A Column B BS(A9) Dout out A0 out B0 out B1 out B2 out B3 Bank0 Active Bank0 Bank1 Dout Dout Bank1 Bank0 Bank1 Active Read Read CAS latency = 3 Burst length = 4 · Write command to Write command interval 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) CLK Command ACTIVE Address (A0-A8) Row WRITE A WRITE B Column A Column B BS(A9) Din in A0 Bank0 Active 24 in B0 in B1 Column =A Column =B Write Write in B2 in B3 Burst write mode Burst length = 4 Bank0 HM5241605 HM5241605 Series Command Intervals (cont) 2. 3. Different bank: Same bank, different ROW address: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. WRITE to WRITE Command Interval (different bank) CLK Command Address (A0-A8) ACTIVE 1 WRITE A WRITE B ACTIVE 0 Row 1 Row 0 Column A Column B BS(A9) Din in A0 Bank0 Active in B0 in B1 in B2 in B3 Burst write mode Burst length = 4 Bank1 Bank0 Bank1 Active Write Write · Read command to Write command interval 1. can be performed after an interval of no less than 1 cycle. However, DQML/DQMU must be set High so that the output buffer becomes High-Z before data input. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command READ to Write Command Interval CLK Command READ A WRITE B CL=1 DQML /DQMU CL=2 CL=3 Din Dout in B0 in B1 in B2 in B3 High-Z 25 HM5241605 HM5241605 Series Command Intervals (cont) 2. DQMU must be set High so that the output buffer becomes High-Z before data input. Same bank, different ROW address: · Write command to Read command interval When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command or a bank-active command. 3. 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the write command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQML/ WRITE to READ Command Interval (1) CLK Command WRITE A READ B DQML/DQMU Din in A0 Dout out B0 Column=A Write out B1 out B2 out B3 Burst write mode CAS latency = 1 Burst length = 4 Bank0 CAS Latency Column=B Read Column=B Dout WRITE to READ Command Interval (2) CLK Command WRITE A READ B DQML/DQMU Din in A0 in A1 Dout out B0 Column=A Write CAS Latency Column=B Read 26 Column=B Dout out B1 out B2 out B3 Burst write mode CAS latency = 1 Burst length = 4 Bank0 HM5241605 HM5241605 Series Command Intervals (cont) 2. · Read command to Precharge command interval (same bank): Same bank, different ROW address: When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. Different bank: To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to precharge command execution. When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 1, Burst Length = 4 CLK Command READ A Dout PRECHARGE out A0 out A1 out A2 out A3 l EP = 0 cycle CL=1 CAS Latency = 2, Burst Length = 4 CLK Command READ A PRECHARGE Dout out A0 CL=2 out A1 out A2 out A3 l EP = -1 cycle 27 HM5241605 HM5241605 Series Command Intervals (cont) CAS Latency = 3, Burst Length = 4 CLK Command READ A PRECHARGE Dout out A0 out A1 CL=3 out A2 out A3 l EP = -2 cycle READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 1, Burst Length = 1, 2, 4, 8 CLK Command READ A PRECHARGE High-Z Dout out A0 l HZP =1 CAS Latency = 2, Burst Length = 1, 2, 4, 8 CLK Command READ A PRECHARGE High-Z Dout out A0 l HZP =2 CAS Latency = 3, Burst Length = 1, 2, 4, 8 CLK Command READ A PRECHARGE High-Z Dout out A0 l HZP =3 28 HM5241605 HM5241605 Series Command Intervals (cont) · Write command to Precharge command interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMU and DQML for assurance of the cycle defined by tRWL. When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command WRITE A PRECHARGE DQMU/DQML Din t RWL CLK Command WRITE A PRECHARGE DQMU/DQML Din in A0 in A1 t RWL Burst Length = 4 (To write all data) CLK Command WRITE A PRECHARGE DQMU/DQML Din in A0 in A1 in A2 in A3 t RWL 29 HM5241605 HM5241605 Series Command Intervals (cont) 2. · Bank active command interval 1. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Same bank: The interval between the two bank-active commands must be no less than tRC. Bank active to bank active for same bank CLK Command ACTIVE ACTIVE Address (A0-A8) ROW ROW BS (A9) t RC Bank 0 Active Bank 0 Active Bank active to bank active for different bank CLK Command Address (A0-A8) ACTIVE 0 ACTIVE 1 ROW:0 ROW:1 BS (A9) t RRD Bank 0 Active 30 Bank 1 Active HM5241605 HM5241605 Series Command Intervals (cont) · Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA. CLK Command MRS Address (A0-A9) ACTIVE CODE BS & ROW t RSA Mode Register Set Bank Active 31 HM5241605 HM5241605 Series DQM Control · Writing: The DQML and DQMU mask the lower and upper bytes of the I/O data, respectively. The timing of DQML/DQMU is different during reading and writing. Input data can be masked by DQML/DQMU. By setting DQML/DQMU to Low, data can be written. In addition, when DQML/DQMU is set to High, the corresponding data is not written, and the previous data is held. The latency of DQML/DQMU during writing is 0. · Reading: When data is read, the output buffer can be controlled by DQML/DQMU. By setting DQML/DQMU to Low, the output buffer becomes Low-Z, enabling data output. By setting DQML/DQMU to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQML/DQMU during reading is 2. Reading CLK DQMU/L I/O(output) High-Z out 0 out 1 out 3 lDOD = 2 Latency Writing CLK DQMU/L I/O(input) in 0 in 3 in 1 l DID = 0 Latency 32 HM5241605 HM5241605 Series Refresh · Clock suspend mode By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". · Auto-refresh All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the interval counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 1,024 cycles/16 ms. (1,024 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. · Power-up sequence HM5241605 HM5241605 series has two types of power-up sequence. Hitachi recommends that the DQML/DQMU and the CKE are set to High to ensure output to be in the high impedance and to prevent from bus contention. · Self-refresh 1. After executing a self-refresh command, the selfrefresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a selfrefresh exit command. After the self-refresh, since it is impossible to determine the address of the last ROW to be refreshed, an auto-refresh should immediately be performed for all addresses (1,024 cycles). Others · Power-down mode The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. During power-up sequence, the DQML/ DQMU and the CKE must be set to High. When 100 µs has past after power on, all banks must be precharged using the precharge command. After tRP delay, set the mode register. And after tRSA delay, execute two or more cycles of auto-refresh operation as dummy, an interval of tRC is required between two auto-refresh commands. 2. During power-up sequence, the DQML/ DQMU and the CKE must be set to High. When 200 µs has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. 33 HM5241605 HM5241605 Series Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT ­1.0 to +5.5 V 1 Supply voltage relative to VSS VCC ­1.0 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg ­55 to +125 °C Note: 1. VIH (max) = 5.75 V for pulse width 5 ns Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Max Unit Note Supply voltage VCC, VCCQ 3.0 3.6 V 1 VSS, VSSQ 0 0 V Input high voltage VIH 2.0 5.5 V 1, 2 Input low voltage VIL ­0.3 0.8 V 1, 3 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.75 V for pulse width 5 ns 3. VIL (min) = ­1.0 V for pulse width 5 ns 34 HM5241605 HM5241605 Series DC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) HM5241605 HM5241605 -15 -17 -20 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current ICC1 - 85 - 75 - 70 mA Burst length=1 tRC = min 1, 2, 4 Standby current ICC2 - 3 - 3 - 3 mA CKE=VIL, tCK = min 5 - 2 - 2 - 2 mA 6 CKE=VIL CLK=VIL or VIH Fixed - 33 - 30 - 26 mA CKE=VIH, NOP command tCK = min 3 - 7 - 7 - 7 mA CKE=VIL, tCK = min, I/O=High-Z 1, 2 - 34 - 31 - 26 mA 1, 2, 3 CKE=VIH, NOP command tCK = min, I/O = High-Z ICC4 - - - 65 - 100 - 105 - 60 95 95 - - - 50 80 85 mA mA mA tCK = min BL = 4 Auto refresh current ICC5 - 70 - 65 - 60 mA tRC = min Self refresh current ICC6 - 2 - 2 - 2 mA VIH VCC ­ 0.2 VIL 0.2 V Input leakage current ILI ­10 10 ­10 10 ­10 10 µA 0 Vin VCC Output leakage current ILO ­10 10 ­10 10 ­10 10 µA 0 Vout VCC I/O = disable Output high voltage VOH 2.4 - 2.4 - 2.4 - V IOH = ­2 mA Output low voltage VOL - 0.4 - 0.4 - 0.4 V IOL = 2 mA (Bank Disable) Active standby current (Bank active) Burst operating current (CL=1) (CL=2) (CL=3) ICC3 1, 2, 4 7 Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode set, CLK operating current. 6. After power down mode set, no CLK operating current. 7. After self refresh mode set, self refresh current. 35 HM5241605 HM5241605 Series Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 - 5 pF 1, 3 Input capacitance (Signals) CI2 - 5 pF 1, 3 Output capacitance (I/O) CO - 7 pF 1, 2, 3 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMU/L = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) HM5241605 HM5241605 -15 -17 -20 Parameter Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CL=1) (CL=2, 3) tCK 30 15 - - 35 17.5 - - 40 20 - - ns ns 1 CLK high pulse width tCKH 6 - 7 - 8 - ns 1 CLK low pulse width tCKL 6 - 7 - 8 - ns 1 Access time from CLK (CL=1) (CL=2) (CL=3) tAC - - - 30 15 13 - - - 34 16.5 15.5 - - - 38 18 18 ns ns ns 1, 2 1, 2 1, 2 Read command to data valid time (CL=1, 2) (CL=3) tACK - - 30 43 - - 34 50.5 - - 38 58 ns ns 1 1 Data-out hold time (CL=1) (CL=2, 3) tOH 4 2 - - 4 2 - - 4 2 - - ns ns 1, 2 CLK to Data-out low impedance tLZ 0 - 0 - 0 - ns 1, 2 CLK to Data-out high impedance tHZ 4 2 15 10 4 2 17 12 4 2 19 14 ns ns 1, 3 (CL=1) (CL=2, 3) Data-in setup time tDS 4 - 4 - 4 - ns 1 Data in hold time tDH 2 - 2 - 2 - ns 1 Address setup time tAS 4 - 4 - 4 - ns 1 Address hold time tAH 2 - 2 - 2 - ns 1 CKE setup time tCES 4 - 4 - 4 - ns 1 CKE setup time for power down exit tCESP 13 - 15 - 17 - ns 1 CKE hold time tCEH 2 - 2 - 2 - ns 1 Command (CS, RAS, CAS, WE, DQM) setup time tCS 4 - 4 - 4 - ns 1 Command (CS, RAS, CAS, WE, DQM) hold time tCH 2 - 2 - 2 - ns 1 Ref/Active to Ref/Active command period tRC 110 - 120 - 130 - ns 1 36 HM5241605 HM5241605 Series AC Characteristics (Ta = 0 to 70 °C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) (cont) HM5241605 HM5241605 -15 Parameter Symbol -17 Min -20 Min Max Max Min Max Unit Notes Active to Precharge command period tRAS 70 10000 75 10000 80 10000 ns 1 Active to precharge on full page mode tRASC - 80000 - 80000 - 80000 ns 1 Active command to column command tRCD (same bank) 30 - 35 - 40 - ns 1 Precharge to active command period tRP 34 - 34 - 40 - ns 1 The last data-in to Precharge lead time tRWL 30 - 35 - 40 - ns 1 Active (a) to Active (b) command period tRRD 30 - 35 - 40 - ns 1 Register set to active command tRSA 30 - 35 - 40 - ns 1 Transition time (rise to fall) tT 1 5 1 5 1 5 ns Refresh period tREF - 16 - 16 - 16 ms Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.40 V. 2. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source. 3. tHZ (max) defines the time at which the outputs achieves ± 200 mV. Load condition is CL = 5 pF with current source. 4. tCES define CKE setup time to CKE rising edge except power down exit command. HM5241605 HM5241605 (LVTTL) 2.8 V 80% input I/O 500 20% V SS +1.4 V CL t T tT 37 HM5241605 HM5241605 Series Relationship Between Frequency and Minimum Latency HM5241605 HM5241605 Parameter Frequency (MHz) tCK (ns) -15 -17 -20 Symbol 66 15 33 30 57 28.5 50 17.5 35 20 25 40 Active command to column command (same bank) tRCD 2 1 2 1 2 1 Active command to active command (same bank) tRC 8 5 7 4 7 4 Active command to precharge command tRAS (same bank) 5 3 5 3 4 2 Precharge command to active command tRP (same bank) 3 2 2 1 2 1 Last data input to precharge command (same bank) tRWL 2 1 2 1 2 1 Active command to active command (different bank) tRRD 2 1 2 1 2 1 Last data in to active command (Auto precharge, same bank) lAPW 5 3 4 2 4 2 = [tRWL + tRP] Self refresh exit to command input lSEC 8 4 7 4 7 4 = [tRC] Precharge command to high impedance (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) lHZP 3 2 - 3 2 1 3 2 - 3 2 1 3 2 - 3 2 1 Last data out to active command (auto precharge) (CAS latency = 2, 3) (same bank) (CAS latency = 1) lAPR 2 - 1 2 1 - 0 1 1 - 0 1 Last data out to precharge (early precharge) (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) lEP ­2 ­1 - ­2 ­1 0 ­2 ­1 - ­2 ­1 0 ­2 ­1 - ­2 ­1 0 Column command to column command lCCD 1 1 1 1 1 1 Write command to data in latency lWCD 0 0 0 0 0 0 DQM to data in lDID 0 0 0 0 0 0 DQM to data out lDOD 2 2 2 2 2 2 CKE to CLK disable lCLE 1 1 1 1 1 1 Register set to active command tRSA 2 1 2 1 2 1 CS to command disable lCDD 0 0 0 0 0 0 Power down exit to command input lPEC 1 1 1 1 1 1 Burst stop to output valid data hold (CAS latency = 1) (CAS latency = 2) (CAS latency = 3) lBSR - 1 2 0 1 2 - 1 2 0 1 2 - 1 2 0 1 2 38 Notes = [tRAS + tRP] = [tRP] ­ 1 = [tRP] HM5241605 HM5241605 Series Relationship Between Frequency and Minimum Latency (cont) HM5241605 HM5241605 Parameter Frequency (MHz) tCK (ns) -15 -17 -20 Burst stop to output high impedance (CAS latency = 1) (CAS latency = 2) (CAS latency = 3) lBSW 33 30 57 28.5 50 17.5 35 20 25 40 1 2 3 - 2 3 1 2 3 - 2 3 1 2 3 1 1 1 1 1 1 Notes lBSH Burst stop to write data ignore 66 15 - 2 3 Symbol Note: 1. tRCD to tRRD are recommended value. 2. CL = CAS latency. 39 HM5241605 HM5241605 Series Timing Waveforms Read Cycle tCK t CKH t CKL CLK t RC VIH CKE t CS t CH t RP t RAS t RCD t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CS t CS t CH t CS t CH RAS t CS t CH t CS t CH CAS t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t CS t CH t AS t AH t CS t CH WE t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH Address t CH t CS DQMU/L I/O(input) t AC tACK I/O(output) t AC t AC Bank 0 Active 40 t AC Bank 0 Read t LZ t OH t OH t OH Bank 0 Precharge t HZ Burst length = 4 Bank0 Access HM5241605 HM5241605 Series Write Cycle t CK t CKH t CKL CLK t RC VIH CKE t RAS t RCD t CS t CH t RP t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CS t CS t CH t CS t CH RAS t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS t CH t AS t AH WE t AS t AH t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH Address t CS t CH DQMU/L t DS t DH tDS t DH t DS t DH t DS t DH I/O(input) t RWL I/O(output) Bank 0 Active Bank 0 Write Bank 0 Precharge Burst length = 4 Bank 0 Access 41 HM5241605 HM5241605 Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK VIH CKE CS RAS CAS WE A9(BS) Address code valid C: b' C: b R: b DQMU/L I/O(output) b+3 b b' b'+1 b'+2 b'+3 High-Z I/O(input) t RSA t RP Precharge If needed Mode register Set t RCD Output mask Bank 1 Active tRCD = 3 CAS latency = 3 Burst length = 4 Bank 1 Read Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 VIH CS RAS CAS WE A9(BS) Address DQMU/L I/O (output) I/O (input) CKE R:a C:a R:b C:b a C:b' a+1 a+2 a+3 b C:b" b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Read Bank 1 Precharge Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 VIH CS RAS CAS WE A9(BS) Address DQMU/L R:a R:b C:b C:b' C:b" High-Z I/O (output) I/O (input) a Bank 0 Active 42 C:a Bank 0 Write a+1 a+2 a+3 Bank 1 Active b Bank 1 Write b+1 b+2 b+3 b' Bank 0 Precharge Bank 1 Write b'+1 b" Bank 1 Write b"+1 b"+2 b"+3 Bank 1 Precharge HM5241605 HM5241605 Series Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A9(BS) R:a Address C:a R:b DQMU/L I/O (input) I/O (output) a a Bank 0 Active CKE C:a' C:a Bank 0 Read C:a a+1 a+2 a+3 Bank 1 Active R:b a Bank 0 Bank 0 Write Read a+1 a+2 a+3 Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) Address DQMU/L I/O (input) I/O (output) R:a C:a a a Bank 0 Active Bank 0 Read Bank 1 Active a+1 C:b C:c b c a+3 Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 43 HM5241605 HM5241605 Series Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A9(BS) R:a Address DQMU/L I/O (input) I/O (output) CKE C:a R:b C:a' a a Bank 0 Active Bank 0 Read Clock suspend Bank 1 Active C:a a+1 a+2 a+3 a+1 a+2 a+3 R:b Bank 0 Write Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) Address DQMU/L R:a I/O (input) I/O (output) C:a a a Bank 0 Active Bank 0 Read Bank 1 Active a+1 a+1 a+2 a+3 a+3 Bank 0 Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 44 HM5241605 HM5241605 Series Full Page Read/Write Cycle 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CKE Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page VIH CS RAS CAS WE A9(BS) Address DQMU/L I/O (output) I/O (input) CKE R:a C:a R:b a a+1 a+2 a+3 a-2 a-1 a a+1 a+2 a+3 a+4 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Burst stop Bank 1 Precharge VIH Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page CS RAS CAS WE A9(BS) Address DQMU/L R:a C:a R:b High-Z I/O (output) I/O (input) a Bank 0 Active Bank 0 Write a+1 a+2 Bank 1 Active a+3 a+4 a+5 a+6 a+1 a+2 a+3 a+4 a+5 a+6 Burst stop Bank 1 Precharge 45 HM5241605 HM5241605 Series Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK CKE VIH CS RAS CAS WE A9(BS) Address R:a A8=1 C:a DQMU/L I/O(input) High-Z I/O(output) t RC t RP Auto Refresh Precharge If needed tRC Active Bank 0 Auto Refresh Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 Auto refresh Self refresh cycle RAS-CAS delay=3 CAS latency=3 Burst length=4 Self Refresh Cycle CLK CKE Low CKE CS RAS CAS WE A9(BS) Address A8=1 DQMU/L I/O(input) High-Z I/O(output) tRP Precharge command If needed 46 tRC Self refresh entry command Self refresh exit ignore command or No operation HM5241605 HM5241605 Series Clock Suspend Mode t CESP 0 1 2 3 4 5 t CES t CEH 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 RAS CAS WE A9(BS) Address R:a C:a R:b DQMU/L I/O (output) I/O (input) a C:b a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end Bank1 Read Bank0 Precharge Earliest Bank1 Precharge CKE CS RAS Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 CAS WE A9(BS) Address DQMU/L R:a C:a R:b C:b High-Z I/O (output) I/O (input) a Bank0 Active Active clock suspend start a+1 a+2 Active clock Bank0 Bank1 supend end Write Active Write suspend start a+3 Write suspend end b b+1 b+2 b+3 Bank1 Bank0 Write Precharge Earliest Bank1 Precharge 47 HM5241605 HM5241605 Series Power Down Mode CLK CKE Low CKE CS RAS CAS WE A9(BS) Address R: a A8=1 DQMU/L I/O(input) High-Z I/O(output) tRP Precharge command If needed 48 Power down entry Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay=3 CAS latency=3 Burst length=4 HM5241605 HM5241605 Series Power Up Sequence (1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE VIH CS RAS CAS WE DQMU/L code valid Address Valid VIH High-Z I/O t RP All banks Precharge t RC t RSA tRC Auto Refresh Mode register Set Bank active If needed Auto Refresh Power Up Sequence (2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE VIH CS RAS CAS WE DQMU/L code valid Address Valid VIH High-Z I/O t RP All banks Precharge t RC Auto Refresh t RSA tRC Auto Refresh Mode register Set Bank active If needed 49 HM5241605SOJ HM5241605SOJ Series Preliminary 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM Rev. 0.0 Mar. 10, 1995 All inputs and outputs are referred to the rising edge of the clock input. The HM5241605 HM5241605 is offered in 2 banks for improved performance. Features · 3.3V Power supply · Clock frequency 66 MHz/57 MHz/50 MHz · LVTTL interface · Single pulsed RAS · 2 Banks can operates simultaneously and independently · Burst read/write operation and burst read/ single write operation capability · Programmable burst length 1/2/4/8/full page · Programmable burst sequence Sequential/interleave · Full page burst length capability Sequential burst burst stop capability · Programmable CAS latency 1/2/3 · Byte control by DQMU and DQML · 1024 refresh cycles: 16 ms · 2 variations of refresh - Auto refresh - Self refresh Ordering Information Type No. Frequency Package -­ HM5241605J-20 HM5241605J-20 50 MHz 400-mil 50-pin HM5241605J-17 HM5241605J-17 57 MHz plastic SOJ HM5241605J-15 HM5241605J-15 66 MHz (CP-50D CP-50D) -­ Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. ADE-203-356 ADE-203-356(Z) HM5241605SOJ HM5241605SOJ Series Pin Arrangement Pin Description HM5241605J HM5241605J Series VCC VSS I/O0 I/O15 I/O15 I/O1 I/O14 I/O14 VSSQ VSSQ I/O2 I/O13 I/O13 I/O3 I/O12 I/O12 VCCQ VCCQ I/O4 I/O11 I/O11 I/O5 I/O10 I/O10 VSSQ VSSQ I/O6 I/O9 I/O7 I/O8 VCCQ VCCQ DQML NC WE DQMU CAS CLK RAS CKE CS NC A9 NC A8 NC A0 A7 A1 A6 A2 A5 A3 Pin name Function -­ A0 ­ A9 Address input ­ Row address A0 ­ A8 ­ Column address A0 ­ A7 ­ Bank select address A9 -­ I/O0 ­ I/O15 I/O15 Data-input/output -­ CS Chip select -­ RAS Row address strobe command -­ CAS Column address strobe command -­ WE Write enable command -­ DQMU Upper byte input/output mask DQML Lower byte input/output mask -­ CLK Clock input -­ CKE Clock enable -­ VCC Power for internal circuit (3.3 V) -­ VSS Ground for internal circuit -­ VCCQ Power for I/O pin (3.3 V) -­ VSSQ Ground for I/O pin -­ NC No connection -­ A4 VCC VSS (Top View) 2 HM5241605SOJ HM5241605SOJ Series Block Diagram A0 ­ A9 A0 ­ A7 Column address counter A0 ­ A9 Column address buffer 512 row X 256 column X 16 bit Input buffer Sense amplifier & I/O bus Bank 0 Row decoder Column decoder Memory array Bank 1 512 row X 256 column X 16 bit Output buffer Control logic & timing generator DQMU DQML WE CAS RAS CS CKE I/O0 ­ I/O15 I/O15 CLK Sense amplifier & I/O bus Column decoder Row decoder Memory array Refresh counter Row address buffer 3 HM5241605SOJ HM5241605SOJ Series Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A8 defines the precharge mode. When A8 = High at the precharge command cycle, both banks are precharged. But when A8 = Low at the precharge command cycle, only the bank that is selected by A9(BS) is precharged. DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers. Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the output buffer becomes Low-Z. Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If DQMU/DQML is Low, the data is written. I/O0 to I/O15 I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM. VCC and VCCQ (power supply pins): 3.3 V is applied. (V CC is for the internal circuit and VCCQ is for the output buffer.) VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) A9 (input pin): A9 is a bank select signal (BS). The memory array of the HM5241605 HM5241605 is divided into bank 0 and bank 1, both which contain 512 row x 256 column x 16 bits. If A9 is Low, bank 0 is selected, and if A9 is High, bank 1 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. 4 HM5241605SOJ HM5241605SOJ Series Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the address pins. CS, RAS, CAS, WE and CKE A7 Function Symbol n-1 n CS RAS CAS WE A9 A8 -0 - Ignore command DESL H X H X X X X X X - No operation NOP H X L H H H X X X - Burst stop in full page BST H X L H H L X X X - Column address and read command READ H X L H L H V L V - Read with auto-precharge READ A H X L H L H V H V - Column address and write command WRIT H X L H L L V L V - Write with auto-precharge WRIT A H X L H L L V H V - Row address strobe and bank act. ACTV H X L L H H V V V - Precharge select bank PRE H X L L H L V L X - Precharge all bank PALL H X L L H L X H X - Refresh REF/SELF H V L L L H X X X - Mode register set MRS H X L L L L L L V - Note: H: VIH. L: VIL. X: VIH or VIL. V: Valid address input ·Ignore command [DESL]: When this command is set ( CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. ·No operation [NOP]: This command is not an execution command. However, the internal operations continue. ·Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page(256), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a fullpage of data (256), it automatically returns to the start address, and input/output is performed repeatedly. ·Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0-AY7) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. ·Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is fullpage(256), this command is illegal. 5 HM5241605SOJ HM5241605SOJ Series ·Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A9) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7) and the bank select address (A9). ·Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page(256), this command is illegal. ·Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A9(BS) and determines the row address (AX0-AX8). When A9 is Low, bank 0 is activated. When A9 is High, bank 1 is activated. ·Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A9. If A9 is Low, bank 0 is selected. If A9 is High, bank 1 is selected. ·Precharge all banks [PALL]: This command starts a precharge operation for all banks. ·Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. ·Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0-A9) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. DQM Truth Table CKE DQM Function Symbol n-1 n U L -­ Upper byte write enable/output enable ENBU H X L X -­ Lower byte write enable/output enable ENBL H X X L -­ Upper byte write inhibit/output disable MASKU H X H X -­ Lower byte write inhibit/output disable MASKL H X X H -­ Note: H: VIH. L: VIL. X: VIH or VIL. The HM5241605 HM5241605 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5241605 HM5241605 operating instructions. 6 HM5241605SOJ HM5241605SOJ Series CKE Truth Table CKE Current state Function n-1 n CS RAS CAS WE Address -­ Active Clock suspend mode entry H L X X X X X -­ Any Clock suspend L L X X X X X -­ Clock suspend Clock suspend mode exit L H X X X X X -­ Idle Auto-refresh command REF H H L L L H X -­ Idle Self-refresh entry SELF H L L L L H X -­ Idle Power down entry H L L H H H X - H L H X X X X -­ Self refresh Self refresh exit SELFX L H L H H H X - L H H X X X X -­ Power down Power down exit L H L H H H X - L H H X X X X -­ Note: H: VIH. L: VIL. X: VIH or VIL. ·Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ·ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. ·READ suspend and READ A suspend: The data being output is held (and continues to be output). ·WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. ·IDLE: In this state, all banks are not selected, and completed precharge operation. ·Auto-refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 1,024 times are required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. ·Clock suspend: During clock suspend mode, keep the CKL to Low. ·Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. 7 HM5241605SOJ HM5241605SOJ Series ·Self-refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. ·Self-refresh exit: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state. ·Power down exit: When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state. ·Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state CS RAS CAS WE Address Command Operation -­ Precharge H X X X X DESL Enter IDLE after tRP - L H H H X NOP Enter IDLE after tRP - L H H L X BST ILLEGAL - L H L H BA, CA, A8 READ/READ A ILLEGAL - L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL - L L H H BA, RA ACTV ILLEGAL - L L H L BA, A8 PRE, PALL ILLEGAL - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL -­ Idle H X X X X DESL NOP - L H H H X NOP NOP - L H H L X BST NOP - L H L H BA, CA, A8 READ/READ A ILLEGAL - L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL - L L H H BA, RA ACTV Bank and row active - L L H L BA, A8 PRE, PALL NOP - L L L H X REF, SELF Refresh - L L L L MODE MRS Mode register set -­ 8 HM5241605SOJ HM5241605SOJ Series Function Truth Table (cont.) Current state CS RAS CAS WE Address Command Operation -­ Row active H X X X X DESL NOP - L H H H X NOP NOP - L H H L X BST NOP - L H L H BA, CA, A8 READ/READ A Begin read - L H L L BA, CA, A8 WRIT/WRIT A Begin write - L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank - L L H L BA, A8 PRE, PALL Precharge - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL - Read H X X X X DESL Continue burst to end - L H H H X NOP Continue burst to end - L H H L X BST Burst stop to full page - L H L H BA, CA, A8 READ/READ A Continue burst read to CAS latency and New read - L H L L BA, CA, A8 WRIT/WRIT A Term burst read/start write - L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank - L L H L BA, A8 PRE, PALL Term burst read and Precharge - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL -­ 9 HM5241605SOJ HM5241605SOJ Series Function Truth Table (cont.) Current state CS RAS CAS WE Address Command Operation -­ Read with H X X X X DESL Continue burst to end auto-precharge and precharge - L H H H X NOP Continue burst to end and precharge - L H H L X BST ILLEGAL - L H L H BA, CA, A8 READ/READ A ILLEGAL - L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL - L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank - L L H L BA, A8 PRE, PALL ILLEGAL - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL - Write H X X X X DESL Continue burst to end - L H H H X NOP Continue burst to end - L H H L X BST Burst stop on full page - L H L H BA, CA, A8 READ/READ A Term burst and New read - L H L L BA, CA, A8 WRIT/WRIT A Term burst and New write - L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank - L L H L BA, A8 PRE, PALL Term burst write and Precharge*2 - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL -­ 10 HM5241605SOJ HM5241605SOJ Series Function Truth Table (cont.) Current state CS RAS CAS WE Address Command Operation -­ Write with H X X X X DESL Continue burst to end auto-precharge and precharge - L H H H X NOP Continue burst to end and precharge - L H H L X BST ILLEGAL - L H L H BA, CA, A8 READ/READ A ILLEGAL - L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL - L L H H BA, RA ACTV Other bank active*3 ILLEGAL on same bank - L L H L BA, A8 PRE, PALL ILLEGAL - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL - Refresh (auto-refresh) H X X X X DESL Enter IDLE after tRC - L H H H X NOP Enter IDLE after tRC - L H H L X BST Enter IDLE after tRC - L H L H BA, CA, A8 READ/READ A ILLEGAL - L H L L BA, CA, A8 WRIT/WRIT A ILLEGAL - L L H H BA, RA ACTV ILLEGAL - L L H L BA, A8 PRE, PALL ILLEGAL - L L L H X REF, SELF ILLEGAL - L L L L MODE MRS ILLEGAL -­ Note 1. H: VIH. L: VIL. X: VIH or VIL. The other combinations are inhibit. 2. An interval of tRWL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 11 HM5241605SOJ HM5241605SOJ Series From [PRECHARGE] To [DESL], [NOP] or [BST]:When these commands are executed, the synchronous DRAM enters the IDLE state after t RP has elapsed from the completion of precharge. From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or selfrefresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of t RCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t RCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of tRAS is required.) From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. From [READ with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. 12 HM5241605SOJ HM5241605SOJ Series From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a fullpage burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]:This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank activ. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an autorefresh cycle (after t RC ), the synchronous DRAM automatically enters the IDLE state. 13 HM5241605SOJ HM5241605SOJ Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE CLOCK SUSPEND CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE READ WRITE WITH AP READ WRITE CKE READ WITH AP WRITE WITH AP WRITEA CKE_ READ CKE CKE POWER ON READ SUSPEND READ WITH AP CKE_ READA CKE PRECHARGE POWER APPLIED WRITE WITH AP Read PRECHARGE CKE_ WRITEA SUSPEND READ WITH AP READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 14 HM5241605SOJ HM5241605SOJ Series Mode Register Configuration The mode register is set by the input to the address pins (A0 to A9) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. ·A7 Keep this bit Low at the mode register set cycle. ·A6, A5, A4: (LMODE) These pins specify the CAS latency. ·A9 and A8: (OPCODE) The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. ·A3: (BT) A burst type is specified. When full-page burst is performed, only "sequential" can be selected. ·A2, A1, A0: (BL) These pins specify the burst length. ·Burst read and BURST WRITE Burst write is performed for the specified burst length starting from the column address specified in the write cycle. ·Burst read and SINGLE WRITE Data is only written to the column address specified during the write cycle, regardless of the burst length. A9 A8 A7 OPCODE A6 0 A5 A4 LMODE A3 A2 BT A6 A5 A4 CAS Latency A1 A0 BL A3 Burst Type A2 A1 A0 0 0 0 R 0 Sequential 0 0 1 1 1 0 1 0 2 0 1 1 3 0 1 X X R 0 Interleave Burst Length BT=0 BT=1 0 0 0 1 0 0 1 2 2 1 0 4 4 1 1 8 8 1 1 A9 A8 0 0 Write mode Burst read and burst write R 0 0 R R 1 0 1 R R 1 1 0 R R 1 1 1 F.P. R 0 1 1 0 Burst read and SINGLE WRITE F.P. =Full Page (256) 1 1 R is Reserved(inhibit) R 15 HM5241605SOJ HM5241605SOJ Series Burst Sequence Burst length = 2 Stating Ad. A0 Burst length = 4 Addressing(decimal) Sequence Interleave Stating Ad. A1 A0 Addressing(decimal) Sequence Interleave 0 0, 1, 0, 1, 0 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 0, 1, 0, 0 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Burst length = 8 Addressing(decimal) Stating Ad. A2 A1 A0 Sequence Interleave 0 0 0 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, 16 HM5241605SOJ HM5241605SOJ Series Operation of HM5241605 HM5241605 Series Read/Write Operations ·Bank active Before executing a read or write operation