HM-6518 HM16518B-9 HM16518-9 HM-6518B-9 HM-6518-9 ISO9000

1024 x 1 CMOS RAM March 1997 Features Description · Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW

HM-6518 HM-6518 1024 x 1 CMOS RAM March 1997 Features Description · Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max The HM-6518 HM-6518 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. · Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max · Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min · TTL Compatible Input/Output · High Output Drive - 2 TTL Loads · High Noise Immunity On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518 HM-6518 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed overtemperature. · On-Chip Address Register · Two-Chip Selects for Easy Array Expansion · Three-State Output Ordering Information PACKAGE TEMP. RANGE 180ns CERDIP -40oC to +85oC HM16518B-9 HM16518B-9 250ns HM16518-9 HM16518-9 PKG. NO. F18.3 Pinout HM-6518 HM-6518 (CERDIP) TOP VIEW S1 1 18 VCC E 2 17 S2 A0 3 16 D A1 4 15 W A2 5 14 A9 A3 6 13 A8 A4 7 12 A7 Q 8 11 A6 GND 9 10 A5 PIN DESCRIPTION A Address Input E Chip Enable W Write Enable S Chip Select D Data Input Q Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-1 File Number 2987.1 HM-6518 HM-6518 Functional Diagram A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A GATED ROW DECODER 32 x 32 MATRIX 32 5 G D 32 GATED COLUMN DECODER AND DATA I/O A D Q LATCH L 5 W A 5 A E LATCHED ADDRESS REGISTER S1, S2 A0 A1 A2 A3 A4 NOTES: 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Data latches: L high Q = D; Q Latches on rising edge of L. 4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E. 6-2 Q A HM-6518 HM-6518 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6518B-9 HM-6518B-9, HM-6518-9 HM-6518-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6518B-9 HM-6518B-9, HM-6518-9 HM-6518-9) LIMITS PARAMETER SYMBOL MIN MAX UNITS Standby Supply Current ICCSB - 10 µA IO = 0mA, VI = VCC or GND, VCC = 5.5V Operating Supply Current (Note 1) ICCOP - 4 mA E = 1MHz, IO = 0mA, VI = VCC or GND, VCC = 5.5V ICCDR - 5 µA - 10 µA VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC VCCDR 2.0 - V II -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V Output Leakage Current IOZ -1.0 +1.0 µA VO = VCC or GND, VCC = 5.5V Input Low Voltage VIL -0.3 0.8 V VCC = 4.5V Input High Voltage VIH VCC -2.0 VCC +0.3 V VCC = 5.5V Output Low Voltage VOL - 0.4 V IO = 3.2mA, VCC = 4.5V Output High Voltage VOH 2.4 - V IO = -0.4mA, VCC = 4.5V Data Retention Supply Current HM-6518B-9 HM-6518B-9 HM-6518-9 HM-6518-9 Data Retention Supply Voltage Input Leakage Current Capacitance TEST CONDITIONS TA = +25oC PARAMETER SYMBOL MAX UNITS Input Capacitance (Note 2) CI 6 pF Output Capacitance (Note 2) CO 10 pF NOTES: 1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. 6-3 TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND HM-6518 HM-6518 AC Electrical Specifications VCC = 5V ± 10%; TA = -40oC to +85oC (HM-6518B-9 HM-6518B-9, HM-6518-9 HM-6518-9) LIMITS HM-6518B-9 HM-6518B-9 HM-6518-9 HM-6518-9 SYMBOL MIN MAX MIN MAX UNITS TEST CONDITIONS Chip Enable Access Time (1) TELQV - 180 - 250 ns (Notes 1, 3) Address Access Time (2) TAVQV - 180 - 250 ns (Notes 1, 3, 4) Chip Select Output Enable Time (3) TSLQX 5 120 5 160 ns (Notes 2, 3) Write Enable Output Disable Time (4) TWLQZ - 120 - 160 ns (Notes 2, 3) Chip Select Output Disable Time (5) TSHQZ - 120 - 160 ns (Notes 2, 3) Chip Enable Pulse Negative Width (6) TELEH 180 - 250 - ns (Notes 1, 3) Chip Enable Pulse Positive Width (7) TEHEL 100 - 100 - ns (Notes 1, 3) Address Setup Time (8) TAVEL 0 - 0 - ns (Notes 1, 3) Address Hold Time (9) TELAX 40 - 50 - ns (Notes 1, 3) Data Setup Time (10) TDVWH 80 - 110 - ns (Notes 1, 3) Data Hold Time (11) TWHDX 0 - 0 - ns (Notes 1, 3) Chip Select Write Pulse Setup Time (12) TWLSH 100 - 130 - ns (Notes 1, 3) Chip Enable Write Pulse Setup Time (13) TWLEH 100 - 130 - ns (Notes 1, 3) Chip Select Write Pulse Hold Time (14) TSLWH 100 - 130 - ns (Notes 1, 3) Chip Enable Write Pulse Hold Time (15) TELWH 100 - 130 - ns (Notes 1, 3) Write Enable Pulse Width (16) TWLWH 100 - 130 - ns (Notes 1, 3) Read or Write Cycle Time (17) TELEL 280 - 350 - ns (Notes 1, 3) PARAMETER NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. 6-4 HM-6518 HM-6518 Timing Waveforms (9) TELAX (8) TAVEL A (8) TAVEL VALID NEXT TELEL TEHEL (17) TELEH (6) TEHEL (7) (7) E HIGH W D TELQV (1) TAVQV (2) Q HIGH Z PREVIOUS DATA HIGH Z VALID OUTPUT LATCHED TSHQZ (5) (5) TSLOX (3) S1, 1 S2 TSHQZ TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE TRUTH TABLE INPUTS OUTPUTS TIME REFERENCE E S1 W A D Q -1 H H X X X Z Memory Disabled X H V X Z Cycle Begins, Addresses are Latched 0 FUNCTION 1 L L H X X X Output Enabled 2 L L H X X V Output Valid L H X X V Output Latched H X X X Z Device Disabled, Prepare for Next Cycle (Same as -1) X H V X Z Cycle Ends, Next Cycle Begins (Same as 0) 3 4 5 H NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. In the HM-6518 HM-6518 read cycle the address information is latched into the on chip registers on the falling edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required hold time the addresses may change state without affecting device operation. In order for the output to be read S1, S2 and E must be low, W must be high. When E goes high, the output data is latched into an on chip register. Taking either or both S1 or S2 high, forces the output buffer to a high impedance state. The output data may be re-enabled at any time by taking S1 and S2 low. On the falling edge of E the data will be unlatched. 6-5 HM-6518 HM-6518 Timing Wavforms (Continued) (9) TELAX (8) TAVEL (8) TAVEL NEXT VALID A TELEL (17) TEHEL (7) TELEH (6) TEHEL (7) E TWLEH (13) TELWH (15) TWLWH (16) W TDVWH (10) TWHDX (11) VALID DATA D HIGH Z Q TSLWH (14) S1, S2 TWLSH (12) TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS OUTPUTS TIME REFERENCE E S1 W A D Q -1 H X X X X Z Memory Disabled X X V X Z Cycle Begins, Addresses are Latched L L X V Z Write Mode has Begun L X V Z Data is Written X X X X Z Write Completed X X X X Z Prepare for Next Cycle (Same as -1) X X V X Z Cycle Ends, Next Cycle Begins (Same as 0) 0 1 L 2 L 3 4 5 H FUNCTION NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. The write cycle is initiated by the falling edge of E which latches the address information into the on chip registers. The write portion of the cycle is defined as E, W, S1 and S2 being low simultaneously. W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is met. The write portion of the cycle is terminated by the first rising edge of either E, W, S1 or S2. Data setup and hold times must be referenced to the terminating signal. If a series of consecutive write cycles are to be performed, the W line may remain low until all desired locations have been written. When this method is used, data setup and hold times must be referenced to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH), various types of write cycles may be performed. If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TSLQX), a combination read write cycle is executed. Data may be modified an indefinite number of times during any write cycle (TELEH). The data input and data output pins may be tied together for use with a common I/O data bus structure. When using the RAM in this method, allow a minimum of one output disable time (TWLQZ) after W goes low before applying input data to the bus. This will ensure that the output buffers are not active. 6-6 HM-6518 HM-6518 Test Load Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 6-7 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029