HEF4526B HEF4526BP DIP16 HEF4526BT 076E07 MS-012 HEF4000B - Datasheet Archive

 

Programmable 4-bit binary down counter Rev. 04 - 21 September 2009 Product data sheet 1. General description The HEF4526B is a

 

HEF4526B HEF4526B Programmable 4-bit binary down counter Rev. 04 - 21 September 2009 Product data sheet 1. General description The HEF4526B HEF4526B is a synchronous programmable 4-bit binary down counter with active HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master reset input (MR) and a decoded TC output that can be used for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required. Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is highly tolerant of slower clock rise and fall times due to Schmitt trigger action. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is suitable for use over the full industrial (-40 °C to +85 °C) temperature range. 2. Features I I I I I Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range -40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications I Industrial HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 4. Ordering information Table 1. Ordering information All types operate from -40 °C to +85 °C. Type number Package Name Description Version HEF4526BP HEF4526BP DIP16 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4526BT HEF4526BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 5. Functional diagram 3 5 11 14 2 PL A0 A1 A2 A3 PARALLEL LOAD CIRCUITRY CD/SD 6 CP0 CP 4 CP1 BINARY DOWN COUNTER CD Q3 1 Q2 15 Q1 9 10 MR Q0 7 TC 12 ZERO DETECTOR 13 CF 001aae719 Fig 1. Functional diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP0 input CP1 input MR input Q0 Q1 Q2 Q3 001aak014 Fig 2. Timing diagram HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 2 of 18 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Q0 A1 Q1 A2 Q2 A3 NXP Semiconductors HEF4526B HEF4526B_4 Product data sheet A0 Q3 PL MR Rev. 04 - 21 September 2009 CD1 CD2 O FF T 1 O SD CD1 CD2 O FF T 2 O SD CD1 CD2 O FF T 3 O SD CD1 CD2 O FF T 4 O SD CP1 CP0 TC 001aae722 Logic diagram 3 of 18 © NXP B.V. 2009. All rights reserved. HEF4526B HEF4526B Fig 3. Programmable 4-bit binary down counter CF HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 6. Pinning information 6.1 Pinning HEF4526B HEF4526B Q3 1 16 VDD A3 2 15 Q2 PL 3 14 A2 CP1 4 13 CF A0 5 12 TC CP0 6 11 A1 Q0 7 10 MR VSS 8 9 Q1 001aae720 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description A0 to A3 5, 11, 14, 2 parallel input PL 3 parallel load input CP0 6 clock input (LOW-to-HIGH, triggered) CP1 4 clock input (HIGH-to-LOW, triggered) CF 13 cascade feedback input MR 10 asynchronous master reset input TC 12 terminal count output Q0 to Q3 7, 9, 15, 1 buffered parallel output VDD 16 supply voltage VSS 8 ground (0 V) HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 4 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 7. Functional description Table 3. Function table[1] MR PL CP0 CP1 Mode H X X X reset (asynchronous) L H X X preset (asynchronous) L L H no change L L L no change L L X no change L L X no change L L L counter advances L L H counter advances [1] H = HIGH voltage level; L = LOW voltage level; X = don't care; = positive-going transition; = negative-going transition. Table 4. Counting mode CF = HIGH; PL = LOW; MR = LOW. Count Outputs Q3 Q2 Q1 Q0 15 H H H H 14 H H H L 13 H H L H 12 H H L L 11 H L H H 10 H L H L 9 H L L H 8 H L L L 7 L H H H 6 L H H L 5 L H L H 4 L H L L 3 L L H H 2 L L H L 1 L L L H 0 L L L L HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 5 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 5. Single stage operation Divide-by-n; MR = LOW; CF = HIGH; CP1 = LOW. PL A3 A2 A1 A0 L X X X TC H H H X TC H H H L 14 TC H H L H 13 TC H H L L 12 TC H L H H 11 TC H L H L 10 TC H L L H 9 TC H L L L 8 TC L H H H 7 TC L H H L 6 TC L H L H 5 TC L H L L 4 TC L L H H 3 TC L L H L 2 TC L L L H 1 TC L L L L no operation 1 TC output pulse width 16 one clock period H 0 Divide by 15 clock pulse HIGH 2 3 4 15 5 14 6 13 7 12 11 10 9 8 001aae721 Fig 5. State diagram HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 6 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI output clamping current II/O Min VI < -0.5 V or VI > VDD + 0.5 V input/output current IDD supply current Tstg V ±10 - VO < -0.5 V or VO > VDD + 0.5 V Unit +18 -0.5 mA VDD + 0.5 V - ±10 mA ±100 mA -65 ambient temperature mA - to any supply terminal ±10 - storage temperature Tamb Max -0.5 input voltage IOK Conditions +150 °C P power dissipation +85 °C DIP16 DIP16 package - 750 mW SO16 package total power dissipation Ptot -40 [1] [2] - 500 mW - 100 mW per output [1] For DIP16 DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 °C t/V input transition rise and fall rate VCC = 5 V - - 3.75 µs/V VCC = 10 V - - 0.5 µs/V VCC = 15 V - - 0.08 µs/V HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 7 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 10. Static characteristics Table 8. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = -40 °C Min |IO| < 1 µA Tamb = 85 °C Min Min Max Unit Max 3.5 - V 7.0 - V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V - 3.0 - 3.0 - 3.0 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA HIGH-level output current VO = 2.5 V 5V -1.7 - -1.4 - -1.1 - mA VO = 4.6 V 5V -0.52 - -0.44 - -0.36 - mA VO = 9.5 V 10 V -1.3 - -1.1 - -0.9 - mA VO = 13.5 V IOH - 10 V IOL 3.5 7.0 15 V VOL - 10 V VOH 3.5 7.0 15 V VIL 5V 10 V VIH HIGH-level input voltage Max Tamb = 25 °C 15 V -3.6 - -3.0 - -2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 µA LOW-level input voltage |IO| < 1 µA HIGH-level output voltage |IO| < 1 µA LOW-level output voltage LOW-level output current II input leakage current IDD supply current |IO| < 1 µA input capacitance - 20 - 20 - 150 µA - 40 - 40 - 300 µA 15 V CI 5V 10 V - 80 - 80 - 600 µA - - - - 7.5 - - pF IO = 0 A HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 8 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 11. Dynamic characteristics Table 9. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter VDD 123 ns + (0.55 ns/pF)CL - 150 300 ns 10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 183 ns + (0.55 ns/pF)CL - 210 420 ns 10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns 62 ns + (0.16 ns/pF)CL - 70 140 ns 173 ns + (0.55 ns/pF)CL - 200 400 ns 69 ns + (0.23 ns/pF)CL - 80 160 ns 52 ns + (0.16 ns/pF)CL - 60 120 ns 5V 113 ns + (0.55 ns/pF)CL - 140 280 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 32 ns + (0.16 ns/pF)CL - 40 80 ns 123 ns + (0.55 ns/pF)CL - 150 300 ns 10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 183 ns + (0.55 ns/pF)CL - 210 420 ns 10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns 15 V 62 ns + (0.16 ns/pF)CL - 70 140 ns 5V 153 ns + (0.55 ns/pF)CL - 180 360 ns 10 V MR to Qn Unit 15 V PL to Qn; see Figure 6 Max 10 V CP0, CP1 to TC; see Figure 6 Typ 5V CP0, CP1 to Qn; see Figure 6 Min 15 V HIGH to LOW propagation delay Extrapolation formula 15 V tPHL Conditions 59 ns + (0.23 ns/pF)CL - 70 140 ns 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V [1] 15 V tPLH LOW to HIGH propagation delay CP0, CP1 to Qn; see Figure 6 CP0, CP1 to TC; see Figure 6 PL to Qn; see Figure 6 5V [1] 15 V An to PL; see Figure 6 - 60 120 ns 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V set-up time see Figure 6 10 ns + (1.00 ns/pF)CL 10 V tt transition time 5V [1] 6 ns + (0.28 ns/pF)CL - 20 40 ns hold time An to PL; see Figure 6 30 0 - ns 10 V 20 0 - ns 15 0 - ns 5V 30 5 - ns 10 V 20 5 - ns 15 V th 5V 15 V tsu 15 5 - ns HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 9 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 9. Dynamic characteristics .continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter Conditions tW CP0 input; LOW; see Figure 6 Unit 40 - ns 40 20 - ns 30 15 - ns 5V 80 40 - ns 10 V 40 20 - ns 15 V CP1 input; HIGH; see Figure 6 Max 15 V pulse width VDD Extrapolation formula Min Typ 5V 80 10 V 30 15 - ns PL = LOW; see Figure 6 - ns 20 - ns 32 16 - ns 5V 130 65 - ns 50 25 - ns 40 20 - ns 6 12 - MHz 10 V 12 25 - MHz 15 V maximum frequency 50 40 15 V fmax 100 10 V MR input; LOW 5V 10 V 15 V PL input; HIGH; see Figure 6 16 32 - MHz 5V [2] [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] In the divide-by-n mode (PL connected to TC), the CP0 or CP1 pulse width must be greater than the maximum HIGH to LOW propagation delay for CP0 or CP1 to TC. Table 10. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 °C. Symbol dynamic power dissipation Typical formula for PD (µW) where: 5V PD = 1000 × fi + (fo × CL) × VDD2 fi = input frequency in MHz, 10 V PD = 4000 × fi + (fo × CL) × VDD2 15 V PD Parameter VDD PD = 10000 × fi + (fo × CL) × VDD fo = output frequency in MHz, 2 CL = output load capacitance in pF, VDD = supply voltage in V, (fo × CL) = sum of the outputs. HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 10 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 12. Waveforms 1/fmax Vl CP0 input VM 0V tW Vl CP1 input VM 0V tW VOH Qn output VM VOL tPLH tPLH tPHL VOH TC output VM VOL tPHL tPLH 001aae724 a. Propagation delays for CP0, CP1 to Qn, and TC, minimum CP0 and CP1 pulse widths and maximum frequency Vl VM PL input 0V tsu th tW Vl VM An input 0V tPLH tPHL VOH 90% Qn output 10% VOL tt tt 001aae723 b. Propagation delays for PL and An to Qn, setup and hold times for PL to An, Qn transition times and minimum PL pulse width Measurement points are given in Table 11. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig 6. Waveforms showing switching times HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 11 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter tW VI 90 % negative pulse VM VM 10 % 0V tf tr VI tr tf 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test data is given in Table 11; Definitions for test circuit: DUT = Device Under Test; CL = Load capacitance, including jig and probe capacitance; RL = Load resistance; RT = Termination resistance, should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit for switching times Table 11. Measurement points and test data Supply voltage Input Load VI 5 V to 15 V VM tr, tf CL RL VDD 0.5VI 20 ns 50 pF 1 k 13. Application information Some examples of HEF4526B HEF4526B applications are: · Divide-by-n counter · Programmable frequency divider HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 12 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter cycle inhibit VDD Q0 Q1 Q2 Q3 PL Q0 Q1 Q2 Q3 PL CF VDD CF MR HEF4526B HEF4526B TC (L.S.D.) CP1 clock MR HEF4526B HEF4526B TC (M.S.D.) CP1 CP0 A0 CP0 A0 A1 A2 A3 A1 A2 A3 Counting cycle: 10 k (4x) S 10 k (4x) n0 S n1 VDD VDD master reset 15 14 . . . n0 . . 1 0 L.S.D. counter n1 . . 1 stop at 0 LOW M.S.D. counter 001aae725 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 8. Typical 2-stage programmable down counter (one cycle) application. f0 = fi/n Q0 Q1 Q2 Q3 PL Q0 Q1 Q2 Q3 PL VDD CF MR CP1 clock CP0 A0 HEF4526B HEF4526B TC MR (L.S.D.) A1 A2 CF CP1 CP0 A0 A3 HEF4526B HEF4526B TC (M.S.D.) A1 A2 A3 Counting cycle: 10 k (4x) S master reset n0 VDD 10 k (4x) S n1 VDD 15 14 . . . . . n0 . . 2 1 0 L.S.D. counter n1 . . 2 1 0 M.S.D. counter 001aae726 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 9. Typical 2-stage programmable frequency divider application HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 13 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 14. Package outline DIP16 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 10. Package outline SOT38-4 (DIP16 DIP16) HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 14 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 076E07 MS-012 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 15 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4526B HEF4526B_4 20090921 Product data sheet - HEF4526B HEF4526B_CNV_3 · The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. · · · · · · · · Modifications: Legal texts have been adapted to the new company name where appropriate. Pin names changed throughout the data sheet. Section 2 "Features" added. Section 3 "Applications" added. Section 4, and Figure 10; Package version SOT38-1 changed to SOT38-4. Section 4; Package SOT74 removed. Section 8 "Limiting values" added, taken from the HEF4000B HEF4000B Family Specifications. Section 10 "Static characteristics" added, taken from the HEF4000B HEF4000B Family Specifications. HEF4526B HEF4526B_CNV_3 19950101 Product specification - HEF4526B HEF4526B_CNV_2 HEF4526B HEF4526B_CNV_2 19950101 Product specification - - HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 16 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft - The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet - A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General - Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use - NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications - Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values - Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale - NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license - Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control - This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4526B HEF4526B_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 - 21 September 2009 17 of 18 HEF4526B HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 September 2009 Document identifier: HEF4526B HEF4526B_4